1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for the r8a774a1 SoC 4 * 5 * Copyright (C) 2018 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/clock/renesas-cpg-mssr.h> 11 12/ { 13 compatible = "renesas,r8a774a1"; 14 #address-cells = <2>; 15 #size-cells = <2>; 16 17 /* 18 * The external audio clocks are configured as 0 Hz fixed frequency 19 * clocks by default. 20 * Boards that provide audio clocks should override them. 21 */ 22 audio_clk_a: audio_clk_a { 23 compatible = "fixed-clock"; 24 #clock-cells = <0>; 25 clock-frequency = <0>; 26 }; 27 28 audio_clk_b: audio_clk_b { 29 compatible = "fixed-clock"; 30 #clock-cells = <0>; 31 clock-frequency = <0>; 32 }; 33 34 audio_clk_c: audio_clk_c { 35 compatible = "fixed-clock"; 36 #clock-cells = <0>; 37 clock-frequency = <0>; 38 }; 39 40 /* External CAN clock - to be overridden by boards that provide it */ 41 can_clk: can { 42 compatible = "fixed-clock"; 43 #clock-cells = <0>; 44 clock-frequency = <0>; 45 }; 46 47 cpus { 48 #address-cells = <1>; 49 #size-cells = <0>; 50 51 a57_0: cpu@0 { 52 compatible = "arm,cortex-a57", "arm,armv8"; 53 reg = <0x0>; 54 device_type = "cpu"; 55 power-domains = <&sysc 0>; 56 next-level-cache = <&L2_CA57>; 57 enable-method = "psci"; 58 clocks =<&cpg CPG_CORE 0>; 59 }; 60 61 a57_1: cpu@1 { 62 compatible = "arm,cortex-a57", "arm,armv8"; 63 reg = <0x1>; 64 device_type = "cpu"; 65 power-domains = <&sysc 1>; 66 next-level-cache = <&L2_CA57>; 67 enable-method = "psci"; 68 clocks =<&cpg CPG_CORE 0>; 69 }; 70 71 L2_CA57: cache-controller-0 { 72 compatible = "cache"; 73 power-domains = <&sysc 12>; 74 cache-unified; 75 cache-level = <2>; 76 }; 77 }; 78 79 extal_clk: extal { 80 compatible = "fixed-clock"; 81 #clock-cells = <0>; 82 /* This value must be overridden by the board */ 83 clock-frequency = <0>; 84 }; 85 86 extalr_clk: extalr { 87 compatible = "fixed-clock"; 88 #clock-cells = <0>; 89 /* This value must be overridden by the board */ 90 clock-frequency = <0>; 91 }; 92 93 /* External PCIe clock - can be overridden by the board */ 94 pcie_bus_clk: pcie_bus { 95 compatible = "fixed-clock"; 96 #clock-cells = <0>; 97 clock-frequency = <0>; 98 }; 99 100 pmu_a57 { 101 compatible = "arm,cortex-a57-pmu"; 102 interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 103 <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 104 interrupt-affinity = <&a57_0>, <&a57_1>; 105 }; 106 107 psci { 108 compatible = "arm,psci-1.0", "arm,psci-0.2"; 109 method = "smc"; 110 }; 111 112 /* External SCIF clock - to be overridden by boards that provide it */ 113 scif_clk: scif { 114 compatible = "fixed-clock"; 115 #clock-cells = <0>; 116 clock-frequency = <0>; 117 }; 118 119 soc { 120 compatible = "simple-bus"; 121 interrupt-parent = <&gic>; 122 #address-cells = <2>; 123 #size-cells = <2>; 124 ranges; 125 126 rwdt: watchdog@e6020000 { 127 compatible = "renesas,r8a774a1-wdt", 128 "renesas,rcar-gen3-wdt"; 129 reg = <0 0xe6020000 0 0x0c>; 130 clocks = <&cpg CPG_MOD 402>; 131 power-domains = <&sysc 32>; 132 resets = <&cpg 402>; 133 status = "disabled"; 134 }; 135 136 pfc: pin-controller@e6060000 { 137 compatible = "renesas,pfc-r8a774a1"; 138 reg = <0 0xe6060000 0 0x50c>; 139 }; 140 141 cpg: clock-controller@e6150000 { 142 compatible = "renesas,r8a774a1-cpg-mssr"; 143 reg = <0 0xe6150000 0 0x0bb0>; 144 clocks = <&extal_clk>, <&extalr_clk>; 145 clock-names = "extal", "extalr"; 146 #clock-cells = <2>; 147 #power-domain-cells = <0>; 148 #reset-cells = <1>; 149 }; 150 151 rst: reset-controller@e6160000 { 152 compatible = "renesas,r8a774a1-rst"; 153 reg = <0 0xe6160000 0 0x018c>; 154 }; 155 156 sysc: system-controller@e6180000 { 157 compatible = "renesas,r8a774a1-sysc"; 158 reg = <0 0xe6180000 0 0x0400>; 159 #power-domain-cells = <1>; 160 }; 161 162 intc_ex: interrupt-controller@e61c0000 { 163 compatible = "renesas,intc-ex-r8a774a1", "renesas,irqc"; 164 #interrupt-cells = <2>; 165 interrupt-controller; 166 reg = <0 0xe61c0000 0 0x200>; 167 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH 168 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH 169 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH 170 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH 171 GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 172 GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 173 clocks = <&cpg CPG_MOD 407>; 174 power-domains = <&sysc 32>; 175 resets = <&cpg 407>; 176 }; 177 178 hscif0: serial@e6540000 { 179 compatible = "renesas,hscif-r8a774a1", 180 "renesas,rcar-gen3-hscif", 181 "renesas,hscif"; 182 reg = <0 0xe6540000 0 0x60>; 183 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 184 clocks = <&cpg CPG_MOD 520>, 185 <&cpg CPG_CORE 19>, 186 <&scif_clk>; 187 clock-names = "fck", "brg_int", "scif_clk"; 188 dmas = <&dmac1 0x31>, <&dmac1 0x30>, 189 <&dmac2 0x31>, <&dmac2 0x30>; 190 dma-names = "tx", "rx", "tx", "rx"; 191 power-domains = <&sysc 32>; 192 resets = <&cpg 520>; 193 status = "disabled"; 194 }; 195 196 hscif1: serial@e6550000 { 197 compatible = "renesas,hscif-r8a774a1", 198 "renesas,rcar-gen3-hscif", 199 "renesas,hscif"; 200 reg = <0 0xe6550000 0 0x60>; 201 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 202 clocks = <&cpg CPG_MOD 519>, 203 <&cpg CPG_CORE 19>, 204 <&scif_clk>; 205 clock-names = "fck", "brg_int", "scif_clk"; 206 dmas = <&dmac1 0x33>, <&dmac1 0x32>, 207 <&dmac2 0x33>, <&dmac2 0x32>; 208 dma-names = "tx", "rx", "tx", "rx"; 209 power-domains = <&sysc 32>; 210 resets = <&cpg 519>; 211 status = "disabled"; 212 }; 213 214 hscif2: serial@e6560000 { 215 compatible = "renesas,hscif-r8a774a1", 216 "renesas,rcar-gen3-hscif", 217 "renesas,hscif"; 218 reg = <0 0xe6560000 0 0x60>; 219 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 220 clocks = <&cpg CPG_MOD 518>, 221 <&cpg CPG_CORE 19>, 222 <&scif_clk>; 223 clock-names = "fck", "brg_int", "scif_clk"; 224 dmas = <&dmac1 0x35>, <&dmac1 0x34>, 225 <&dmac2 0x35>, <&dmac2 0x34>; 226 dma-names = "tx", "rx", "tx", "rx"; 227 power-domains = <&sysc 32>; 228 resets = <&cpg 518>; 229 status = "disabled"; 230 }; 231 232 hscif3: serial@e66a0000 { 233 compatible = "renesas,hscif-r8a774a1", 234 "renesas,rcar-gen3-hscif", 235 "renesas,hscif"; 236 reg = <0 0xe66a0000 0 0x60>; 237 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 238 clocks = <&cpg CPG_MOD 517>, 239 <&cpg CPG_CORE 19>, 240 <&scif_clk>; 241 clock-names = "fck", "brg_int", "scif_clk"; 242 dmas = <&dmac0 0x37>, <&dmac0 0x36>; 243 dma-names = "tx", "rx"; 244 power-domains = <&sysc 32>; 245 resets = <&cpg 517>; 246 status = "disabled"; 247 }; 248 249 hscif4: serial@e66b0000 { 250 compatible = "renesas,hscif-r8a774a1", 251 "renesas,rcar-gen3-hscif", 252 "renesas,hscif"; 253 reg = <0 0xe66b0000 0 0x60>; 254 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 255 clocks = <&cpg CPG_MOD 516>, 256 <&cpg CPG_CORE 19>, 257 <&scif_clk>; 258 clock-names = "fck", "brg_int", "scif_clk"; 259 dmas = <&dmac0 0x39>, <&dmac0 0x38>; 260 dma-names = "tx", "rx"; 261 power-domains = <&sysc 32>; 262 resets = <&cpg 516>; 263 status = "disabled"; 264 }; 265 266 dmac0: dma-controller@e6700000 { 267 compatible = "renesas,dmac-r8a774a1", 268 "renesas,rcar-dmac"; 269 reg = <0 0xe6700000 0 0x10000>; 270 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH 271 GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH 272 GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH 273 GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH 274 GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 275 GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH 276 GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH 277 GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH 278 GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH 279 GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH 280 GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH 281 GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH 282 GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH 283 GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH 284 GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH 285 GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH 286 GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; 287 interrupt-names = "error", 288 "ch0", "ch1", "ch2", "ch3", 289 "ch4", "ch5", "ch6", "ch7", 290 "ch8", "ch9", "ch10", "ch11", 291 "ch12", "ch13", "ch14", "ch15"; 292 clocks = <&cpg CPG_MOD 219>; 293 clock-names = "fck"; 294 power-domains = <&sysc 32>; 295 resets = <&cpg 219>; 296 #dma-cells = <1>; 297 dma-channels = <16>; 298 }; 299 300 dmac1: dma-controller@e7300000 { 301 compatible = "renesas,dmac-r8a774a1", 302 "renesas,rcar-dmac"; 303 reg = <0 0xe7300000 0 0x10000>; 304 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 305 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH 306 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH 307 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH 308 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH 309 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH 310 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH 311 GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH 312 GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH 313 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH 314 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH 315 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH 316 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH 317 GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH 318 GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH 319 GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH 320 GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>; 321 interrupt-names = "error", 322 "ch0", "ch1", "ch2", "ch3", 323 "ch4", "ch5", "ch6", "ch7", 324 "ch8", "ch9", "ch10", "ch11", 325 "ch12", "ch13", "ch14", "ch15"; 326 clocks = <&cpg CPG_MOD 218>; 327 clock-names = "fck"; 328 power-domains = <&sysc 32>; 329 resets = <&cpg 218>; 330 #dma-cells = <1>; 331 dma-channels = <16>; 332 }; 333 334 dmac2: dma-controller@e7310000 { 335 compatible = "renesas,dmac-r8a774a1", 336 "renesas,rcar-dmac"; 337 reg = <0 0xe7310000 0 0x10000>; 338 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH 339 GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH 340 GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH 341 GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH 342 GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH 343 GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH 344 GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH 345 GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH 346 GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH 347 GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH 348 GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH 349 GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH 350 GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH 351 GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH 352 GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH 353 GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH 354 GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>; 355 interrupt-names = "error", 356 "ch0", "ch1", "ch2", "ch3", 357 "ch4", "ch5", "ch6", "ch7", 358 "ch8", "ch9", "ch10", "ch11", 359 "ch12", "ch13", "ch14", "ch15"; 360 clocks = <&cpg CPG_MOD 217>; 361 clock-names = "fck"; 362 power-domains = <&sysc 32>; 363 resets = <&cpg 217>; 364 #dma-cells = <1>; 365 dma-channels = <16>; 366 }; 367 368 avb: ethernet@e6800000 { 369 compatible = "renesas,etheravb-r8a774a1", 370 "renesas,etheravb-rcar-gen3"; 371 reg = <0 0xe6800000 0 0x800>; 372 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 373 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 374 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 375 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 376 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 377 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 378 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 379 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 380 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 381 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 382 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 383 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 384 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 385 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 386 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 387 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 388 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 389 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 390 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 391 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 392 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 393 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 394 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 395 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, 396 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 397 interrupt-names = "ch0", "ch1", "ch2", "ch3", 398 "ch4", "ch5", "ch6", "ch7", 399 "ch8", "ch9", "ch10", "ch11", 400 "ch12", "ch13", "ch14", "ch15", 401 "ch16", "ch17", "ch18", "ch19", 402 "ch20", "ch21", "ch22", "ch23", 403 "ch24"; 404 clocks = <&cpg CPG_MOD 812>; 405 power-domains = <&sysc 32>; 406 resets = <&cpg 812>; 407 phy-mode = "rgmii"; 408 #address-cells = <1>; 409 #size-cells = <0>; 410 status = "disabled"; 411 }; 412 413 scif0: serial@e6e60000 { 414 compatible = "renesas,scif-r8a774a1", 415 "renesas,rcar-gen3-scif", "renesas,scif"; 416 reg = <0 0xe6e60000 0 0x40>; 417 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 418 clocks = <&cpg CPG_MOD 207>, 419 <&cpg CPG_CORE 19>, 420 <&scif_clk>; 421 clock-names = "fck", "brg_int", "scif_clk"; 422 dmas = <&dmac1 0x51>, <&dmac1 0x50>, 423 <&dmac2 0x51>, <&dmac2 0x50>; 424 dma-names = "tx", "rx", "tx", "rx"; 425 power-domains = <&sysc 32>; 426 resets = <&cpg 207>; 427 status = "disabled"; 428 }; 429 430 scif1: serial@e6e68000 { 431 compatible = "renesas,scif-r8a774a1", 432 "renesas,rcar-gen3-scif", "renesas,scif"; 433 reg = <0 0xe6e68000 0 0x40>; 434 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 435 clocks = <&cpg CPG_MOD 206>, 436 <&cpg CPG_CORE 19>, 437 <&scif_clk>; 438 clock-names = "fck", "brg_int", "scif_clk"; 439 dmas = <&dmac1 0x53>, <&dmac1 0x52>, 440 <&dmac2 0x53>, <&dmac2 0x52>; 441 dma-names = "tx", "rx", "tx", "rx"; 442 power-domains = <&sysc 32>; 443 resets = <&cpg 206>; 444 status = "disabled"; 445 }; 446 447 scif2: serial@e6e88000 { 448 compatible = "renesas,scif-r8a774a1", 449 "renesas,rcar-gen3-scif", "renesas,scif"; 450 reg = <0 0xe6e88000 0 0x40>; 451 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 452 clocks = <&cpg CPG_MOD 310>, 453 <&cpg CPG_CORE 19>, 454 <&scif_clk>; 455 clock-names = "fck", "brg_int", "scif_clk"; 456 power-domains = <&sysc 32>; 457 resets = <&cpg 310>; 458 status = "disabled"; 459 }; 460 461 scif3: serial@e6c50000 { 462 compatible = "renesas,scif-r8a774a1", 463 "renesas,rcar-gen3-scif", "renesas,scif"; 464 reg = <0 0xe6c50000 0 0x40>; 465 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 466 clocks = <&cpg CPG_MOD 204>, 467 <&cpg CPG_CORE 19>, 468 <&scif_clk>; 469 clock-names = "fck", "brg_int", "scif_clk"; 470 dmas = <&dmac0 0x57>, <&dmac0 0x56>; 471 dma-names = "tx", "rx"; 472 power-domains = <&sysc 32>; 473 resets = <&cpg 204>; 474 status = "disabled"; 475 }; 476 477 scif4: serial@e6c40000 { 478 compatible = "renesas,scif-r8a774a1", 479 "renesas,rcar-gen3-scif", "renesas,scif"; 480 reg = <0 0xe6c40000 0 0x40>; 481 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 482 clocks = <&cpg CPG_MOD 203>, 483 <&cpg CPG_CORE 19>, 484 <&scif_clk>; 485 clock-names = "fck", "brg_int", "scif_clk"; 486 dmas = <&dmac0 0x59>, <&dmac0 0x58>; 487 dma-names = "tx", "rx"; 488 power-domains = <&sysc 32>; 489 resets = <&cpg 203>; 490 status = "disabled"; 491 }; 492 493 scif5: serial@e6f30000 { 494 compatible = "renesas,scif-r8a774a1", 495 "renesas,rcar-gen3-scif", "renesas,scif"; 496 reg = <0 0xe6f30000 0 0x40>; 497 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 498 clocks = <&cpg CPG_MOD 202>, 499 <&cpg CPG_CORE 19>, 500 <&scif_clk>; 501 clock-names = "fck", "brg_int", "scif_clk"; 502 dmas = <&dmac1 0x5b>, <&dmac1 0x5a>, 503 <&dmac2 0x5b>, <&dmac2 0x5a>; 504 dma-names = "tx", "rx", "tx", "rx"; 505 power-domains = <&sysc 32>; 506 resets = <&cpg 202>; 507 status = "disabled"; 508 }; 509 510 gic: interrupt-controller@f1010000 { 511 compatible = "arm,gic-400"; 512 #interrupt-cells = <3>; 513 #address-cells = <0>; 514 interrupt-controller; 515 reg = <0x0 0xf1010000 0 0x1000>, 516 <0x0 0xf1020000 0 0x20000>, 517 <0x0 0xf1040000 0 0x20000>, 518 <0x0 0xf1060000 0 0x20000>; 519 interrupts = <GIC_PPI 9 520 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; 521 clocks = <&cpg CPG_MOD 408>; 522 clock-names = "clk"; 523 power-domains = <&sysc 32>; 524 resets = <&cpg 408>; 525 }; 526 527 prr: chipid@fff00044 { 528 compatible = "renesas,prr"; 529 reg = <0 0xfff00044 0 4>; 530 }; 531 }; 532 533 timer { 534 compatible = "arm,armv8-timer"; 535 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 536 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 537 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 538 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; 539 }; 540 541 /* External USB clocks - can be overridden by the board */ 542 usb3s0_clk: usb3s0 { 543 compatible = "fixed-clock"; 544 #clock-cells = <0>; 545 clock-frequency = <0>; 546 }; 547 548 usb_extal_clk: usb_extal { 549 compatible = "fixed-clock"; 550 #clock-cells = <0>; 551 clock-frequency = <0>; 552 }; 553}; 554