sdm845.dtsi (407da561244b9d51e6a794d6305ba38ec2c9d907) sdm845.dtsi (d05e342882e4fb2ccd8e4b6af00b0b82e22ad325)
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * SDM845 SoC device tree source
4 *
5 * Copyright (c) 2018, The Linux Foundation. All rights reserved.
6 */
7
8#include <dt-bindings/clock/qcom,camcc-sdm845.h>

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204 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
205 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
206 power-domains = <&CPU_PD0>;
207 power-domain-names = "psci";
208 #cooling-cells = <2>;
209 next-level-cache = <&L2_0>;
210 L2_0: l2-cache {
211 compatible = "cache";
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * SDM845 SoC device tree source
4 *
5 * Copyright (c) 2018, The Linux Foundation. All rights reserved.
6 */
7
8#include <dt-bindings/clock/qcom,camcc-sdm845.h>

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204 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
205 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
206 power-domains = <&CPU_PD0>;
207 power-domain-names = "psci";
208 #cooling-cells = <2>;
209 next-level-cache = <&L2_0>;
210 L2_0: l2-cache {
211 compatible = "cache";
212 cache-level = <2>;
212 next-level-cache = <&L3_0>;
213 L3_0: l3-cache {
214 compatible = "cache";
213 next-level-cache = <&L3_0>;
214 L3_0: l3-cache {
215 compatible = "cache";
216 cache-level = <3>;
215 };
216 };
217 };
218
219 CPU1: cpu@100 {
220 device_type = "cpu";
221 compatible = "qcom,kryo385";
222 reg = <0x0 0x100>;

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228 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
229 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
230 power-domains = <&CPU_PD1>;
231 power-domain-names = "psci";
232 #cooling-cells = <2>;
233 next-level-cache = <&L2_100>;
234 L2_100: l2-cache {
235 compatible = "cache";
217 };
218 };
219 };
220
221 CPU1: cpu@100 {
222 device_type = "cpu";
223 compatible = "qcom,kryo385";
224 reg = <0x0 0x100>;

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230 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
231 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
232 power-domains = <&CPU_PD1>;
233 power-domain-names = "psci";
234 #cooling-cells = <2>;
235 next-level-cache = <&L2_100>;
236 L2_100: l2-cache {
237 compatible = "cache";
238 cache-level = <2>;
236 next-level-cache = <&L3_0>;
237 };
238 };
239
240 CPU2: cpu@200 {
241 device_type = "cpu";
242 compatible = "qcom,kryo385";
243 reg = <0x0 0x200>;

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249 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
250 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
251 power-domains = <&CPU_PD2>;
252 power-domain-names = "psci";
253 #cooling-cells = <2>;
254 next-level-cache = <&L2_200>;
255 L2_200: l2-cache {
256 compatible = "cache";
239 next-level-cache = <&L3_0>;
240 };
241 };
242
243 CPU2: cpu@200 {
244 device_type = "cpu";
245 compatible = "qcom,kryo385";
246 reg = <0x0 0x200>;

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252 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
253 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
254 power-domains = <&CPU_PD2>;
255 power-domain-names = "psci";
256 #cooling-cells = <2>;
257 next-level-cache = <&L2_200>;
258 L2_200: l2-cache {
259 compatible = "cache";
260 cache-level = <2>;
257 next-level-cache = <&L3_0>;
258 };
259 };
260
261 CPU3: cpu@300 {
262 device_type = "cpu";
263 compatible = "qcom,kryo385";
264 reg = <0x0 0x300>;

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270 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
271 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
272 #cooling-cells = <2>;
273 power-domains = <&CPU_PD3>;
274 power-domain-names = "psci";
275 next-level-cache = <&L2_300>;
276 L2_300: l2-cache {
277 compatible = "cache";
261 next-level-cache = <&L3_0>;
262 };
263 };
264
265 CPU3: cpu@300 {
266 device_type = "cpu";
267 compatible = "qcom,kryo385";
268 reg = <0x0 0x300>;

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274 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
275 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
276 #cooling-cells = <2>;
277 power-domains = <&CPU_PD3>;
278 power-domain-names = "psci";
279 next-level-cache = <&L2_300>;
280 L2_300: l2-cache {
281 compatible = "cache";
282 cache-level = <2>;
278 next-level-cache = <&L3_0>;
279 };
280 };
281
282 CPU4: cpu@400 {
283 device_type = "cpu";
284 compatible = "qcom,kryo385";
285 reg = <0x0 0x400>;

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291 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
292 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
293 power-domains = <&CPU_PD4>;
294 power-domain-names = "psci";
295 #cooling-cells = <2>;
296 next-level-cache = <&L2_400>;
297 L2_400: l2-cache {
298 compatible = "cache";
283 next-level-cache = <&L3_0>;
284 };
285 };
286
287 CPU4: cpu@400 {
288 device_type = "cpu";
289 compatible = "qcom,kryo385";
290 reg = <0x0 0x400>;

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296 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
297 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
298 power-domains = <&CPU_PD4>;
299 power-domain-names = "psci";
300 #cooling-cells = <2>;
301 next-level-cache = <&L2_400>;
302 L2_400: l2-cache {
303 compatible = "cache";
304 cache-level = <2>;
299 next-level-cache = <&L3_0>;
300 };
301 };
302
303 CPU5: cpu@500 {
304 device_type = "cpu";
305 compatible = "qcom,kryo385";
306 reg = <0x0 0x500>;

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312 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
313 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
314 power-domains = <&CPU_PD5>;
315 power-domain-names = "psci";
316 #cooling-cells = <2>;
317 next-level-cache = <&L2_500>;
318 L2_500: l2-cache {
319 compatible = "cache";
305 next-level-cache = <&L3_0>;
306 };
307 };
308
309 CPU5: cpu@500 {
310 device_type = "cpu";
311 compatible = "qcom,kryo385";
312 reg = <0x0 0x500>;

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318 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
319 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
320 power-domains = <&CPU_PD5>;
321 power-domain-names = "psci";
322 #cooling-cells = <2>;
323 next-level-cache = <&L2_500>;
324 L2_500: l2-cache {
325 compatible = "cache";
326 cache-level = <2>;
320 next-level-cache = <&L3_0>;
321 };
322 };
323
324 CPU6: cpu@600 {
325 device_type = "cpu";
326 compatible = "qcom,kryo385";
327 reg = <0x0 0x600>;

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333 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
334 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
335 power-domains = <&CPU_PD6>;
336 power-domain-names = "psci";
337 #cooling-cells = <2>;
338 next-level-cache = <&L2_600>;
339 L2_600: l2-cache {
340 compatible = "cache";
327 next-level-cache = <&L3_0>;
328 };
329 };
330
331 CPU6: cpu@600 {
332 device_type = "cpu";
333 compatible = "qcom,kryo385";
334 reg = <0x0 0x600>;

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340 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
341 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
342 power-domains = <&CPU_PD6>;
343 power-domain-names = "psci";
344 #cooling-cells = <2>;
345 next-level-cache = <&L2_600>;
346 L2_600: l2-cache {
347 compatible = "cache";
348 cache-level = <2>;
341 next-level-cache = <&L3_0>;
342 };
343 };
344
345 CPU7: cpu@700 {
346 device_type = "cpu";
347 compatible = "qcom,kryo385";
348 reg = <0x0 0x700>;

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354 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
355 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
356 power-domains = <&CPU_PD7>;
357 power-domain-names = "psci";
358 #cooling-cells = <2>;
359 next-level-cache = <&L2_700>;
360 L2_700: l2-cache {
361 compatible = "cache";
349 next-level-cache = <&L3_0>;
350 };
351 };
352
353 CPU7: cpu@700 {
354 device_type = "cpu";
355 compatible = "qcom,kryo385";
356 reg = <0x0 0x700>;

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362 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
363 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
364 power-domains = <&CPU_PD7>;
365 power-domain-names = "psci";
366 #cooling-cells = <2>;
367 next-level-cache = <&L2_700>;
368 L2_700: l2-cache {
369 compatible = "cache";
370 cache-level = <2>;
362 next-level-cache = <&L3_0>;
363 };
364 };
365
366 cpu-map {
367 cluster0 {
368 core0 {
369 cpu = <&CPU0>;

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691 };
692
693 cpu4_opp32: opp-2803200000 {
694 opp-hz = /bits/ 64 <2803200000>;
695 opp-peak-kBps = <7216000 25497600>;
696 };
697 };
698
371 next-level-cache = <&L3_0>;
372 };
373 };
374
375 cpu-map {
376 cluster0 {
377 core0 {
378 cpu = <&CPU0>;

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700 };
701
702 cpu4_opp32: opp-2803200000 {
703 opp-hz = /bits/ 64 <2803200000>;
704 opp-peak-kBps = <7216000 25497600>;
705 };
706 };
707
708 dsi_opp_table: opp-table-dsi {
709 compatible = "operating-points-v2";
710
711 opp-19200000 {
712 opp-hz = /bits/ 64 <19200000>;
713 required-opps = <&rpmhpd_opp_min_svs>;
714 };
715
716 opp-180000000 {
717 opp-hz = /bits/ 64 <180000000>;
718 required-opps = <&rpmhpd_opp_low_svs>;
719 };
720
721 opp-275000000 {
722 opp-hz = /bits/ 64 <275000000>;
723 required-opps = <&rpmhpd_opp_svs>;
724 };
725
726 opp-328580000 {
727 opp-hz = /bits/ 64 <328580000>;
728 required-opps = <&rpmhpd_opp_svs_l1>;
729 };
730
731 opp-358000000 {
732 opp-hz = /bits/ 64 <358000000>;
733 required-opps = <&rpmhpd_opp_nom>;
734 };
735 };
736
737 qspi_opp_table: opp-table-qspi {
738 compatible = "operating-points-v2";
739
740 opp-19200000 {
741 opp-hz = /bits/ 64 <19200000>;
742 required-opps = <&rpmhpd_opp_min_svs>;
743 };
744
745 opp-100000000 {
746 opp-hz = /bits/ 64 <100000000>;
747 required-opps = <&rpmhpd_opp_low_svs>;
748 };
749
750 opp-150000000 {
751 opp-hz = /bits/ 64 <150000000>;
752 required-opps = <&rpmhpd_opp_svs>;
753 };
754
755 opp-300000000 {
756 opp-hz = /bits/ 64 <300000000>;
757 required-opps = <&rpmhpd_opp_nom>;
758 };
759 };
760
761 qup_opp_table: opp-table-qup {
762 compatible = "operating-points-v2";
763
764 opp-50000000 {
765 opp-hz = /bits/ 64 <50000000>;
766 required-opps = <&rpmhpd_opp_min_svs>;
767 };
768
769 opp-75000000 {
770 opp-hz = /bits/ 64 <75000000>;
771 required-opps = <&rpmhpd_opp_low_svs>;
772 };
773
774 opp-100000000 {
775 opp-hz = /bits/ 64 <100000000>;
776 required-opps = <&rpmhpd_opp_svs>;
777 };
778
779 opp-128000000 {
780 opp-hz = /bits/ 64 <128000000>;
781 required-opps = <&rpmhpd_opp_nom>;
782 };
783 };
784
699 pmu {
700 compatible = "arm,armv8-pmuv3";
701 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
702 };
703
704 timer {
705 compatible = "arm,armv8-timer";
706 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,

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1120
1121 rng: rng@793000 {
1122 compatible = "qcom,prng-ee";
1123 reg = <0 0x00793000 0 0x1000>;
1124 clocks = <&gcc GCC_PRNG_AHB_CLK>;
1125 clock-names = "core";
1126 };
1127
785 pmu {
786 compatible = "arm,armv8-pmuv3";
787 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
788 };
789
790 timer {
791 compatible = "arm,armv8-timer";
792 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,

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1206
1207 rng: rng@793000 {
1208 compatible = "qcom,prng-ee";
1209 reg = <0 0x00793000 0 0x1000>;
1210 clocks = <&gcc GCC_PRNG_AHB_CLK>;
1211 clock-names = "core";
1212 };
1213
1128 qup_opp_table: opp-table-qup {
1129 compatible = "operating-points-v2";
1130
1131 opp-50000000 {
1132 opp-hz = /bits/ 64 <50000000>;
1133 required-opps = <&rpmhpd_opp_min_svs>;
1134 };
1135
1136 opp-75000000 {
1137 opp-hz = /bits/ 64 <75000000>;
1138 required-opps = <&rpmhpd_opp_low_svs>;
1139 };
1140
1141 opp-100000000 {
1142 opp-hz = /bits/ 64 <100000000>;
1143 required-opps = <&rpmhpd_opp_svs>;
1144 };
1145
1146 opp-128000000 {
1147 opp-hz = /bits/ 64 <128000000>;
1148 required-opps = <&rpmhpd_opp_nom>;
1149 };
1150 };
1151
1152 gpi_dma0: dma-controller@800000 {
1153 #dma-cells = <3>;
1154 compatible = "qcom,sdm845-gpi-dma";
1155 reg = <0 0x00800000 0 0x60000>;
1156 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
1157 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
1158 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
1159 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,

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1631 operating-points-v2 = <&qup_opp_table>;
1632 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1633 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1634 interconnect-names = "qup-core", "qup-config";
1635 status = "disabled";
1636 };
1637 };
1638
1214 gpi_dma0: dma-controller@800000 {
1215 #dma-cells = <3>;
1216 compatible = "qcom,sdm845-gpi-dma";
1217 reg = <0 0x00800000 0 0x60000>;
1218 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
1219 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
1220 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
1221 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,

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1693 operating-points-v2 = <&qup_opp_table>;
1694 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1695 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1696 interconnect-names = "qup-core", "qup-config";
1697 status = "disabled";
1698 };
1699 };
1700
1639 gpi_dma1: dma-controller@0xa00000 {
1701 gpi_dma1: dma-controller@a00000 {
1640 #dma-cells = <3>;
1641 compatible = "qcom,sdm845-gpi-dma";
1642 reg = <0 0x00a00000 0 0x60000>;
1643 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
1644 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
1645 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
1646 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
1647 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,

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2132
2133 llcc: system-cache-controller@1100000 {
2134 compatible = "qcom,sdm845-llcc";
2135 reg = <0 0x01100000 0 0x31000>, <0 0x01300000 0 0x50000>;
2136 reg-names = "llcc_base", "llcc_broadcast_base";
2137 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
2138 };
2139
1702 #dma-cells = <3>;
1703 compatible = "qcom,sdm845-gpi-dma";
1704 reg = <0 0x00a00000 0 0x60000>;
1705 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
1706 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
1707 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
1708 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
1709 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,

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2194
2195 llcc: system-cache-controller@1100000 {
2196 compatible = "qcom,sdm845-llcc";
2197 reg = <0 0x01100000 0 0x31000>, <0 0x01300000 0 0x50000>;
2198 reg-names = "llcc_base", "llcc_broadcast_base";
2199 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
2200 };
2201
2202 dma@10a2000 {
2203 compatible = "qcom,sdm845-dcc", "qcom,dcc";
2204 reg = <0x0 0x010a2000 0x0 0x1000>,
2205 <0x0 0x010ae000 0x0 0x2000>;
2206 };
2207
2140 pmu@114a000 {
2141 compatible = "qcom,sdm845-llcc-bwmon";
2142 reg = <0 0x0114a000 0 0x1000>;
2143 interrupts = <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>;
2144 interconnects = <&mem_noc MASTER_LLCC 3 &mem_noc SLAVE_EBI1 3>;
2145
2146 operating-points-v2 = <&llcc_bwmon_opp_table>;
2147

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2636 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
2637 gpio-controller;
2638 #gpio-cells = <2>;
2639 interrupt-controller;
2640 #interrupt-cells = <2>;
2641 gpio-ranges = <&tlmm 0 0 151>;
2642 wakeup-parent = <&pdc_intc>;
2643
2208 pmu@114a000 {
2209 compatible = "qcom,sdm845-llcc-bwmon";
2210 reg = <0 0x0114a000 0 0x1000>;
2211 interrupts = <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>;
2212 interconnects = <&mem_noc MASTER_LLCC 3 &mem_noc SLAVE_EBI1 3>;
2213
2214 operating-points-v2 = <&llcc_bwmon_opp_table>;
2215

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2704 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
2705 gpio-controller;
2706 #gpio-cells = <2>;
2707 interrupt-controller;
2708 #interrupt-cells = <2>;
2709 gpio-ranges = <&tlmm 0 0 151>;
2710 wakeup-parent = <&pdc_intc>;
2711
2644 cci0_default: cci0-default {
2712 cci0_default: cci0-default-state {
2645 /* SDA, SCL */
2646 pins = "gpio17", "gpio18";
2647 function = "cci_i2c";
2648
2649 bias-pull-up;
2650 drive-strength = <2>; /* 2 mA */
2651 };
2652
2713 /* SDA, SCL */
2714 pins = "gpio17", "gpio18";
2715 function = "cci_i2c";
2716
2717 bias-pull-up;
2718 drive-strength = <2>; /* 2 mA */
2719 };
2720
2653 cci0_sleep: cci0-sleep {
2721 cci0_sleep: cci0-sleep-state {
2654 /* SDA, SCL */
2655 pins = "gpio17", "gpio18";
2656 function = "cci_i2c";
2657
2658 drive-strength = <2>; /* 2 mA */
2659 bias-pull-down;
2660 };
2661
2722 /* SDA, SCL */
2723 pins = "gpio17", "gpio18";
2724 function = "cci_i2c";
2725
2726 drive-strength = <2>; /* 2 mA */
2727 bias-pull-down;
2728 };
2729
2662 cci1_default: cci1-default {
2730 cci1_default: cci1-default-state {
2663 /* SDA, SCL */
2664 pins = "gpio19", "gpio20";
2665 function = "cci_i2c";
2666
2667 bias-pull-up;
2668 drive-strength = <2>; /* 2 mA */
2669 };
2670
2731 /* SDA, SCL */
2732 pins = "gpio19", "gpio20";
2733 function = "cci_i2c";
2734
2735 bias-pull-up;
2736 drive-strength = <2>; /* 2 mA */
2737 };
2738
2671 cci1_sleep: cci1-sleep {
2739 cci1_sleep: cci1-sleep-state {
2672 /* SDA, SCL */
2673 pins = "gpio19", "gpio20";
2674 function = "cci_i2c";
2675
2676 drive-strength = <2>; /* 2 mA */
2677 bias-pull-down;
2678 };
2679
2740 /* SDA, SCL */
2741 pins = "gpio19", "gpio20";
2742 function = "cci_i2c";
2743
2744 drive-strength = <2>; /* 2 mA */
2745 bias-pull-down;
2746 };
2747
2680 qspi_clk: qspi-clk {
2681 pinmux {
2682 pins = "gpio95";
2683 function = "qspi_clk";
2684 };
2748 qspi_clk: qspi-clk-state {
2749 pins = "gpio95";
2750 function = "qspi_clk";
2685 };
2686
2751 };
2752
2687 qspi_cs0: qspi-cs0 {
2688 pinmux {
2689 pins = "gpio90";
2690 function = "qspi_cs";
2691 };
2753 qspi_cs0: qspi-cs0-state {
2754 pins = "gpio90";
2755 function = "qspi_cs";
2692 };
2693
2756 };
2757
2694 qspi_cs1: qspi-cs1 {
2695 pinmux {
2696 pins = "gpio89";
2697 function = "qspi_cs";
2698 };
2758 qspi_cs1: qspi-cs1-state {
2759 pins = "gpio89";
2760 function = "qspi_cs";
2699 };
2700
2761 };
2762
2701 qspi_data01: qspi-data01 {
2702 pinmux-data {
2703 pins = "gpio91", "gpio92";
2704 function = "qspi_data";
2705 };
2763 qspi_data01: qspi-data01-state {
2764 pins = "gpio91", "gpio92";
2765 function = "qspi_data";
2706 };
2707
2766 };
2767
2708 qspi_data12: qspi-data12 {
2709 pinmux-data {
2710 pins = "gpio93", "gpio94";
2711 function = "qspi_data";
2712 };
2768 qspi_data12: qspi-data12-state {
2769 pins = "gpio93", "gpio94";
2770 function = "qspi_data";
2713 };
2714
2771 };
2772
2715 qup_i2c0_default: qup-i2c0-default {
2716 pinmux {
2717 pins = "gpio0", "gpio1";
2718 function = "qup0";
2719 };
2773 qup_i2c0_default: qup-i2c0-default-state {
2774 pins = "gpio0", "gpio1";
2775 function = "qup0";
2720 };
2721
2776 };
2777
2722 qup_i2c1_default: qup-i2c1-default {
2723 pinmux {
2724 pins = "gpio17", "gpio18";
2725 function = "qup1";
2726 };
2778 qup_i2c1_default: qup-i2c1-default-state {
2779 pins = "gpio17", "gpio18";
2780 function = "qup1";
2727 };
2728
2781 };
2782
2729 qup_i2c2_default: qup-i2c2-default {
2730 pinmux {
2731 pins = "gpio27", "gpio28";
2732 function = "qup2";
2733 };
2783 qup_i2c2_default: qup-i2c2-default-state {
2784 pins = "gpio27", "gpio28";
2785 function = "qup2";
2734 };
2735
2786 };
2787
2736 qup_i2c3_default: qup-i2c3-default {
2737 pinmux {
2738 pins = "gpio41", "gpio42";
2739 function = "qup3";
2740 };
2788 qup_i2c3_default: qup-i2c3-default-state {
2789 pins = "gpio41", "gpio42";
2790 function = "qup3";
2741 };
2742
2791 };
2792
2743 qup_i2c4_default: qup-i2c4-default {
2744 pinmux {
2745 pins = "gpio89", "gpio90";
2746 function = "qup4";
2747 };
2793 qup_i2c4_default: qup-i2c4-default-state {
2794 pins = "gpio89", "gpio90";
2795 function = "qup4";
2748 };
2749
2796 };
2797
2750 qup_i2c5_default: qup-i2c5-default {
2751 pinmux {
2752 pins = "gpio85", "gpio86";
2753 function = "qup5";
2754 };
2798 qup_i2c5_default: qup-i2c5-default-state {
2799 pins = "gpio85", "gpio86";
2800 function = "qup5";
2755 };
2756
2801 };
2802
2757 qup_i2c6_default: qup-i2c6-default {
2758 pinmux {
2759 pins = "gpio45", "gpio46";
2760 function = "qup6";
2761 };
2803 qup_i2c6_default: qup-i2c6-default-state {
2804 pins = "gpio45", "gpio46";
2805 function = "qup6";
2762 };
2763
2806 };
2807
2764 qup_i2c7_default: qup-i2c7-default {
2765 pinmux {
2766 pins = "gpio93", "gpio94";
2767 function = "qup7";
2768 };
2808 qup_i2c7_default: qup-i2c7-default-state {
2809 pins = "gpio93", "gpio94";
2810 function = "qup7";
2769 };
2770
2811 };
2812
2771 qup_i2c8_default: qup-i2c8-default {
2772 pinmux {
2773 pins = "gpio65", "gpio66";
2774 function = "qup8";
2775 };
2813 qup_i2c8_default: qup-i2c8-default-state {
2814 pins = "gpio65", "gpio66";
2815 function = "qup8";
2776 };
2777
2816 };
2817
2778 qup_i2c9_default: qup-i2c9-default {
2779 pinmux {
2780 pins = "gpio6", "gpio7";
2781 function = "qup9";
2782 };
2818 qup_i2c9_default: qup-i2c9-default-state {
2819 pins = "gpio6", "gpio7";
2820 function = "qup9";
2783 };
2784
2821 };
2822
2785 qup_i2c10_default: qup-i2c10-default {
2786 pinmux {
2787 pins = "gpio55", "gpio56";
2788 function = "qup10";
2789 };
2823 qup_i2c10_default: qup-i2c10-default-state {
2824 pins = "gpio55", "gpio56";
2825 function = "qup10";
2790 };
2791
2826 };
2827
2792 qup_i2c11_default: qup-i2c11-default {
2793 pinmux {
2794 pins = "gpio31", "gpio32";
2795 function = "qup11";
2796 };
2828 qup_i2c11_default: qup-i2c11-default-state {
2829 pins = "gpio31", "gpio32";
2830 function = "qup11";
2797 };
2798
2831 };
2832
2799 qup_i2c12_default: qup-i2c12-default {
2800 pinmux {
2801 pins = "gpio49", "gpio50";
2802 function = "qup12";
2803 };
2833 qup_i2c12_default: qup-i2c12-default-state {
2834 pins = "gpio49", "gpio50";
2835 function = "qup12";
2804 };
2805
2836 };
2837
2806 qup_i2c13_default: qup-i2c13-default {
2807 pinmux {
2808 pins = "gpio105", "gpio106";
2809 function = "qup13";
2810 };
2838 qup_i2c13_default: qup-i2c13-default-state {
2839 pins = "gpio105", "gpio106";
2840 function = "qup13";
2811 };
2812
2841 };
2842
2813 qup_i2c14_default: qup-i2c14-default {
2814 pinmux {
2815 pins = "gpio33", "gpio34";
2816 function = "qup14";
2817 };
2843 qup_i2c14_default: qup-i2c14-default-state {
2844 pins = "gpio33", "gpio34";
2845 function = "qup14";
2818 };
2819
2846 };
2847
2820 qup_i2c15_default: qup-i2c15-default {
2821 pinmux {
2822 pins = "gpio81", "gpio82";
2823 function = "qup15";
2824 };
2848 qup_i2c15_default: qup-i2c15-default-state {
2849 pins = "gpio81", "gpio82";
2850 function = "qup15";
2825 };
2826
2851 };
2852
2827 qup_spi0_default: qup-spi0-default {
2828 pinmux {
2829 pins = "gpio0", "gpio1",
2830 "gpio2", "gpio3";
2831 function = "qup0";
2832 };
2853 qup_spi0_default: qup-spi0-default-state {
2854 pins = "gpio0", "gpio1", "gpio2", "gpio3";
2855 function = "qup0";
2856 drive-strength = <6>;
2857 bias-disable;
2858 };
2833
2859
2834 config {
2835 pins = "gpio0", "gpio1",
2836 "gpio2", "gpio3";
2837 drive-strength = <6>;
2838 bias-disable;
2839 };
2860 qup_spi1_default: qup-spi1-default-state {
2861 pins = "gpio17", "gpio18", "gpio19", "gpio20";
2862 function = "qup1";
2840 };
2841
2863 };
2864
2842 qup_spi1_default: qup-spi1-default {
2843 pinmux {
2844 pins = "gpio17", "gpio18",
2845 "gpio19", "gpio20";
2846 function = "qup1";
2847 };
2865 qup_spi2_default: qup-spi2-default-state {
2866 pins = "gpio27", "gpio28", "gpio29", "gpio30";
2867 function = "qup2";
2848 };
2849
2868 };
2869
2850 qup_spi2_default: qup-spi2-default {
2851 pinmux {
2852 pins = "gpio27", "gpio28",
2853 "gpio29", "gpio30";
2854 function = "qup2";
2855 };
2870 qup_spi3_default: qup-spi3-default-state {
2871 pins = "gpio41", "gpio42", "gpio43", "gpio44";
2872 function = "qup3";
2856 };
2857
2873 };
2874
2858 qup_spi3_default: qup-spi3-default {
2859 pinmux {
2860 pins = "gpio41", "gpio42",
2861 "gpio43", "gpio44";
2862 function = "qup3";
2863 };
2875 qup_spi4_default: qup-spi4-default-state {
2876 pins = "gpio89", "gpio90", "gpio91", "gpio92";
2877 function = "qup4";
2864 };
2865
2878 };
2879
2866 qup_spi4_default: qup-spi4-default {
2867 pinmux {
2868 pins = "gpio89", "gpio90",
2869 "gpio91", "gpio92";
2870 function = "qup4";
2871 };
2880 qup_spi5_default: qup-spi5-default-state {
2881 pins = "gpio85", "gpio86", "gpio87", "gpio88";
2882 function = "qup5";
2872 };
2873
2883 };
2884
2874 qup_spi5_default: qup-spi5-default {
2875 pinmux {
2876 pins = "gpio85", "gpio86",
2877 "gpio87", "gpio88";
2878 function = "qup5";
2879 };
2885 qup_spi6_default: qup-spi6-default-state {
2886 pins = "gpio45", "gpio46", "gpio47", "gpio48";
2887 function = "qup6";
2880 };
2881
2888 };
2889
2882 qup_spi6_default: qup-spi6-default {
2883 pinmux {
2884 pins = "gpio45", "gpio46",
2885 "gpio47", "gpio48";
2886 function = "qup6";
2887 };
2890 qup_spi7_default: qup-spi7-default-state {
2891 pins = "gpio93", "gpio94", "gpio95", "gpio96";
2892 function = "qup7";
2888 };
2889
2893 };
2894
2890 qup_spi7_default: qup-spi7-default {
2891 pinmux {
2892 pins = "gpio93", "gpio94",
2893 "gpio95", "gpio96";
2894 function = "qup7";
2895 };
2895 qup_spi8_default: qup-spi8-default-state {
2896 pins = "gpio65", "gpio66", "gpio67", "gpio68";
2897 function = "qup8";
2896 };
2897
2898 };
2899
2898 qup_spi8_default: qup-spi8-default {
2899 pinmux {
2900 pins = "gpio65", "gpio66",
2901 "gpio67", "gpio68";
2902 function = "qup8";
2903 };
2900 qup_spi9_default: qup-spi9-default-state {
2901 pins = "gpio6", "gpio7", "gpio4", "gpio5";
2902 function = "qup9";
2904 };
2905
2903 };
2904
2906 qup_spi9_default: qup-spi9-default {
2907 pinmux {
2908 pins = "gpio6", "gpio7",
2909 "gpio4", "gpio5";
2910 function = "qup9";
2911 };
2905 qup_spi10_default: qup-spi10-default-state {
2906 pins = "gpio55", "gpio56", "gpio53", "gpio54";
2907 function = "qup10";
2912 };
2913
2908 };
2909
2914 qup_spi10_default: qup-spi10-default {
2915 pinmux {
2916 pins = "gpio55", "gpio56",
2917 "gpio53", "gpio54";
2918 function = "qup10";
2919 };
2910 qup_spi11_default: qup-spi11-default-state {
2911 pins = "gpio31", "gpio32", "gpio33", "gpio34";
2912 function = "qup11";
2920 };
2921
2913 };
2914
2922 qup_spi11_default: qup-spi11-default {
2923 pinmux {
2924 pins = "gpio31", "gpio32",
2925 "gpio33", "gpio34";
2926 function = "qup11";
2927 };
2915 qup_spi12_default: qup-spi12-default-state {
2916 pins = "gpio49", "gpio50", "gpio51", "gpio52";
2917 function = "qup12";
2928 };
2929
2918 };
2919
2930 qup_spi12_default: qup-spi12-default {
2931 pinmux {
2932 pins = "gpio49", "gpio50",
2933 "gpio51", "gpio52";
2934 function = "qup12";
2935 };
2920 qup_spi13_default: qup-spi13-default-state {
2921 pins = "gpio105", "gpio106", "gpio107", "gpio108";
2922 function = "qup13";
2936 };
2937
2923 };
2924
2938 qup_spi13_default: qup-spi13-default {
2939 pinmux {
2940 pins = "gpio105", "gpio106",
2941 "gpio107", "gpio108";
2942 function = "qup13";
2943 };
2925 qup_spi14_default: qup-spi14-default-state {
2926 pins = "gpio33", "gpio34", "gpio31", "gpio32";
2927 function = "qup14";
2944 };
2945
2928 };
2929
2946 qup_spi14_default: qup-spi14-default {
2947 pinmux {
2948 pins = "gpio33", "gpio34",
2949 "gpio31", "gpio32";
2950 function = "qup14";
2951 };
2930 qup_spi15_default: qup-spi15-default-state {
2931 pins = "gpio81", "gpio82", "gpio83", "gpio84";
2932 function = "qup15";
2952 };
2953
2933 };
2934
2954 qup_spi15_default: qup-spi15-default {
2955 pinmux {
2956 pins = "gpio81", "gpio82",
2957 "gpio83", "gpio84";
2958 function = "qup15";
2935 qup_uart0_default: qup-uart0-default-state {
2936 qup_uart0_tx: tx-pins {
2937 pins = "gpio2";
2938 function = "qup0";
2959 };
2939 };
2960 };
2961
2940
2962 qup_uart0_default: qup-uart0-default {
2963 pinmux {
2964 pins = "gpio2", "gpio3";
2941 qup_uart0_rx: rx-pins {
2942 pins = "gpio3";
2965 function = "qup0";
2966 };
2967 };
2968
2943 function = "qup0";
2944 };
2945 };
2946
2969 qup_uart1_default: qup-uart1-default {
2970 pinmux {
2971 pins = "gpio19", "gpio20";
2947 qup_uart1_default: qup-uart1-default-state {
2948 qup_uart1_tx: tx-pins {
2949 pins = "gpio19";
2972 function = "qup1";
2973 };
2950 function = "qup1";
2951 };
2952
2953 qup_uart1_rx: rx-pins {
2954 pins = "gpio20";
2955 function = "qup1";
2956 };
2974 };
2975
2957 };
2958
2976 qup_uart2_default: qup-uart2-default {
2977 pinmux {
2978 pins = "gpio29", "gpio30";
2959 qup_uart2_default: qup-uart2-default-state {
2960 qup_uart2_tx: tx-pins {
2961 pins = "gpio29";
2979 function = "qup2";
2980 };
2962 function = "qup2";
2963 };
2964
2965 qup_uart2_rx: rx-pins {
2966 pins = "gpio30";
2967 function = "qup2";
2968 };
2981 };
2982
2969 };
2970
2983 qup_uart3_default: qup-uart3-default {
2984 pinmux {
2985 pins = "gpio43", "gpio44";
2971 qup_uart3_default: qup-uart3-default-state {
2972 qup_uart3_tx: tx-pins {
2973 pins = "gpio43";
2986 function = "qup3";
2987 };
2974 function = "qup3";
2975 };
2976
2977 qup_uart3_rx: rx-pins {
2978 pins = "gpio44";
2979 function = "qup3";
2980 };
2988 };
2989
2981 };
2982
2990 qup_uart4_default: qup-uart4-default {
2991 pinmux {
2992 pins = "gpio91", "gpio92";
2983 qup_uart3_4pin: qup-uart3-4pin-state {
2984 qup_uart3_4pin_cts: cts-pins {
2985 pins = "gpio41";
2986 function = "qup3";
2987 };
2988
2989 qup_uart3_4pin_rts_tx: rts-tx-pins {
2990 pins = "gpio42", "gpio43";
2991 function = "qup3";
2992 };
2993
2994 qup_uart3_4pin_rx: rx-pins {
2995 pins = "gpio44";
2996 function = "qup3";
2997 };
2998 };
2999
3000 qup_uart4_default: qup-uart4-default-state {
3001 qup_uart4_tx: tx-pins {
3002 pins = "gpio91";
2993 function = "qup4";
2994 };
3003 function = "qup4";
3004 };
3005
3006 qup_uart4_rx: rx-pins {
3007 pins = "gpio92";
3008 function = "qup4";
3009 };
2995 };
2996
3010 };
3011
2997 qup_uart5_default: qup-uart5-default {
2998 pinmux {
2999 pins = "gpio87", "gpio88";
3012 qup_uart5_default: qup-uart5-default-state {
3013 qup_uart5_tx: tx-pins {
3014 pins = "gpio87";
3000 function = "qup5";
3001 };
3015 function = "qup5";
3016 };
3017
3018 qup_uart5_rx: rx-pins {
3019 pins = "gpio88";
3020 function = "qup5";
3021 };
3002 };
3003
3022 };
3023
3004 qup_uart6_default: qup-uart6-default {
3005 pinmux {
3006 pins = "gpio47", "gpio48";
3024 qup_uart6_default: qup-uart6-default-state {
3025 qup_uart6_tx: tx-pins {
3026 pins = "gpio47";
3007 function = "qup6";
3008 };
3027 function = "qup6";
3028 };
3029
3030 qup_uart6_rx: rx-pins {
3031 pins = "gpio48";
3032 function = "qup6";
3033 };
3009 };
3010
3011 qup_uart6_4pin: qup-uart6-4pin-state {
3034 };
3035
3036 qup_uart6_4pin: qup-uart6-4pin-state {
3012
3013 cts-pins {
3037 qup_uart6_4pin_cts: cts-pins {
3014 pins = "gpio45";
3015 function = "qup6";
3016 bias-pull-down;
3017 };
3018
3038 pins = "gpio45";
3039 function = "qup6";
3040 bias-pull-down;
3041 };
3042
3019 rts-tx-pins {
3043 qup_uart6_4pin_rts_tx: rts-tx-pins {
3020 pins = "gpio46", "gpio47";
3021 function = "qup6";
3022 drive-strength = <2>;
3023 bias-disable;
3024 };
3025
3044 pins = "gpio46", "gpio47";
3045 function = "qup6";
3046 drive-strength = <2>;
3047 bias-disable;
3048 };
3049
3026 rx-pins {
3050 qup_uart6_4pin_rx: rx-pins {
3027 pins = "gpio48";
3028 function = "qup6";
3029 bias-pull-up;
3030 };
3031 };
3032
3051 pins = "gpio48";
3052 function = "qup6";
3053 bias-pull-up;
3054 };
3055 };
3056
3033 qup_uart7_default: qup-uart7-default {
3034 pinmux {
3035 pins = "gpio95", "gpio96";
3057 qup_uart7_default: qup-uart7-default-state {
3058 qup_uart7_tx: tx-pins {
3059 pins = "gpio95";
3036 function = "qup7";
3037 };
3060 function = "qup7";
3061 };
3062
3063 qup_uart7_rx: rx-pins {
3064 pins = "gpio96";
3065 function = "qup7";
3066 };
3038 };
3039
3067 };
3068
3040 qup_uart8_default: qup-uart8-default {
3041 pinmux {
3042 pins = "gpio67", "gpio68";
3069 qup_uart8_default: qup-uart8-default-state {
3070 qup_uart8_tx: tx-pins {
3071 pins = "gpio67";
3043 function = "qup8";
3044 };
3072 function = "qup8";
3073 };
3045 };
3046
3074
3047 qup_uart9_default: qup-uart9-default {
3048 pinmux {
3049 pins = "gpio4", "gpio5";
3050 function = "qup9";
3075 qup_uart8_rx: rx-pins {
3076 pins = "gpio68";
3077 function = "qup8";
3051 };
3052 };
3053
3078 };
3079 };
3080
3054 qup_uart10_default: qup-uart10-default {
3055 pinmux {
3056 pins = "gpio53", "gpio54";
3057 function = "qup10";
3081 qup_uart9_default: qup-uart9-default-state {
3082 qup_uart9_tx: tx-pins {
3083 pins = "gpio4";
3084 function = "qup9";
3058 };
3085 };
3059 };
3060
3086
3061 qup_uart11_default: qup-uart11-default {
3062 pinmux {
3063 pins = "gpio33", "gpio34";
3064 function = "qup11";
3087 qup_uart9_rx: rx-pins {
3088 pins = "gpio5";
3089 function = "qup9";
3065 };
3066 };
3067
3090 };
3091 };
3092
3068 qup_uart12_default: qup-uart12-default {
3069 pinmux {
3070 pins = "gpio51", "gpio52";
3071 function = "qup12";
3093 qup_uart10_default: qup-uart10-default-state {
3094 qup_uart10_tx: tx-pins {
3095 pins = "gpio53";
3096 function = "qup10";
3072 };
3097 };
3073 };
3074
3098
3075 qup_uart13_default: qup-uart13-default {
3076 pinmux {
3077 pins = "gpio107", "gpio108";
3078 function = "qup13";
3099 qup_uart10_rx: rx-pins {
3100 pins = "gpio54";
3101 function = "qup10";
3079 };
3080 };
3081
3102 };
3103 };
3104
3082 qup_uart14_default: qup-uart14-default {
3083 pinmux {
3084 pins = "gpio31", "gpio32";
3085 function = "qup14";
3105 qup_uart11_default: qup-uart11-default-state {
3106 qup_uart11_tx: tx-pins {
3107 pins = "gpio33";
3108 function = "qup11";
3086 };
3109 };
3087 };
3088
3110
3089 qup_uart15_default: qup-uart15-default {
3090 pinmux {
3091 pins = "gpio83", "gpio84";
3092 function = "qup15";
3111 qup_uart11_rx: rx-pins {
3112 pins = "gpio34";
3113 function = "qup11";
3093 };
3094 };
3095
3114 };
3115 };
3116
3096 quat_mi2s_sleep: quat_mi2s_sleep {
3097 mux {
3098 pins = "gpio58", "gpio59";
3099 function = "gpio";
3117 qup_uart12_default: qup-uart12-default-state {
3118 qup_uart12_tx: tx-pins {
3119 pins = "gpio51";
3120 function = "qup0";
3100 };
3101
3121 };
3122
3102 config {
3103 pins = "gpio58", "gpio59";
3104 drive-strength = <2>;
3105 bias-pull-down;
3106 input-enable;
3123 qup_uart12_rx: rx-pins {
3124 pins = "gpio52";
3125 function = "qup0";
3107 };
3108 };
3109
3126 };
3127 };
3128
3110 quat_mi2s_active: quat_mi2s_active {
3111 mux {
3112 pins = "gpio58", "gpio59";
3113 function = "qua_mi2s";
3129 qup_uart13_default: qup-uart13-default-state {
3130 qup_uart13_tx: tx-pins {
3131 pins = "gpio107";
3132 function = "qup13";
3114 };
3115
3133 };
3134
3116 config {
3117 pins = "gpio58", "gpio59";
3118 drive-strength = <8>;
3119 bias-disable;
3120 output-high;
3135 qup_uart13_rx: rx-pins {
3136 pins = "gpio108";
3137 function = "qup13";
3121 };
3122 };
3123
3138 };
3139 };
3140
3124 quat_mi2s_sd0_sleep: quat_mi2s_sd0_sleep {
3125 mux {
3126 pins = "gpio60";
3127 function = "gpio";
3141 qup_uart14_default: qup-uart14-default-state {
3142 qup_uart14_tx: tx-pins {
3143 pins = "gpio31";
3144 function = "qup14";
3128 };
3129
3145 };
3146
3130 config {
3131 pins = "gpio60";
3132 drive-strength = <2>;
3133 bias-pull-down;
3134 input-enable;
3147 qup_uart14_rx: rx-pins {
3148 pins = "gpio32";
3149 function = "qup14";
3135 };
3136 };
3137
3150 };
3151 };
3152
3138 quat_mi2s_sd0_active: quat_mi2s_sd0_active {
3139 mux {
3140 pins = "gpio60";
3141 function = "qua_mi2s";
3153 qup_uart15_default: qup-uart15-default-state {
3154 qup_uart15_tx: tx-pins {
3155 pins = "gpio83";
3156 function = "qup15";
3142 };
3143
3157 };
3158
3144 config {
3145 pins = "gpio60";
3146 drive-strength = <8>;
3147 bias-disable;
3159 qup_uart15_rx: rx-pins {
3160 pins = "gpio84";
3161 function = "qup15";
3148 };
3149 };
3150
3162 };
3163 };
3164
3151 quat_mi2s_sd1_sleep: quat_mi2s_sd1_sleep {
3152 mux {
3153 pins = "gpio61";
3154 function = "gpio";
3155 };
3165 quat_mi2s_sleep: quat-mi2s-sleep-state {
3166 pins = "gpio58", "gpio59";
3167 function = "gpio";
3168 drive-strength = <2>;
3169 bias-pull-down;
3170 input-enable;
3171 };
3156
3172
3157 config {
3158 pins = "gpio61";
3159 drive-strength = <2>;
3160 bias-pull-down;
3161 input-enable;
3162 };
3173 quat_mi2s_active: quat-mi2s-active-state {
3174 pins = "gpio58", "gpio59";
3175 function = "qua_mi2s";
3176 drive-strength = <8>;
3177 bias-disable;
3178 output-high;
3163 };
3164
3179 };
3180
3165 quat_mi2s_sd1_active: quat_mi2s_sd1_active {
3166 mux {
3167 pins = "gpio61";
3168 function = "qua_mi2s";
3169 };
3181 quat_mi2s_sd0_sleep: quat-mi2s-sd0-sleep-state {
3182 pins = "gpio60";
3183 function = "gpio";
3184 drive-strength = <2>;
3185 bias-pull-down;
3186 input-enable;
3187 };
3170
3188
3171 config {
3172 pins = "gpio61";
3173 drive-strength = <8>;
3174 bias-disable;
3175 };
3189 quat_mi2s_sd0_active: quat-mi2s-sd0-active-state {
3190 pins = "gpio60";
3191 function = "qua_mi2s";
3192 drive-strength = <8>;
3193 bias-disable;
3176 };
3177
3194 };
3195
3178 quat_mi2s_sd2_sleep: quat_mi2s_sd2_sleep {
3179 mux {
3180 pins = "gpio62";
3181 function = "gpio";
3182 };
3196 quat_mi2s_sd1_sleep: quat-mi2s-sd1-sleep-state {
3197 pins = "gpio61";
3198 function = "gpio";
3199 drive-strength = <2>;
3200 bias-pull-down;
3201 input-enable;
3202 };
3183
3203
3184 config {
3185 pins = "gpio62";
3186 drive-strength = <2>;
3187 bias-pull-down;
3188 input-enable;
3189 };
3204 quat_mi2s_sd1_active: quat-mi2s-sd1-active-state {
3205 pins = "gpio61";
3206 function = "qua_mi2s";
3207 drive-strength = <8>;
3208 bias-disable;
3190 };
3191
3209 };
3210
3192 quat_mi2s_sd2_active: quat_mi2s_sd2_active {
3193 mux {
3194 pins = "gpio62";
3195 function = "qua_mi2s";
3196 };
3211 quat_mi2s_sd2_sleep: quat-mi2s-sd2-sleep-state {
3212 pins = "gpio62";
3213 function = "gpio";
3214 drive-strength = <2>;
3215 bias-pull-down;
3216 input-enable;
3217 };
3197
3218
3198 config {
3199 pins = "gpio62";
3200 drive-strength = <8>;
3201 bias-disable;
3202 };
3219 quat_mi2s_sd2_active: quat-mi2s-sd2-active-state {
3220 pins = "gpio62";
3221 function = "qua_mi2s";
3222 drive-strength = <8>;
3223 bias-disable;
3203 };
3204
3224 };
3225
3205 quat_mi2s_sd3_sleep: quat_mi2s_sd3_sleep {
3206 mux {
3207 pins = "gpio63";
3208 function = "gpio";
3209 };
3210
3211 config {
3212 pins = "gpio63";
3213 drive-strength = <2>;
3214 bias-pull-down;
3215 input-enable;
3216 };
3226 quat_mi2s_sd3_sleep: quat-mi2s-sd3-sleep-state {
3227 pins = "gpio63";
3228 function = "gpio";
3229 drive-strength = <2>;
3230 bias-pull-down;
3231 input-enable;
3217 };
3218
3232 };
3233
3219 quat_mi2s_sd3_active: quat_mi2s_sd3_active {
3220 mux {
3221 pins = "gpio63";
3222 function = "qua_mi2s";
3223 };
3224
3225 config {
3226 pins = "gpio63";
3227 drive-strength = <8>;
3228 bias-disable;
3229 };
3234 quat_mi2s_sd3_active: quat-mi2s-sd3-active-state {
3235 pins = "gpio63";
3236 function = "qua_mi2s";
3237 drive-strength = <8>;
3238 bias-disable;
3230 };
3231 };
3232
3233 mss_pil: remoteproc@4080000 {
3234 compatible = "qcom,sdm845-mss-pil";
3235 reg = <0 0x04080000 0 0x408>, <0 0x04180000 0 0x48>;
3236 reg-names = "qdsp6", "rmb";
3237

--- 564 unchanged lines hidden (view full) ---

3802
3803 opp-201500000 {
3804 opp-hz = /bits/ 64 <201500000>;
3805 required-opps = <&rpmhpd_opp_svs_l1>;
3806 };
3807 };
3808 };
3809
3239 };
3240 };
3241
3242 mss_pil: remoteproc@4080000 {
3243 compatible = "qcom,sdm845-mss-pil";
3244 reg = <0 0x04080000 0 0x408>, <0 0x04180000 0 0x48>;
3245 reg-names = "qdsp6", "rmb";
3246

--- 564 unchanged lines hidden (view full) ---

3811
3812 opp-201500000 {
3813 opp-hz = /bits/ 64 <201500000>;
3814 required-opps = <&rpmhpd_opp_svs_l1>;
3815 };
3816 };
3817 };
3818
3810 qspi_opp_table: opp-table-qspi {
3811 compatible = "operating-points-v2";
3812
3813 opp-19200000 {
3814 opp-hz = /bits/ 64 <19200000>;
3815 required-opps = <&rpmhpd_opp_min_svs>;
3816 };
3817
3818 opp-100000000 {
3819 opp-hz = /bits/ 64 <100000000>;
3820 required-opps = <&rpmhpd_opp_low_svs>;
3821 };
3822
3823 opp-150000000 {
3824 opp-hz = /bits/ 64 <150000000>;
3825 required-opps = <&rpmhpd_opp_svs>;
3826 };
3827
3828 opp-300000000 {
3829 opp-hz = /bits/ 64 <300000000>;
3830 required-opps = <&rpmhpd_opp_nom>;
3831 };
3832 };
3833
3834 qspi: spi@88df000 {
3835 compatible = "qcom,sdm845-qspi", "qcom,qspi-v1";
3836 reg = <0 0x088df000 0 0x600>;
3837 #address-cells = <1>;
3838 #size-cells = <0>;
3839 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
3840 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
3841 <&gcc GCC_QSPI_CORE_CLK>;

--- 56 unchanged lines hidden (view full) ---

3898
3899 swm: swm@c85 {
3900 compatible = "qcom,soundwire-v1.3.0";
3901 reg = <0xc85 0x40>;
3902 interrupts-extended = <&wcd9340 20>;
3903
3904 qcom,dout-ports = <6>;
3905 qcom,din-ports = <2>;
3819 qspi: spi@88df000 {
3820 compatible = "qcom,sdm845-qspi", "qcom,qspi-v1";
3821 reg = <0 0x088df000 0 0x600>;
3822 #address-cells = <1>;
3823 #size-cells = <0>;
3824 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
3825 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
3826 <&gcc GCC_QSPI_CORE_CLK>;

--- 56 unchanged lines hidden (view full) ---

3883
3884 swm: swm@c85 {
3885 compatible = "qcom,soundwire-v1.3.0";
3886 reg = <0xc85 0x40>;
3887 interrupts-extended = <&wcd9340 20>;
3888
3889 qcom,dout-ports = <6>;
3890 qcom,din-ports = <2>;
3906 qcom,ports-sinterval-low =/bits/ 8 <0x07 0x1F 0x3F 0x7 0x1F 0x3F 0x0F 0x0F>;
3907 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0C 0x6 0x12 0x0D 0x07 0x0A >;
3908 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x1F 0x00 0x00 0x1F 0x00 0x00>;
3891 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x7 0x1f 0x3f 0x0f 0x0f>;
3892 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x6 0x12 0x0d 0x07 0x0a>;
3893 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x1f 0x00 0x00 0x1f 0x00 0x00>;
3909
3910 #sound-dai-cells = <1>;
3911 clocks = <&wcd9340>;
3912 clock-names = "iface";
3913 #address-cells = <2>;
3914 #size-cells = <0>;
3894
3895 #sound-dai-cells = <1>;
3896 clocks = <&wcd9340>;
3897 clock-names = "iface";
3898 #address-cells = <2>;
3899 #size-cells = <0>;
3915
3916
3917 };
3918 };
3919 };
3920 };
3921
3922 lmh_cluster1: lmh@17d70800 {
3923 compatible = "qcom,sdm845-lmh";
3924 reg = <0 0x17d70800 0 0x400>;

--- 13 unchanged lines hidden (view full) ---

3938 cpus = <&CPU0>;
3939 qcom,lmh-temp-arm-millicelsius = <65000>;
3940 qcom,lmh-temp-low-millicelsius = <94500>;
3941 qcom,lmh-temp-high-millicelsius = <95000>;
3942 interrupt-controller;
3943 #interrupt-cells = <1>;
3944 };
3945
3900 };
3901 };
3902 };
3903 };
3904
3905 lmh_cluster1: lmh@17d70800 {
3906 compatible = "qcom,sdm845-lmh";
3907 reg = <0 0x17d70800 0 0x400>;

--- 13 unchanged lines hidden (view full) ---

3921 cpus = <&CPU0>;
3922 qcom,lmh-temp-arm-millicelsius = <65000>;
3923 qcom,lmh-temp-low-millicelsius = <94500>;
3924 qcom,lmh-temp-high-millicelsius = <95000>;
3925 interrupt-controller;
3926 #interrupt-cells = <1>;
3927 };
3928
3946 sound: sound {
3947 };
3948
3949 usb_1_hsphy: phy@88e2000 {
3950 compatible = "qcom,sdm845-qusb2-phy", "qcom,qusb2-v2-phy";
3951 reg = <0 0x088e2000 0 0x400>;
3952 status = "disabled";
3953 #phy-cells = <0>;
3954
3955 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
3956 <&rpmhcc RPMH_CXO_CLK>;

--- 482 unchanged lines hidden (view full) ---

4439 reg = <0 0x0ad00000 0 0x10000>;
4440 #clock-cells = <1>;
4441 #reset-cells = <1>;
4442 #power-domain-cells = <1>;
4443 clocks = <&rpmhcc RPMH_CXO_CLK>;
4444 clock-names = "bi_tcxo";
4445 };
4446
3929 usb_1_hsphy: phy@88e2000 {
3930 compatible = "qcom,sdm845-qusb2-phy", "qcom,qusb2-v2-phy";
3931 reg = <0 0x088e2000 0 0x400>;
3932 status = "disabled";
3933 #phy-cells = <0>;
3934
3935 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
3936 <&rpmhcc RPMH_CXO_CLK>;

--- 482 unchanged lines hidden (view full) ---

4419 reg = <0 0x0ad00000 0 0x10000>;
4420 #clock-cells = <1>;
4421 #reset-cells = <1>;
4422 #power-domain-cells = <1>;
4423 clocks = <&rpmhcc RPMH_CXO_CLK>;
4424 clock-names = "bi_tcxo";
4425 };
4426
4447 dsi_opp_table: opp-table-dsi {
4448 compatible = "operating-points-v2";
4449
4450 opp-19200000 {
4451 opp-hz = /bits/ 64 <19200000>;
4452 required-opps = <&rpmhpd_opp_min_svs>;
4453 };
4454
4455 opp-180000000 {
4456 opp-hz = /bits/ 64 <180000000>;
4457 required-opps = <&rpmhpd_opp_low_svs>;
4458 };
4459
4460 opp-275000000 {
4461 opp-hz = /bits/ 64 <275000000>;
4462 required-opps = <&rpmhpd_opp_svs>;
4463 };
4464
4465 opp-328580000 {
4466 opp-hz = /bits/ 64 <328580000>;
4467 required-opps = <&rpmhpd_opp_svs_l1>;
4468 };
4469
4470 opp-358000000 {
4471 opp-hz = /bits/ 64 <358000000>;
4472 required-opps = <&rpmhpd_opp_nom>;
4473 };
4474 };
4475
4476 mdss: mdss@ae00000 {
4477 compatible = "qcom,sdm845-mdss";
4478 reg = <0 0x0ae00000 0 0x1000>;
4479 reg-names = "mdss";
4480
4481 power-domains = <&dispcc MDSS_GDSC>;
4482
4483 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,

--- 156 unchanged lines hidden (view full) ---

4640 opp-810000000 {
4641 opp-hz = /bits/ 64 <810000000>;
4642 required-opps = <&rpmhpd_opp_nom>;
4643 };
4644 };
4645 };
4646
4647 dsi0: dsi@ae94000 {
4427 mdss: mdss@ae00000 {
4428 compatible = "qcom,sdm845-mdss";
4429 reg = <0 0x0ae00000 0 0x1000>;
4430 reg-names = "mdss";
4431
4432 power-domains = <&dispcc MDSS_GDSC>;
4433
4434 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,

--- 156 unchanged lines hidden (view full) ---

4591 opp-810000000 {
4592 opp-hz = /bits/ 64 <810000000>;
4593 required-opps = <&rpmhpd_opp_nom>;
4594 };
4595 };
4596 };
4597
4598 dsi0: dsi@ae94000 {
4648 compatible = "qcom,mdss-dsi-ctrl";
4599 compatible = "qcom,sdm845-dsi-ctrl",
4600 "qcom,mdss-dsi-ctrl";
4649 reg = <0 0x0ae94000 0 0x400>;
4650 reg-names = "dsi_ctrl";
4651
4652 interrupt-parent = <&mdss>;
4653 interrupts = <4>;
4654
4655 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
4656 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,

--- 54 unchanged lines hidden (view full) ---

4711 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4712 <&rpmhcc RPMH_CXO_CLK>;
4713 clock-names = "iface", "ref";
4714
4715 status = "disabled";
4716 };
4717
4718 dsi1: dsi@ae96000 {
4601 reg = <0 0x0ae94000 0 0x400>;
4602 reg-names = "dsi_ctrl";
4603
4604 interrupt-parent = <&mdss>;
4605 interrupts = <4>;
4606
4607 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
4608 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,

--- 54 unchanged lines hidden (view full) ---

4663 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4664 <&rpmhcc RPMH_CXO_CLK>;
4665 clock-names = "iface", "ref";
4666
4667 status = "disabled";
4668 };
4669
4670 dsi1: dsi@ae96000 {
4719 compatible = "qcom,mdss-dsi-ctrl";
4671 compatible = "qcom,sdm845-dsi-ctrl",
4672 "qcom,mdss-dsi-ctrl";
4720 reg = <0 0x0ae96000 0 0x400>;
4721 reg-names = "dsi_ctrl";
4722
4723 interrupt-parent = <&mdss>;
4724 interrupts = <5>;
4725
4726 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
4727 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,

--- 632 unchanged lines hidden (view full) ---

5360 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
5361 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
5362 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
5363 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>;
5364 iommus = <&apps_smmu 0x0040 0x1>;
5365 };
5366 };
5367
4673 reg = <0 0x0ae96000 0 0x400>;
4674 reg-names = "dsi_ctrl";
4675
4676 interrupt-parent = <&mdss>;
4677 interrupts = <5>;
4678
4679 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
4680 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,

--- 632 unchanged lines hidden (view full) ---

5313 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
5314 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
5315 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
5316 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>;
5317 iommus = <&apps_smmu 0x0040 0x1>;
5318 };
5319 };
5320
5321 sound: sound {
5322 };
5323
5368 thermal-zones {
5369 cpu0-thermal {
5370 polling-delay-passive = <250>;
5371 polling-delay = <1000>;
5372
5373 thermal-sensors = <&tsens0 1>;
5374
5375 trips {

--- 415 unchanged lines hidden --- 		5324 thermal-zones {
5325 cpu0-thermal {
5326 polling-delay-passive = <250>;
5327 polling-delay = <1000>;
5328
5329 thermal-sensors = <&tsens0 1>;
5330
5331 trips {

--- 415 unchanged lines hidden ---