sc7180.dtsi (4aef2ec9022b217f74d0f4c9b84081f07cc223d9) sc7180.dtsi (39f3d3bb05a43414905aba33f6250e8ddaea38b6)
1// SPDX-License-Identifier: BSD-3-Clause
2/*
3 * SC7180 SoC device tree source
4 *
5 * Copyright (c) 2019, The Linux Foundation. All rights reserved.
6 */
7
8#include <dt-bindings/clock/qcom,dispcc-sc7180.h>
9#include <dt-bindings/clock/qcom,gcc-sc7180.h>
10#include <dt-bindings/clock/qcom,gpucc-sc7180.h>
11#include <dt-bindings/clock/qcom,rpmh.h>
12#include <dt-bindings/clock/qcom,videocc-sc7180.h>
1// SPDX-License-Identifier: BSD-3-Clause
2/*
3 * SC7180 SoC device tree source
4 *
5 * Copyright (c) 2019, The Linux Foundation. All rights reserved.
6 */
7
8#include <dt-bindings/clock/qcom,dispcc-sc7180.h>
9#include <dt-bindings/clock/qcom,gcc-sc7180.h>
10#include <dt-bindings/clock/qcom,gpucc-sc7180.h>
11#include <dt-bindings/clock/qcom,rpmh.h>
12#include <dt-bindings/clock/qcom,videocc-sc7180.h>
13#include <dt-bindings/interconnect/qcom,sc7180.h>
13#include <dt-bindings/interrupt-controller/arm-gic.h>
14#include <dt-bindings/phy/phy-qcom-qusb2.h>
15#include <dt-bindings/power/qcom-aoss-qmp.h>
16#include <dt-bindings/power/qcom-rpmpd.h>
17#include <dt-bindings/reset/qcom,sdm845-aoss.h>
18#include <dt-bindings/reset/qcom,sdm845-pdc.h>
19#include <dt-bindings/soc/qcom,rpmh-rsc.h>
20#include <dt-bindings/thermal/thermal.h>

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64 };
65 };
66
67 reserved_memory: reserved-memory {
68 #address-cells = <2>;
69 #size-cells = <2>;
70 ranges;
71
14#include <dt-bindings/interrupt-controller/arm-gic.h>
15#include <dt-bindings/phy/phy-qcom-qusb2.h>
16#include <dt-bindings/power/qcom-aoss-qmp.h>
17#include <dt-bindings/power/qcom-rpmpd.h>
18#include <dt-bindings/reset/qcom,sdm845-aoss.h>
19#include <dt-bindings/reset/qcom,sdm845-pdc.h>
20#include <dt-bindings/soc/qcom,rpmh-rsc.h>
21#include <dt-bindings/thermal/thermal.h>

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65 };
66 };
67
68 reserved_memory: reserved-memory {
69 #address-cells = <2>;
70 #size-cells = <2>;
71 ranges;
72
73 hyp_mem: memory@80000000 {
74 reg = <0x0 0x80000000 0x0 0x600000>;
75 no-map;
76 };
77
78 xbl_mem: memory@80600000 {
79 reg = <0x0 0x80600000 0x0 0x200000>;
80 no-map;
81 };
82
83 aop_mem: memory@80800000 {
84 reg = <0x0 0x80800000 0x0 0x20000>;
85 no-map;
86 };
87
72 aop_cmd_db_mem: memory@80820000 {
73 reg = <0x0 0x80820000 0x0 0x20000>;
74 compatible = "qcom,cmd-db";
88 aop_cmd_db_mem: memory@80820000 {
89 reg = <0x0 0x80820000 0x0 0x20000>;
90 compatible = "qcom,cmd-db";
91 no-map;
75 };
76
92 };
93
94 sec_apps_mem: memory@808ff000 {
95 reg = <0x0 0x808ff000 0x0 0x1000>;
96 no-map;
97 };
98
77 smem_mem: memory@80900000 {
78 reg = <0x0 0x80900000 0x0 0x200000>;
79 no-map;
80 };
81
99 smem_mem: memory@80900000 {
100 reg = <0x0 0x80900000 0x0 0x200000>;
101 no-map;
102 };
103
82 venus_mem: memory@8f600000 {
83 reg = <0 0x8f600000 0 0x500000>;
104 tz_mem: memory@80b00000 {
105 reg = <0x0 0x80b00000 0x0 0x3900000>;
84 no-map;
85 };
106 no-map;
107 };
108
109 rmtfs_mem: memory@84400000 {
110 compatible = "qcom,rmtfs-mem";
111 reg = <0x0 0x84400000 0x0 0x200000>;
112 no-map;
113
114 qcom,client-id = <1>;
115 qcom,vmid = <15>;
116 };
86 };
87
88 cpus {
89 #address-cells = <2>;
90 #size-cells = <0>;
91
92 CPU0: cpu@0 {
93 device_type = "cpu";
117 };
118
119 cpus {
120 #address-cells = <2>;
121 #size-cells = <0>;
122
123 CPU0: cpu@0 {
124 device_type = "cpu";
94 compatible = "arm,armv8";
125 compatible = "qcom,kryo468";
95 reg = <0x0 0x0>;
96 enable-method = "psci";
126 reg = <0x0 0x0>;
127 enable-method = "psci";
128 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
129 &LITTLE_CPU_SLEEP_1
130 &CLUSTER_SLEEP_0>;
97 capacity-dmips-mhz = <1024>;
98 dynamic-power-coefficient = <100>;
99 next-level-cache = <&L2_0>;
100 #cooling-cells = <2>;
101 qcom,freq-domain = <&cpufreq_hw 0>;
102 L2_0: l2-cache {
103 compatible = "cache";
104 next-level-cache = <&L3_0>;
105 L3_0: l3-cache {
106 compatible = "cache";
107 };
108 };
109 };
110
111 CPU1: cpu@100 {
112 device_type = "cpu";
131 capacity-dmips-mhz = <1024>;
132 dynamic-power-coefficient = <100>;
133 next-level-cache = <&L2_0>;
134 #cooling-cells = <2>;
135 qcom,freq-domain = <&cpufreq_hw 0>;
136 L2_0: l2-cache {
137 compatible = "cache";
138 next-level-cache = <&L3_0>;
139 L3_0: l3-cache {
140 compatible = "cache";
141 };
142 };
143 };
144
145 CPU1: cpu@100 {
146 device_type = "cpu";
113 compatible = "arm,armv8";
147 compatible = "qcom,kryo468";
114 reg = <0x0 0x100>;
115 enable-method = "psci";
148 reg = <0x0 0x100>;
149 enable-method = "psci";
150 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
151 &LITTLE_CPU_SLEEP_1
152 &CLUSTER_SLEEP_0>;
116 capacity-dmips-mhz = <1024>;
117 dynamic-power-coefficient = <100>;
118 next-level-cache = <&L2_100>;
119 #cooling-cells = <2>;
120 qcom,freq-domain = <&cpufreq_hw 0>;
121 L2_100: l2-cache {
122 compatible = "cache";
123 next-level-cache = <&L3_0>;
124 };
125 };
126
127 CPU2: cpu@200 {
128 device_type = "cpu";
153 capacity-dmips-mhz = <1024>;
154 dynamic-power-coefficient = <100>;
155 next-level-cache = <&L2_100>;
156 #cooling-cells = <2>;
157 qcom,freq-domain = <&cpufreq_hw 0>;
158 L2_100: l2-cache {
159 compatible = "cache";
160 next-level-cache = <&L3_0>;
161 };
162 };
163
164 CPU2: cpu@200 {
165 device_type = "cpu";
129 compatible = "arm,armv8";
166 compatible = "qcom,kryo468";
130 reg = <0x0 0x200>;
131 enable-method = "psci";
167 reg = <0x0 0x200>;
168 enable-method = "psci";
169 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
170 &LITTLE_CPU_SLEEP_1
171 &CLUSTER_SLEEP_0>;
132 capacity-dmips-mhz = <1024>;
133 dynamic-power-coefficient = <100>;
134 next-level-cache = <&L2_200>;
135 #cooling-cells = <2>;
136 qcom,freq-domain = <&cpufreq_hw 0>;
137 L2_200: l2-cache {
138 compatible = "cache";
139 next-level-cache = <&L3_0>;
140 };
141 };
142
143 CPU3: cpu@300 {
144 device_type = "cpu";
172 capacity-dmips-mhz = <1024>;
173 dynamic-power-coefficient = <100>;
174 next-level-cache = <&L2_200>;
175 #cooling-cells = <2>;
176 qcom,freq-domain = <&cpufreq_hw 0>;
177 L2_200: l2-cache {
178 compatible = "cache";
179 next-level-cache = <&L3_0>;
180 };
181 };
182
183 CPU3: cpu@300 {
184 device_type = "cpu";
145 compatible = "arm,armv8";
185 compatible = "qcom,kryo468";
146 reg = <0x0 0x300>;
147 enable-method = "psci";
186 reg = <0x0 0x300>;
187 enable-method = "psci";
188 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
189 &LITTLE_CPU_SLEEP_1
190 &CLUSTER_SLEEP_0>;
148 capacity-dmips-mhz = <1024>;
149 dynamic-power-coefficient = <100>;
150 next-level-cache = <&L2_300>;
151 #cooling-cells = <2>;
152 qcom,freq-domain = <&cpufreq_hw 0>;
153 L2_300: l2-cache {
154 compatible = "cache";
155 next-level-cache = <&L3_0>;
156 };
157 };
158
159 CPU4: cpu@400 {
160 device_type = "cpu";
191 capacity-dmips-mhz = <1024>;
192 dynamic-power-coefficient = <100>;
193 next-level-cache = <&L2_300>;
194 #cooling-cells = <2>;
195 qcom,freq-domain = <&cpufreq_hw 0>;
196 L2_300: l2-cache {
197 compatible = "cache";
198 next-level-cache = <&L3_0>;
199 };
200 };
201
202 CPU4: cpu@400 {
203 device_type = "cpu";
161 compatible = "arm,armv8";
204 compatible = "qcom,kryo468";
162 reg = <0x0 0x400>;
163 enable-method = "psci";
205 reg = <0x0 0x400>;
206 enable-method = "psci";
207 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
208 &LITTLE_CPU_SLEEP_1
209 &CLUSTER_SLEEP_0>;
164 capacity-dmips-mhz = <1024>;
165 dynamic-power-coefficient = <100>;
166 next-level-cache = <&L2_400>;
167 #cooling-cells = <2>;
168 qcom,freq-domain = <&cpufreq_hw 0>;
169 L2_400: l2-cache {
170 compatible = "cache";
171 next-level-cache = <&L3_0>;
172 };
173 };
174
175 CPU5: cpu@500 {
176 device_type = "cpu";
210 capacity-dmips-mhz = <1024>;
211 dynamic-power-coefficient = <100>;
212 next-level-cache = <&L2_400>;
213 #cooling-cells = <2>;
214 qcom,freq-domain = <&cpufreq_hw 0>;
215 L2_400: l2-cache {
216 compatible = "cache";
217 next-level-cache = <&L3_0>;
218 };
219 };
220
221 CPU5: cpu@500 {
222 device_type = "cpu";
177 compatible = "arm,armv8";
223 compatible = "qcom,kryo468";
178 reg = <0x0 0x500>;
179 enable-method = "psci";
224 reg = <0x0 0x500>;
225 enable-method = "psci";
226 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
227 &LITTLE_CPU_SLEEP_1
228 &CLUSTER_SLEEP_0>;
180 capacity-dmips-mhz = <1024>;
181 dynamic-power-coefficient = <100>;
182 next-level-cache = <&L2_500>;
183 #cooling-cells = <2>;
184 qcom,freq-domain = <&cpufreq_hw 0>;
185 L2_500: l2-cache {
186 compatible = "cache";
187 next-level-cache = <&L3_0>;
188 };
189 };
190
191 CPU6: cpu@600 {
192 device_type = "cpu";
229 capacity-dmips-mhz = <1024>;
230 dynamic-power-coefficient = <100>;
231 next-level-cache = <&L2_500>;
232 #cooling-cells = <2>;
233 qcom,freq-domain = <&cpufreq_hw 0>;
234 L2_500: l2-cache {
235 compatible = "cache";
236 next-level-cache = <&L3_0>;
237 };
238 };
239
240 CPU6: cpu@600 {
241 device_type = "cpu";
193 compatible = "arm,armv8";
242 compatible = "qcom,kryo468";
194 reg = <0x0 0x600>;
195 enable-method = "psci";
243 reg = <0x0 0x600>;
244 enable-method = "psci";
245 cpu-idle-states = <&BIG_CPU_SLEEP_0
246 &BIG_CPU_SLEEP_1
247 &CLUSTER_SLEEP_0>;
196 capacity-dmips-mhz = <1740>;
197 dynamic-power-coefficient = <405>;
198 next-level-cache = <&L2_600>;
199 #cooling-cells = <2>;
200 qcom,freq-domain = <&cpufreq_hw 1>;
201 L2_600: l2-cache {
202 compatible = "cache";
203 next-level-cache = <&L3_0>;
204 };
205 };
206
207 CPU7: cpu@700 {
208 device_type = "cpu";
248 capacity-dmips-mhz = <1740>;
249 dynamic-power-coefficient = <405>;
250 next-level-cache = <&L2_600>;
251 #cooling-cells = <2>;
252 qcom,freq-domain = <&cpufreq_hw 1>;
253 L2_600: l2-cache {
254 compatible = "cache";
255 next-level-cache = <&L3_0>;
256 };
257 };
258
259 CPU7: cpu@700 {
260 device_type = "cpu";
209 compatible = "arm,armv8";
261 compatible = "qcom,kryo468";
210 reg = <0x0 0x700>;
211 enable-method = "psci";
262 reg = <0x0 0x700>;
263 enable-method = "psci";
264 cpu-idle-states = <&BIG_CPU_SLEEP_0
265 &BIG_CPU_SLEEP_1
266 &CLUSTER_SLEEP_0>;
212 capacity-dmips-mhz = <1740>;
213 dynamic-power-coefficient = <405>;
214 next-level-cache = <&L2_700>;
215 #cooling-cells = <2>;
216 qcom,freq-domain = <&cpufreq_hw 1>;
217 L2_700: l2-cache {
218 compatible = "cache";
219 next-level-cache = <&L3_0>;

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250 cpu = <&CPU6>;
251 };
252
253 core7 {
254 cpu = <&CPU7>;
255 };
256 };
257 };
267 capacity-dmips-mhz = <1740>;
268 dynamic-power-coefficient = <405>;
269 next-level-cache = <&L2_700>;
270 #cooling-cells = <2>;
271 qcom,freq-domain = <&cpufreq_hw 1>;
272 L2_700: l2-cache {
273 compatible = "cache";
274 next-level-cache = <&L3_0>;

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305 cpu = <&CPU6>;
306 };
307
308 core7 {
309 cpu = <&CPU7>;
310 };
311 };
312 };
313
314 idle-states {
315 entry-method = "psci";
316
317 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
318 compatible = "arm,idle-state";
319 idle-state-name = "little-power-down";
320 arm,psci-suspend-param = <0x40000003>;
321 entry-latency-us = <549>;
322 exit-latency-us = <901>;
323 min-residency-us = <1774>;
324 local-timer-stop;
325 };
326
327 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
328 compatible = "arm,idle-state";
329 idle-state-name = "little-rail-power-down";
330 arm,psci-suspend-param = <0x40000004>;
331 entry-latency-us = <702>;
332 exit-latency-us = <915>;
333 min-residency-us = <4001>;
334 local-timer-stop;
335 };
336
337 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
338 compatible = "arm,idle-state";
339 idle-state-name = "big-power-down";
340 arm,psci-suspend-param = <0x40000003>;
341 entry-latency-us = <523>;
342 exit-latency-us = <1244>;
343 min-residency-us = <2207>;
344 local-timer-stop;
345 };
346
347 BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
348 compatible = "arm,idle-state";
349 idle-state-name = "big-rail-power-down";
350 arm,psci-suspend-param = <0x40000004>;
351 entry-latency-us = <526>;
352 exit-latency-us = <1854>;
353 min-residency-us = <5555>;
354 local-timer-stop;
355 };
356
357 CLUSTER_SLEEP_0: cluster-sleep-0 {
358 compatible = "arm,idle-state";
359 idle-state-name = "cluster-power-down";
360 arm,psci-suspend-param = <0x40003444>;
361 entry-latency-us = <3263>;
362 exit-latency-us = <6562>;
363 min-residency-us = <9926>;
364 local-timer-stop;
365 };
366 };
258 };
259
260 memory@80000000 {
261 device_type = "memory";
262 /* We expect the bootloader to fill in the size */
263 reg = <0 0x80000000 0 0>;
264 };
265

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898 qcom,bcm-voters = <&apps_bcm_voter>;
899 };
900
901 tcsr_mutex_regs: syscon@1f40000 {
902 compatible = "syscon";
903 reg = <0 0x01f40000 0 0x40000>;
904 };
905
367 };
368
369 memory@80000000 {
370 device_type = "memory";
371 /* We expect the bootloader to fill in the size */
372 reg = <0 0x80000000 0 0>;
373 };
374

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1007 qcom,bcm-voters = <&apps_bcm_voter>;
1008 };
1009
1010 tcsr_mutex_regs: syscon@1f40000 {
1011 compatible = "syscon";
1012 reg = <0 0x01f40000 0 0x40000>;
1013 };
1014
1015 tcsr_regs: syscon@1fc0000 {
1016 compatible = "syscon";
1017 reg = <0 0x01fc0000 0 0x40000>;
1018 };
1019
906 tlmm: pinctrl@3500000 {
907 compatible = "qcom,sc7180-pinctrl";
908 reg = <0 0x03500000 0 0x300000>,
909 <0 0x03900000 0 0x300000>,
910 <0 0x03d00000 0 0x300000>;
911 reg-names = "west", "north", "south";
912 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
913 gpio-controller;

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1289 pinconf-sd-cd {
1290 pins = "gpio69";
1291 bias-disable;
1292 drive-strength = <2>;
1293 };
1294 };
1295 };
1296
1020 tlmm: pinctrl@3500000 {
1021 compatible = "qcom,sc7180-pinctrl";
1022 reg = <0 0x03500000 0 0x300000>,
1023 <0 0x03900000 0 0x300000>,
1024 <0 0x03d00000 0 0x300000>;
1025 reg-names = "west", "north", "south";
1026 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
1027 gpio-controller;

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1403 pinconf-sd-cd {
1404 pins = "gpio69";
1405 bias-disable;
1406 drive-strength = <2>;
1407 };
1408 };
1409 };
1410
1297 sdhc_2: sdhci@8804000 {
1298 compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5";
1299 reg = <0 0x08804000 0 0x1000>;
1411 gpu: gpu@5000000 {
1412 compatible = "qcom,adreno-618.0", "qcom,adreno";
1413 #stream-id-cells = <16>;
1414 reg = <0 0x05000000 0 0x40000>, <0 0x0509e000 0 0x1000>,
1415 <0 0x05061000 0 0x800>;
1416 reg-names = "kgsl_3d0_reg_memory", "cx_mem", "cx_dbgc";
1417 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
1418 iommus = <&adreno_smmu 0>;
1419 operating-points-v2 = <&gpu_opp_table>;
1420 qcom,gmu = <&gmu>;
1300
1421
1301 iommus = <&apps_smmu 0x80 0>;
1302 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
1303 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
1304 interrupt-names = "hc_irq", "pwr_irq";
1422 gpu_opp_table: opp-table {
1423 compatible = "operating-points-v2";
1305
1424
1306 clocks = <&gcc GCC_SDCC2_APPS_CLK>,
1307 <&gcc GCC_SDCC2_AHB_CLK>;
1308 clock-names = "core", "iface";
1425 opp-800000000 {
1426 opp-hz = /bits/ 64 <800000000>;
1427 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
1428 };
1309
1429
1310 bus-width = <4>;
1430 opp-650000000 {
1431 opp-hz = /bits/ 64 <650000000>;
1432 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
1433 };
1311
1434
1312 status = "disabled";
1435 opp-565000000 {
1436 opp-hz = /bits/ 64 <565000000>;
1437 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
1438 };
1439
1440 opp-430000000 {
1441 opp-hz = /bits/ 64 <430000000>;
1442 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
1443 };
1444
1445 opp-355000000 {
1446 opp-hz = /bits/ 64 <355000000>;
1447 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
1448 };
1449
1450 opp-267000000 {
1451 opp-hz = /bits/ 64 <267000000>;
1452 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
1453 };
1454
1455 opp-180000000 {
1456 opp-hz = /bits/ 64 <180000000>;
1457 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
1458 };
1459 };
1313 };
1314
1460 };
1461
1462 adreno_smmu: iommu@5040000 {
1463 compatible = "qcom,sc7180-smmu-v2", "qcom,smmu-v2";
1464 reg = <0 0x05040000 0 0x10000>;
1465 #iommu-cells = <1>;
1466 #global-interrupts = <2>;
1467 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
1468 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
1469 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
1470 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
1471 <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>,
1472 <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>,
1473 <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>,
1474 <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>,
1475 <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>,
1476 <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>;
1477
1478 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
1479 <&gcc GCC_GPU_CFG_AHB_CLK>;
1480 clock-names = "bus", "iface";
1481
1482 power-domains = <&gpucc CX_GDSC>;
1483 };
1484
1485 gmu: gmu@506a000 {
1486 compatible="qcom,adreno-gmu-618.0", "qcom,adreno-gmu";
1487 reg = <0 0x0506a000 0 0x31000>, <0 0x0b290000 0 0x10000>,
1488 <0 0x0b490000 0 0x10000>;
1489 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
1490 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
1491 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
1492 interrupt-names = "hfi", "gmu";
1493 clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
1494 <&gpucc GPU_CC_CXO_CLK>,
1495 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
1496 <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
1497 clock-names = "gmu", "cxo", "axi", "memnoc";
1498 power-domains = <&gpucc CX_GDSC>, <&gpucc GX_GDSC>;
1499 power-domain-names = "cx", "gx";
1500 iommus = <&adreno_smmu 5>;
1501 operating-points-v2 = <&gmu_opp_table>;
1502
1503 gmu_opp_table: opp-table {
1504 compatible = "operating-points-v2";
1505
1506 opp-200000000 {
1507 opp-hz = /bits/ 64 <200000000>;
1508 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
1509 };
1510 };
1511 };
1512
1315 gpucc: clock-controller@5090000 {
1316 compatible = "qcom,sc7180-gpucc";
1317 reg = <0 0x05090000 0 0x9000>;
1318 clocks = <&rpmhcc RPMH_CXO_CLK>,
1319 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
1320 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
1321 clock-names = "bi_tcxo",
1322 "gcc_gpu_gpll0_clk_src",
1323 "gcc_gpu_gpll0_div_clk_src";
1324 #clock-cells = <1>;
1325 #reset-cells = <1>;
1326 #power-domain-cells = <1>;
1327 };
1328
1513 gpucc: clock-controller@5090000 {
1514 compatible = "qcom,sc7180-gpucc";
1515 reg = <0 0x05090000 0 0x9000>;
1516 clocks = <&rpmhcc RPMH_CXO_CLK>,
1517 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
1518 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
1519 clock-names = "bi_tcxo",
1520 "gcc_gpu_gpll0_clk_src",
1521 "gcc_gpu_gpll0_div_clk_src";
1522 #clock-cells = <1>;
1523 #reset-cells = <1>;
1524 #power-domain-cells = <1>;
1525 };
1526
1527 stm@6002000 {
1528 compatible = "arm,coresight-stm", "arm,primecell";
1529 reg = <0 0x06002000 0 0x1000>,
1530 <0 0x16280000 0 0x180000>;
1531 reg-names = "stm-base", "stm-stimulus-base";
1532
1533 clocks = <&aoss_qmp>;
1534 clock-names = "apb_pclk";
1535
1536 out-ports {
1537 port {
1538 stm_out: endpoint {
1539 remote-endpoint = <&funnel0_in7>;
1540 };
1541 };
1542 };
1543 };
1544
1545 funnel@6041000 {
1546 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1547 reg = <0 0x06041000 0 0x1000>;
1548
1549 clocks = <&aoss_qmp>;
1550 clock-names = "apb_pclk";
1551
1552 out-ports {
1553 port {
1554 funnel0_out: endpoint {
1555 remote-endpoint = <&merge_funnel_in0>;
1556 };
1557 };
1558 };
1559
1560 in-ports {
1561 #address-cells = <1>;
1562 #size-cells = <0>;
1563
1564 port@7 {
1565 reg = <7>;
1566 funnel0_in7: endpoint {
1567 remote-endpoint = <&stm_out>;
1568 };
1569 };
1570 };
1571 };
1572
1573 funnel@6042000 {
1574 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1575 reg = <0 0x06042000 0 0x1000>;
1576
1577 clocks = <&aoss_qmp>;
1578 clock-names = "apb_pclk";
1579
1580 out-ports {
1581 port {
1582 funnel1_out: endpoint {
1583 remote-endpoint = <&merge_funnel_in1>;
1584 };
1585 };
1586 };
1587
1588 in-ports {
1589 #address-cells = <1>;
1590 #size-cells = <0>;
1591
1592 port@4 {
1593 reg = <4>;
1594 funnel1_in4: endpoint {
1595 remote-endpoint = <&apss_merge_funnel_out>;
1596 };
1597 };
1598 };
1599 };
1600
1601 funnel@6045000 {
1602 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1603 reg = <0 0x06045000 0 0x1000>;
1604
1605 clocks = <&aoss_qmp>;
1606 clock-names = "apb_pclk";
1607
1608 out-ports {
1609 port {
1610 merge_funnel_out: endpoint {
1611 remote-endpoint = <&swao_funnel_in>;
1612 };
1613 };
1614 };
1615
1616 in-ports {
1617 #address-cells = <1>;
1618 #size-cells = <0>;
1619
1620 port@0 {
1621 reg = <0>;
1622 merge_funnel_in0: endpoint {
1623 remote-endpoint = <&funnel0_out>;
1624 };
1625 };
1626
1627 port@1 {
1628 reg = <1>;
1629 merge_funnel_in1: endpoint {
1630 remote-endpoint = <&funnel1_out>;
1631 };
1632 };
1633 };
1634 };
1635
1636 replicator@6046000 {
1637 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
1638 reg = <0 0x06046000 0 0x1000>;
1639
1640 clocks = <&aoss_qmp>;
1641 clock-names = "apb_pclk";
1642
1643 out-ports {
1644 port {
1645 replicator_out: endpoint {
1646 remote-endpoint = <&etr_in>;
1647 };
1648 };
1649 };
1650
1651 in-ports {
1652 port {
1653 replicator_in: endpoint {
1654 remote-endpoint = <&swao_replicator_out>;
1655 };
1656 };
1657 };
1658 };
1659
1660 etr@6048000 {
1661 compatible = "arm,coresight-tmc", "arm,primecell";
1662 reg = <0 0x06048000 0 0x1000>;
1663
1664 clocks = <&aoss_qmp>;
1665 clock-names = "apb_pclk";
1666 arm,scatter-gather;
1667
1668 in-ports {
1669 port {
1670 etr_in: endpoint {
1671 remote-endpoint = <&replicator_out>;
1672 };
1673 };
1674 };
1675 };
1676
1677 funnel@6b04000 {
1678 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1679 reg = <0 0x06b04000 0 0x1000>;
1680
1681 clocks = <&aoss_qmp>;
1682 clock-names = "apb_pclk";
1683
1684 out-ports {
1685 port {
1686 swao_funnel_out: endpoint {
1687 remote-endpoint = <&etf_in>;
1688 };
1689 };
1690 };
1691
1692 in-ports {
1693 #address-cells = <1>;
1694 #size-cells = <0>;
1695
1696 port@7 {
1697 reg = <7>;
1698 swao_funnel_in: endpoint {
1699 remote-endpoint = <&merge_funnel_out>;
1700 };
1701 };
1702 };
1703 };
1704
1705 etf@6b05000 {
1706 compatible = "arm,coresight-tmc", "arm,primecell";
1707 reg = <0 0x06b05000 0 0x1000>;
1708
1709 clocks = <&aoss_qmp>;
1710 clock-names = "apb_pclk";
1711
1712 out-ports {
1713 port {
1714 etf_out: endpoint {
1715 remote-endpoint = <&swao_replicator_in>;
1716 };
1717 };
1718 };
1719
1720 in-ports {
1721 port {
1722 etf_in: endpoint {
1723 remote-endpoint = <&swao_funnel_out>;
1724 };
1725 };
1726 };
1727 };
1728
1729 replicator@6b06000 {
1730 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
1731 reg = <0 0x06b06000 0 0x1000>;
1732
1733 clocks = <&aoss_qmp>;
1734 clock-names = "apb_pclk";
1735 arm,coresight-loses-context-with-cpu;
1736
1737 out-ports {
1738 port {
1739 swao_replicator_out: endpoint {
1740 remote-endpoint = <&replicator_in>;
1741 };
1742 };
1743 };
1744
1745 in-ports {
1746 port {
1747 swao_replicator_in: endpoint {
1748 remote-endpoint = <&etf_out>;
1749 };
1750 };
1751 };
1752 };
1753
1754 etm@7040000 {
1755 compatible = "arm,coresight-etm4x", "arm,primecell";
1756 reg = <0 0x07040000 0 0x1000>;
1757
1758 cpu = <&CPU0>;
1759
1760 clocks = <&aoss_qmp>;
1761 clock-names = "apb_pclk";
1762 arm,coresight-loses-context-with-cpu;
1763
1764 out-ports {
1765 port {
1766 etm0_out: endpoint {
1767 remote-endpoint = <&apss_funnel_in0>;
1768 };
1769 };
1770 };
1771 };
1772
1773 etm@7140000 {
1774 compatible = "arm,coresight-etm4x", "arm,primecell";
1775 reg = <0 0x07140000 0 0x1000>;
1776
1777 cpu = <&CPU1>;
1778
1779 clocks = <&aoss_qmp>;
1780 clock-names = "apb_pclk";
1781 arm,coresight-loses-context-with-cpu;
1782
1783 out-ports {
1784 port {
1785 etm1_out: endpoint {
1786 remote-endpoint = <&apss_funnel_in1>;
1787 };
1788 };
1789 };
1790 };
1791
1792 etm@7240000 {
1793 compatible = "arm,coresight-etm4x", "arm,primecell";
1794 reg = <0 0x07240000 0 0x1000>;
1795
1796 cpu = <&CPU2>;
1797
1798 clocks = <&aoss_qmp>;
1799 clock-names = "apb_pclk";
1800 arm,coresight-loses-context-with-cpu;
1801
1802 out-ports {
1803 port {
1804 etm2_out: endpoint {
1805 remote-endpoint = <&apss_funnel_in2>;
1806 };
1807 };
1808 };
1809 };
1810
1811 etm@7340000 {
1812 compatible = "arm,coresight-etm4x", "arm,primecell";
1813 reg = <0 0x07340000 0 0x1000>;
1814
1815 cpu = <&CPU3>;
1816
1817 clocks = <&aoss_qmp>;
1818 clock-names = "apb_pclk";
1819 arm,coresight-loses-context-with-cpu;
1820
1821 out-ports {
1822 port {
1823 etm3_out: endpoint {
1824 remote-endpoint = <&apss_funnel_in3>;
1825 };
1826 };
1827 };
1828 };
1829
1830 etm@7440000 {
1831 compatible = "arm,coresight-etm4x", "arm,primecell";
1832 reg = <0 0x07440000 0 0x1000>;
1833
1834 cpu = <&CPU4>;
1835
1836 clocks = <&aoss_qmp>;
1837 clock-names = "apb_pclk";
1838 arm,coresight-loses-context-with-cpu;
1839
1840 out-ports {
1841 port {
1842 etm4_out: endpoint {
1843 remote-endpoint = <&apss_funnel_in4>;
1844 };
1845 };
1846 };
1847 };
1848
1849 etm@7540000 {
1850 compatible = "arm,coresight-etm4x", "arm,primecell";
1851 reg = <0 0x07540000 0 0x1000>;
1852
1853 cpu = <&CPU5>;
1854
1855 clocks = <&aoss_qmp>;
1856 clock-names = "apb_pclk";
1857 arm,coresight-loses-context-with-cpu;
1858
1859 out-ports {
1860 port {
1861 etm5_out: endpoint {
1862 remote-endpoint = <&apss_funnel_in5>;
1863 };
1864 };
1865 };
1866 };
1867
1868 etm@7640000 {
1869 compatible = "arm,coresight-etm4x", "arm,primecell";
1870 reg = <0 0x07640000 0 0x1000>;
1871
1872 cpu = <&CPU6>;
1873
1874 clocks = <&aoss_qmp>;
1875 clock-names = "apb_pclk";
1876 arm,coresight-loses-context-with-cpu;
1877
1878 out-ports {
1879 port {
1880 etm6_out: endpoint {
1881 remote-endpoint = <&apss_funnel_in6>;
1882 };
1883 };
1884 };
1885 };
1886
1887 etm@7740000 {
1888 compatible = "arm,coresight-etm4x", "arm,primecell";
1889 reg = <0 0x07740000 0 0x1000>;
1890
1891 cpu = <&CPU7>;
1892
1893 clocks = <&aoss_qmp>;
1894 clock-names = "apb_pclk";
1895
1896 out-ports {
1897 port {
1898 etm7_out: endpoint {
1899 remote-endpoint = <&apss_funnel_in7>;
1900 };
1901 };
1902 };
1903 };
1904
1905 funnel@7800000 { /* APSS Funnel */
1906 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1907 reg = <0 0x07800000 0 0x1000>;
1908
1909 clocks = <&aoss_qmp>;
1910 clock-names = "apb_pclk";
1911
1912 out-ports {
1913 port {
1914 apss_funnel_out: endpoint {
1915 remote-endpoint = <&apss_merge_funnel_in>;
1916 };
1917 };
1918 };
1919
1920 in-ports {
1921 #address-cells = <1>;
1922 #size-cells = <0>;
1923
1924 port@0 {
1925 reg = <0>;
1926 apss_funnel_in0: endpoint {
1927 remote-endpoint = <&etm0_out>;
1928 };
1929 };
1930
1931 port@1 {
1932 reg = <1>;
1933 apss_funnel_in1: endpoint {
1934 remote-endpoint = <&etm1_out>;
1935 };
1936 };
1937
1938 port@2 {
1939 reg = <2>;
1940 apss_funnel_in2: endpoint {
1941 remote-endpoint = <&etm2_out>;
1942 };
1943 };
1944
1945 port@3 {
1946 reg = <3>;
1947 apss_funnel_in3: endpoint {
1948 remote-endpoint = <&etm3_out>;
1949 };
1950 };
1951
1952 port@4 {
1953 reg = <4>;
1954 apss_funnel_in4: endpoint {
1955 remote-endpoint = <&etm4_out>;
1956 };
1957 };
1958
1959 port@5 {
1960 reg = <5>;
1961 apss_funnel_in5: endpoint {
1962 remote-endpoint = <&etm5_out>;
1963 };
1964 };
1965
1966 port@6 {
1967 reg = <6>;
1968 apss_funnel_in6: endpoint {
1969 remote-endpoint = <&etm6_out>;
1970 };
1971 };
1972
1973 port@7 {
1974 reg = <7>;
1975 apss_funnel_in7: endpoint {
1976 remote-endpoint = <&etm7_out>;
1977 };
1978 };
1979 };
1980 };
1981
1982 funnel@7810000 {
1983 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1984 reg = <0 0x07810000 0 0x1000>;
1985
1986 clocks = <&aoss_qmp>;
1987 clock-names = "apb_pclk";
1988
1989 out-ports {
1990 port {
1991 apss_merge_funnel_out: endpoint {
1992 remote-endpoint = <&funnel1_in4>;
1993 };
1994 };
1995 };
1996
1997 in-ports {
1998 port {
1999 apss_merge_funnel_in: endpoint {
2000 remote-endpoint = <&apss_funnel_out>;
2001 };
2002 };
2003 };
2004 };
2005
2006 remoteproc_mpss: remoteproc@4080000 {
2007 compatible = "qcom,sc7180-mpss-pas";
2008 reg = <0 0x04080000 0 0x4040>, <0 0x04180000 0 0x48>;
2009 reg-names = "qdsp6", "rmb";
2010
2011 interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
2012 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2013 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2014 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2015 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
2016 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
2017 interrupt-names = "wdog", "fatal", "ready", "handover",
2018 "stop-ack", "shutdown-ack";
2019
2020 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
2021 <&gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>,
2022 <&gcc GCC_MSS_NAV_AXI_CLK>,
2023 <&gcc GCC_MSS_SNOC_AXI_CLK>,
2024 <&gcc GCC_MSS_MFAB_AXIS_CLK>,
2025 <&rpmhcc RPMH_CXO_CLK>;
2026 clock-names = "iface", "bus", "nav", "snoc_axi",
2027 "mnoc_axi", "xo";
2028
2029 power-domains = <&aoss_qmp AOSS_QMP_LS_MODEM>,
2030 <&rpmhpd SC7180_CX>,
2031 <&rpmhpd SC7180_MX>,
2032 <&rpmhpd SC7180_MSS>;
2033 power-domain-names = "load_state", "cx", "mx", "mss";
2034
2035 memory-region = <&mpss_mem>;
2036
2037 qcom,smem-states = <&modem_smp2p_out 0>;
2038 qcom,smem-state-names = "stop";
2039
2040 resets = <&aoss_reset AOSS_CC_MSS_RESTART>,
2041 <&pdc_reset PDC_MODEM_SYNC_RESET>;
2042 reset-names = "mss_restart", "pdc_reset";
2043
2044 qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>;
2045 qcom,spare-regs = <&tcsr_regs 0xb3e4>;
2046
2047 status = "disabled";
2048
2049 glink-edge {
2050 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
2051 label = "modem";
2052 qcom,remote-pid = <1>;
2053 mboxes = <&apss_shared 12>;
2054 };
2055 };
2056
2057 sdhc_2: sdhci@8804000 {
2058 compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5";
2059 reg = <0 0x08804000 0 0x1000>;
2060
2061 iommus = <&apps_smmu 0x80 0>;
2062 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
2063 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
2064 interrupt-names = "hc_irq", "pwr_irq";
2065
2066 clocks = <&gcc GCC_SDCC2_APPS_CLK>,
2067 <&gcc GCC_SDCC2_AHB_CLK>;
2068 clock-names = "core", "iface";
2069
2070 bus-width = <4>;
2071
2072 status = "disabled";
2073 };
2074
1329 qspi: spi@88dc000 {
1330 compatible = "qcom,qspi-v1";
1331 reg = <0 0x088dc000 0 0x600>;
1332 #address-cells = <1>;
1333 #size-cells = <0>;
1334 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
1335 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
1336 <&gcc GCC_QSPI_CORE_CLK>;
1337 clock-names = "iface", "core";
1338 status = "disabled";
1339 };
1340
1341 usb_1_hsphy: phy@88e3000 {
2075 qspi: spi@88dc000 {
2076 compatible = "qcom,qspi-v1";
2077 reg = <0 0x088dc000 0 0x600>;
2078 #address-cells = <1>;
2079 #size-cells = <0>;
2080 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
2081 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
2082 <&gcc GCC_QSPI_CORE_CLK>;
2083 clock-names = "iface", "core";
2084 status = "disabled";
2085 };
2086
2087 usb_1_hsphy: phy@88e3000 {
1342 compatible = "qcom,sc7180-qusb2-phy";
2088 compatible = "qcom,sc7180-qusb2-phy", "qcom,qusb2-v2-phy";
1343 reg = <0 0x088e3000 0 0x400>;
1344 status = "disabled";
1345 #phy-cells = <0>;
1346 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
1347 <&rpmhcc RPMH_CXO_CLK>;
1348 clock-names = "cfg_ahb", "ref";
1349 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
1350

--- 119 unchanged lines hidden (view full) ---

1470 <&videocc VIDEO_CC_VENUS_AHB_CLK>,
1471 <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>,
1472 <&videocc VIDEO_CC_VCODEC0_CORE_CLK>,
1473 <&videocc VIDEO_CC_VCODEC0_AXI_CLK>;
1474 clock-names = "core", "iface", "bus",
1475 "vcodec0_core", "vcodec0_bus";
1476 iommus = <&apps_smmu 0x0c00 0x60>;
1477 memory-region = <&venus_mem>;
2089 reg = <0 0x088e3000 0 0x400>;
2090 status = "disabled";
2091 #phy-cells = <0>;
2092 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2093 <&rpmhcc RPMH_CXO_CLK>;
2094 clock-names = "cfg_ahb", "ref";
2095 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2096

--- 119 unchanged lines hidden (view full) ---

2216 <&videocc VIDEO_CC_VENUS_AHB_CLK>,
2217 <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>,
2218 <&videocc VIDEO_CC_VCODEC0_CORE_CLK>,
2219 <&videocc VIDEO_CC_VCODEC0_AXI_CLK>;
2220 clock-names = "core", "iface", "bus",
2221 "vcodec0_core", "vcodec0_bus";
2222 iommus = <&apps_smmu 0x0c00 0x60>;
2223 memory-region = <&venus_mem>;
2224 interconnects = <&mmss_noc MASTER_VIDEO_P0 &mc_virt SLAVE_EBI1>,
2225 <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_VENUS_CFG>;
2226 interconnect-names = "video-mem", "cpu-cfg";
1478
1479 video-decoder {
1480 compatible = "venus-decoder";
1481 };
1482
1483 video-encoder {
1484 compatible = "venus-encoder";
1485 };

--- 53 unchanged lines hidden (view full) ---

1539 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
1540 <&dispcc DISP_CC_MDSS_ROT_CLK>,
1541 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
1542 <&dispcc DISP_CC_MDSS_MDP_CLK>,
1543 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
1544 clock-names = "iface", "rot", "lut", "core",
1545 "vsync";
1546 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>,
2227
2228 video-decoder {
2229 compatible = "venus-decoder";
2230 };
2231
2232 video-encoder {
2233 compatible = "venus-encoder";
2234 };

--- 53 unchanged lines hidden (view full) ---

2288 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
2289 <&dispcc DISP_CC_MDSS_ROT_CLK>,
2290 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
2291 <&dispcc DISP_CC_MDSS_MDP_CLK>,
2292 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
2293 clock-names = "iface", "rot", "lut", "core",
2294 "vsync";
2295 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>,
1547 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
2296 <&dispcc DISP_CC_MDSS_VSYNC_CLK>,
2297 <&dispcc DISP_CC_MDSS_ROT_CLK>,
2298 <&dispcc DISP_CC_MDSS_AHB_CLK>;
1548 assigned-clock-rates = <300000000>,
2299 assigned-clock-rates = <300000000>,
2300 <19200000>,
2301 <19200000>,
1549 <19200000>;
1550
1551 interrupt-parent = <&mdss>;
1552 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
1553
1554 status = "disabled";
1555
1556 ports {

--- 449 unchanged lines hidden (view full) ---

2006 clock-names = "xo", "alternate";
2007
2008 #freq-domain-cells = <1>;
2009 };
2010 };
2011
2012 thermal-zones {
2013 cpu0-thermal {
2302 <19200000>;
2303
2304 interrupt-parent = <&mdss>;
2305 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
2306
2307 status = "disabled";
2308
2309 ports {

--- 449 unchanged lines hidden (view full) ---

2759 clock-names = "xo", "alternate";
2760
2761 #freq-domain-cells = <1>;
2762 };
2763 };
2764
2765 thermal-zones {
2766 cpu0-thermal {
2014 polling-delay-passive = <250>;
2015 polling-delay = <1000>;
2767 polling-delay-passive = <0>;
2768 polling-delay = <0>;
2016
2017 thermal-sensors = <&tsens0 1>;
2018
2019 trips {
2020 cpu0_alert0: trip-point0 {
2021 temperature = <90000>;
2022 hysteresis = <2000>;
2023 type = "passive";

--- 30 unchanged lines hidden (view full) ---

2054 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2055 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2056 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2057 };
2058 };
2059 };
2060
2061 cpu1-thermal {
2769
2770 thermal-sensors = <&tsens0 1>;
2771
2772 trips {
2773 cpu0_alert0: trip-point0 {
2774 temperature = <90000>;
2775 hysteresis = <2000>;
2776 type = "passive";

--- 30 unchanged lines hidden (view full) ---

2807 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2808 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2809 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2810 };
2811 };
2812 };
2813
2814 cpu1-thermal {
2062 polling-delay-passive = <250>;
2063 polling-delay = <1000>;
2815 polling-delay-passive = <0>;
2816 polling-delay = <0>;
2064
2065 thermal-sensors = <&tsens0 2>;
2066
2067 trips {
2068 cpu1_alert0: trip-point0 {
2069 temperature = <90000>;
2070 hysteresis = <2000>;
2071 type = "passive";

--- 30 unchanged lines hidden (view full) ---

2102 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2103 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2104 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2105 };
2106 };
2107 };
2108
2109 cpu2-thermal {
2817
2818 thermal-sensors = <&tsens0 2>;
2819
2820 trips {
2821 cpu1_alert0: trip-point0 {
2822 temperature = <90000>;
2823 hysteresis = <2000>;
2824 type = "passive";

--- 30 unchanged lines hidden (view full) ---

2855 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2856 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2857 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2858 };
2859 };
2860 };
2861
2862 cpu2-thermal {
2110 polling-delay-passive = <250>;
2111 polling-delay = <1000>;
2863 polling-delay-passive = <0>;
2864 polling-delay = <0>;
2112
2113 thermal-sensors = <&tsens0 3>;
2114
2115 trips {
2116 cpu2_alert0: trip-point0 {
2117 temperature = <90000>;
2118 hysteresis = <2000>;
2119 type = "passive";

--- 30 unchanged lines hidden (view full) ---

2150 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2151 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2152 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2153 };
2154 };
2155 };
2156
2157 cpu3-thermal {
2865
2866 thermal-sensors = <&tsens0 3>;
2867
2868 trips {
2869 cpu2_alert0: trip-point0 {
2870 temperature = <90000>;
2871 hysteresis = <2000>;
2872 type = "passive";

--- 30 unchanged lines hidden (view full) ---

2903 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2904 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2905 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2906 };
2907 };
2908 };
2909
2910 cpu3-thermal {
2158 polling-delay-passive = <250>;
2159 polling-delay = <1000>;
2911 polling-delay-passive = <0>;
2912 polling-delay = <0>;
2160
2161 thermal-sensors = <&tsens0 4>;
2162
2163 trips {
2164 cpu3_alert0: trip-point0 {
2165 temperature = <90000>;
2166 hysteresis = <2000>;
2167 type = "passive";

--- 30 unchanged lines hidden (view full) ---

2198 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2199 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2200 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2201 };
2202 };
2203 };
2204
2205 cpu4-thermal {
2913
2914 thermal-sensors = <&tsens0 4>;
2915
2916 trips {
2917 cpu3_alert0: trip-point0 {
2918 temperature = <90000>;
2919 hysteresis = <2000>;
2920 type = "passive";

--- 30 unchanged lines hidden (view full) ---

2951 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2952 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2953 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2954 };
2955 };
2956 };
2957
2958 cpu4-thermal {
2206 polling-delay-passive = <250>;
2207 polling-delay = <1000>;
2959 polling-delay-passive = <0>;
2960 polling-delay = <0>;
2208
2209 thermal-sensors = <&tsens0 5>;
2210
2211 trips {
2212 cpu4_alert0: trip-point0 {
2213 temperature = <90000>;
2214 hysteresis = <2000>;
2215 type = "passive";

--- 30 unchanged lines hidden (view full) ---

2246 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2247 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2248 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2249 };
2250 };
2251 };
2252
2253 cpu5-thermal {
2961
2962 thermal-sensors = <&tsens0 5>;
2963
2964 trips {
2965 cpu4_alert0: trip-point0 {
2966 temperature = <90000>;
2967 hysteresis = <2000>;
2968 type = "passive";

--- 30 unchanged lines hidden (view full) ---

2999 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3000 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3001 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3002 };
3003 };
3004 };
3005
3006 cpu5-thermal {
2254 polling-delay-passive = <250>;
2255 polling-delay = <1000>;
3007 polling-delay-passive = <0>;
3008 polling-delay = <0>;
2256
2257 thermal-sensors = <&tsens0 6>;
2258
2259 trips {
2260 cpu5_alert0: trip-point0 {
2261 temperature = <90000>;
2262 hysteresis = <2000>;
2263 type = "passive";

--- 30 unchanged lines hidden (view full) ---

2294 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2295 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2296 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2297 };
2298 };
2299 };
2300
2301 cpu6-thermal {
3009
3010 thermal-sensors = <&tsens0 6>;
3011
3012 trips {
3013 cpu5_alert0: trip-point0 {
3014 temperature = <90000>;
3015 hysteresis = <2000>;
3016 type = "passive";

--- 30 unchanged lines hidden (view full) ---

3047 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3048 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3049 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3050 };
3051 };
3052 };
3053
3054 cpu6-thermal {
2302 polling-delay-passive = <250>;
2303 polling-delay = <1000>;
3055 polling-delay-passive = <0>;
3056 polling-delay = <0>;
2304
2305 thermal-sensors = <&tsens0 9>;
2306
2307 trips {
2308 cpu6_alert0: trip-point0 {
2309 temperature = <90000>;
2310 hysteresis = <2000>;
2311 type = "passive";

--- 22 unchanged lines hidden (view full) ---

2334 trip = <&cpu6_alert1>;
2335 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2336 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2337 };
2338 };
2339 };
2340
2341 cpu7-thermal {
3057
3058 thermal-sensors = <&tsens0 9>;
3059
3060 trips {
3061 cpu6_alert0: trip-point0 {
3062 temperature = <90000>;
3063 hysteresis = <2000>;
3064 type = "passive";

--- 22 unchanged lines hidden (view full) ---

3087 trip = <&cpu6_alert1>;
3088 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3089 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3090 };
3091 };
3092 };
3093
3094 cpu7-thermal {
2342 polling-delay-passive = <250>;
2343 polling-delay = <1000>;
3095 polling-delay-passive = <0>;
3096 polling-delay = <0>;
2344
2345 thermal-sensors = <&tsens0 10>;
2346
2347 trips {
2348 cpu7_alert0: trip-point0 {
2349 temperature = <90000>;
2350 hysteresis = <2000>;
2351 type = "passive";

--- 22 unchanged lines hidden (view full) ---

2374 trip = <&cpu7_alert1>;
2375 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2376 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2377 };
2378 };
2379 };
2380
2381 cpu8-thermal {
3097
3098 thermal-sensors = <&tsens0 10>;
3099
3100 trips {
3101 cpu7_alert0: trip-point0 {
3102 temperature = <90000>;
3103 hysteresis = <2000>;
3104 type = "passive";

--- 22 unchanged lines hidden (view full) ---

3127 trip = <&cpu7_alert1>;
3128 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3129 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3130 };
3131 };
3132 };
3133
3134 cpu8-thermal {
2382 polling-delay-passive = <250>;
2383 polling-delay = <1000>;
3135 polling-delay-passive = <0>;
3136 polling-delay = <0>;
2384
2385 thermal-sensors = <&tsens0 11>;
2386
2387 trips {
2388 cpu8_alert0: trip-point0 {
2389 temperature = <90000>;
2390 hysteresis = <2000>;
2391 type = "passive";

--- 22 unchanged lines hidden (view full) ---

2414 trip = <&cpu8_alert1>;
2415 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2416 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2417 };
2418 };
2419 };
2420
2421 cpu9-thermal {
3137
3138 thermal-sensors = <&tsens0 11>;
3139
3140 trips {
3141 cpu8_alert0: trip-point0 {
3142 temperature = <90000>;
3143 hysteresis = <2000>;
3144 type = "passive";

--- 22 unchanged lines hidden (view full) ---

3167 trip = <&cpu8_alert1>;
3168 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3169 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3170 };
3171 };
3172 };
3173
3174 cpu9-thermal {
2422 polling-delay-passive = <250>;
2423 polling-delay = <1000>;
3175 polling-delay-passive = <0>;
3176 polling-delay = <0>;
2424
2425 thermal-sensors = <&tsens0 12>;
2426
2427 trips {
2428 cpu9_alert0: trip-point0 {
2429 temperature = <90000>;
2430 hysteresis = <2000>;
2431 type = "passive";

--- 22 unchanged lines hidden (view full) ---

2454 trip = <&cpu9_alert1>;
2455 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2456 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2457 };
2458 };
2459 };
2460
2461 aoss0-thermal {
3177
3178 thermal-sensors = <&tsens0 12>;
3179
3180 trips {
3181 cpu9_alert0: trip-point0 {
3182 temperature = <90000>;
3183 hysteresis = <2000>;
3184 type = "passive";

--- 22 unchanged lines hidden (view full) ---

3207 trip = <&cpu9_alert1>;
3208 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3209 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3210 };
3211 };
3212 };
3213
3214 aoss0-thermal {
2462 polling-delay-passive = <250>;
2463 polling-delay = <1000>;
3215 polling-delay-passive = <0>;
3216 polling-delay = <0>;
2464
2465 thermal-sensors = <&tsens0 0>;
2466
2467 trips {
2468 aoss0_alert0: trip-point0 {
2469 temperature = <90000>;
2470 hysteresis = <2000>;
2471 type = "hot";
2472 };
2473
2474 aoss0_crit: aoss0_crit {
2475 temperature = <110000>;
2476 hysteresis = <2000>;
2477 type = "critical";
2478 };
2479 };
2480 };
2481
2482 cpuss0-thermal {
3217
3218 thermal-sensors = <&tsens0 0>;
3219
3220 trips {
3221 aoss0_alert0: trip-point0 {
3222 temperature = <90000>;
3223 hysteresis = <2000>;
3224 type = "hot";
3225 };
3226
3227 aoss0_crit: aoss0_crit {
3228 temperature = <110000>;
3229 hysteresis = <2000>;
3230 type = "critical";
3231 };
3232 };
3233 };
3234
3235 cpuss0-thermal {
2483 polling-delay-passive = <250>;
2484 polling-delay = <1000>;
3236 polling-delay-passive = <0>;
3237 polling-delay = <0>;
2485
2486 thermal-sensors = <&tsens0 7>;
2487
2488 trips {
2489 cpuss0_alert0: trip-point0 {
2490 temperature = <90000>;
2491 hysteresis = <2000>;
2492 type = "hot";
2493 };
2494 cpuss0_crit: cluster0_crit {
2495 temperature = <110000>;
2496 hysteresis = <2000>;
2497 type = "critical";
2498 };
2499 };
2500 };
2501
2502 cpuss1-thermal {
3238
3239 thermal-sensors = <&tsens0 7>;
3240
3241 trips {
3242 cpuss0_alert0: trip-point0 {
3243 temperature = <90000>;
3244 hysteresis = <2000>;
3245 type = "hot";
3246 };
3247 cpuss0_crit: cluster0_crit {
3248 temperature = <110000>;
3249 hysteresis = <2000>;
3250 type = "critical";
3251 };
3252 };
3253 };
3254
3255 cpuss1-thermal {
2503 polling-delay-passive = <250>;
2504 polling-delay = <1000>;
3256 polling-delay-passive = <0>;
3257 polling-delay = <0>;
2505
2506 thermal-sensors = <&tsens0 8>;
2507
2508 trips {
2509 cpuss1_alert0: trip-point0 {
2510 temperature = <90000>;
2511 hysteresis = <2000>;
2512 type = "hot";
2513 };
2514 cpuss1_crit: cluster0_crit {
2515 temperature = <110000>;
2516 hysteresis = <2000>;
2517 type = "critical";
2518 };
2519 };
2520 };
2521
2522 gpuss0-thermal {
3258
3259 thermal-sensors = <&tsens0 8>;
3260
3261 trips {
3262 cpuss1_alert0: trip-point0 {
3263 temperature = <90000>;
3264 hysteresis = <2000>;
3265 type = "hot";
3266 };
3267 cpuss1_crit: cluster0_crit {
3268 temperature = <110000>;
3269 hysteresis = <2000>;
3270 type = "critical";
3271 };
3272 };
3273 };
3274
3275 gpuss0-thermal {
2523 polling-delay-passive = <250>;
2524 polling-delay = <1000>;
3276 polling-delay-passive = <0>;
3277 polling-delay = <0>;
2525
2526 thermal-sensors = <&tsens0 13>;
2527
2528 trips {
2529 gpuss0_alert0: trip-point0 {
2530 temperature = <90000>;
2531 hysteresis = <2000>;
2532 type = "hot";
2533 };
2534
2535 gpuss0_crit: gpuss0_crit {
2536 temperature = <110000>;
2537 hysteresis = <2000>;
2538 type = "critical";
2539 };
2540 };
2541 };
2542
2543 gpuss1-thermal {
3278
3279 thermal-sensors = <&tsens0 13>;
3280
3281 trips {
3282 gpuss0_alert0: trip-point0 {
3283 temperature = <90000>;
3284 hysteresis = <2000>;
3285 type = "hot";
3286 };
3287
3288 gpuss0_crit: gpuss0_crit {
3289 temperature = <110000>;
3290 hysteresis = <2000>;
3291 type = "critical";
3292 };
3293 };
3294 };
3295
3296 gpuss1-thermal {
2544 polling-delay-passive = <250>;
2545 polling-delay = <1000>;
3297 polling-delay-passive = <0>;
3298 polling-delay = <0>;
2546
2547 thermal-sensors = <&tsens0 14>;
2548
2549 trips {
2550 gpuss1_alert0: trip-point0 {
2551 temperature = <90000>;
2552 hysteresis = <2000>;
2553 type = "hot";
2554 };
2555
2556 gpuss1_crit: gpuss1_crit {
2557 temperature = <110000>;
2558 hysteresis = <2000>;
2559 type = "critical";
2560 };
2561 };
2562 };
2563
2564 aoss1-thermal {
3299
3300 thermal-sensors = <&tsens0 14>;
3301
3302 trips {
3303 gpuss1_alert0: trip-point0 {
3304 temperature = <90000>;
3305 hysteresis = <2000>;
3306 type = "hot";
3307 };
3308
3309 gpuss1_crit: gpuss1_crit {
3310 temperature = <110000>;
3311 hysteresis = <2000>;
3312 type = "critical";
3313 };
3314 };
3315 };
3316
3317 aoss1-thermal {
2565 polling-delay-passive = <250>;
2566 polling-delay = <1000>;
3318 polling-delay-passive = <0>;
3319 polling-delay = <0>;
2567
2568 thermal-sensors = <&tsens1 0>;
2569
2570 trips {
2571 aoss1_alert0: trip-point0 {
2572 temperature = <90000>;
2573 hysteresis = <2000>;
2574 type = "hot";
2575 };
2576
2577 aoss1_crit: aoss1_crit {
2578 temperature = <110000>;
2579 hysteresis = <2000>;
2580 type = "critical";
2581 };
2582 };
2583 };
2584
2585 cwlan-thermal {
3320
3321 thermal-sensors = <&tsens1 0>;
3322
3323 trips {
3324 aoss1_alert0: trip-point0 {
3325 temperature = <90000>;
3326 hysteresis = <2000>;
3327 type = "hot";
3328 };
3329
3330 aoss1_crit: aoss1_crit {
3331 temperature = <110000>;
3332 hysteresis = <2000>;
3333 type = "critical";
3334 };
3335 };
3336 };
3337
3338 cwlan-thermal {
2586 polling-delay-passive = <250>;
2587 polling-delay = <1000>;
3339 polling-delay-passive = <0>;
3340 polling-delay = <0>;
2588
2589 thermal-sensors = <&tsens1 1>;
2590
2591 trips {
2592 cwlan_alert0: trip-point0 {
2593 temperature = <90000>;
2594 hysteresis = <2000>;
2595 type = "hot";
2596 };
2597
2598 cwlan_crit: cwlan_crit {
2599 temperature = <110000>;
2600 hysteresis = <2000>;
2601 type = "critical";
2602 };
2603 };
2604 };
2605
2606 audio-thermal {
3341
3342 thermal-sensors = <&tsens1 1>;
3343
3344 trips {
3345 cwlan_alert0: trip-point0 {
3346 temperature = <90000>;
3347 hysteresis = <2000>;
3348 type = "hot";
3349 };
3350
3351 cwlan_crit: cwlan_crit {
3352 temperature = <110000>;
3353 hysteresis = <2000>;
3354 type = "critical";
3355 };
3356 };
3357 };
3358
3359 audio-thermal {
2607 polling-delay-passive = <250>;
2608 polling-delay = <1000>;
3360 polling-delay-passive = <0>;
3361 polling-delay = <0>;
2609
2610 thermal-sensors = <&tsens1 2>;
2611
2612 trips {
2613 audio_alert0: trip-point0 {
2614 temperature = <90000>;
2615 hysteresis = <2000>;
2616 type = "hot";
2617 };
2618
2619 audio_crit: audio_crit {
2620 temperature = <110000>;
2621 hysteresis = <2000>;
2622 type = "critical";
2623 };
2624 };
2625 };
2626
2627 ddr-thermal {
3362
3363 thermal-sensors = <&tsens1 2>;
3364
3365 trips {
3366 audio_alert0: trip-point0 {
3367 temperature = <90000>;
3368 hysteresis = <2000>;
3369 type = "hot";
3370 };
3371
3372 audio_crit: audio_crit {
3373 temperature = <110000>;
3374 hysteresis = <2000>;
3375 type = "critical";
3376 };
3377 };
3378 };
3379
3380 ddr-thermal {
2628 polling-delay-passive = <250>;
2629 polling-delay = <1000>;
3381 polling-delay-passive = <0>;
3382 polling-delay = <0>;
2630
2631 thermal-sensors = <&tsens1 3>;
2632
2633 trips {
2634 ddr_alert0: trip-point0 {
2635 temperature = <90000>;
2636 hysteresis = <2000>;
2637 type = "hot";
2638 };
2639
2640 ddr_crit: ddr_crit {
2641 temperature = <110000>;
2642 hysteresis = <2000>;
2643 type = "critical";
2644 };
2645 };
2646 };
2647
2648 q6-hvx-thermal {
3383
3384 thermal-sensors = <&tsens1 3>;
3385
3386 trips {
3387 ddr_alert0: trip-point0 {
3388 temperature = <90000>;
3389 hysteresis = <2000>;
3390 type = "hot";
3391 };
3392
3393 ddr_crit: ddr_crit {
3394 temperature = <110000>;
3395 hysteresis = <2000>;
3396 type = "critical";
3397 };
3398 };
3399 };
3400
3401 q6-hvx-thermal {
2649 polling-delay-passive = <250>;
2650 polling-delay = <1000>;
3402 polling-delay-passive = <0>;
3403 polling-delay = <0>;
2651
2652 thermal-sensors = <&tsens1 4>;
2653
2654 trips {
2655 q6_hvx_alert0: trip-point0 {
2656 temperature = <90000>;
2657 hysteresis = <2000>;
2658 type = "hot";
2659 };
2660
2661 q6_hvx_crit: q6_hvx_crit {
2662 temperature = <110000>;
2663 hysteresis = <2000>;
2664 type = "critical";
2665 };
2666 };
2667 };
2668
2669 camera-thermal {
3404
3405 thermal-sensors = <&tsens1 4>;
3406
3407 trips {
3408 q6_hvx_alert0: trip-point0 {
3409 temperature = <90000>;
3410 hysteresis = <2000>;
3411 type = "hot";
3412 };
3413
3414 q6_hvx_crit: q6_hvx_crit {
3415 temperature = <110000>;
3416 hysteresis = <2000>;
3417 type = "critical";
3418 };
3419 };
3420 };
3421
3422 camera-thermal {
2670 polling-delay-passive = <250>;
2671 polling-delay = <1000>;
3423 polling-delay-passive = <0>;
3424 polling-delay = <0>;
2672
2673 thermal-sensors = <&tsens1 5>;
2674
2675 trips {
2676 camera_alert0: trip-point0 {
2677 temperature = <90000>;
2678 hysteresis = <2000>;
2679 type = "hot";
2680 };
2681
2682 camera_crit: camera_crit {
2683 temperature = <110000>;
2684 hysteresis = <2000>;
2685 type = "critical";
2686 };
2687 };
2688 };
2689
2690 mdm-core-thermal {
3425
3426 thermal-sensors = <&tsens1 5>;
3427
3428 trips {
3429 camera_alert0: trip-point0 {
3430 temperature = <90000>;
3431 hysteresis = <2000>;
3432 type = "hot";
3433 };
3434
3435 camera_crit: camera_crit {
3436 temperature = <110000>;
3437 hysteresis = <2000>;
3438 type = "critical";
3439 };
3440 };
3441 };
3442
3443 mdm-core-thermal {
2691 polling-delay-passive = <250>;
2692 polling-delay = <1000>;
3444 polling-delay-passive = <0>;
3445 polling-delay = <0>;
2693
2694 thermal-sensors = <&tsens1 6>;
2695
2696 trips {
2697 mdm_alert0: trip-point0 {
2698 temperature = <90000>;
2699 hysteresis = <2000>;
2700 type = "hot";
2701 };
2702
2703 mdm_crit: mdm_crit {
2704 temperature = <110000>;
2705 hysteresis = <2000>;
2706 type = "critical";
2707 };
2708 };
2709 };
2710
2711 mdm-dsp-thermal {
3446
3447 thermal-sensors = <&tsens1 6>;
3448
3449 trips {
3450 mdm_alert0: trip-point0 {
3451 temperature = <90000>;
3452 hysteresis = <2000>;
3453 type = "hot";
3454 };
3455
3456 mdm_crit: mdm_crit {
3457 temperature = <110000>;
3458 hysteresis = <2000>;
3459 type = "critical";
3460 };
3461 };
3462 };
3463
3464 mdm-dsp-thermal {
2712 polling-delay-passive = <250>;
2713 polling-delay = <1000>;
3465 polling-delay-passive = <0>;
3466 polling-delay = <0>;
2714
2715 thermal-sensors = <&tsens1 7>;
2716
2717 trips {
2718 mdm_dsp_alert0: trip-point0 {
2719 temperature = <90000>;
2720 hysteresis = <2000>;
2721 type = "hot";
2722 };
2723
2724 mdm_dsp_crit: mdm_dsp_crit {
2725 temperature = <110000>;
2726 hysteresis = <2000>;
2727 type = "critical";
2728 };
2729 };
2730 };
2731
2732 npu-thermal {
3467
3468 thermal-sensors = <&tsens1 7>;
3469
3470 trips {
3471 mdm_dsp_alert0: trip-point0 {
3472 temperature = <90000>;
3473 hysteresis = <2000>;
3474 type = "hot";
3475 };
3476
3477 mdm_dsp_crit: mdm_dsp_crit {
3478 temperature = <110000>;
3479 hysteresis = <2000>;
3480 type = "critical";
3481 };
3482 };
3483 };
3484
3485 npu-thermal {
2733 polling-delay-passive = <250>;
2734 polling-delay = <1000>;
3486 polling-delay-passive = <0>;
3487 polling-delay = <0>;
2735
2736 thermal-sensors = <&tsens1 8>;
2737
2738 trips {
2739 npu_alert0: trip-point0 {
2740 temperature = <90000>;
2741 hysteresis = <2000>;
2742 type = "hot";
2743 };
2744
2745 npu_crit: npu_crit {
2746 temperature = <110000>;
2747 hysteresis = <2000>;
2748 type = "critical";
2749 };
2750 };
2751 };
2752
2753 video-thermal {
3488
3489 thermal-sensors = <&tsens1 8>;
3490
3491 trips {
3492 npu_alert0: trip-point0 {
3493 temperature = <90000>;
3494 hysteresis = <2000>;
3495 type = "hot";
3496 };
3497
3498 npu_crit: npu_crit {
3499 temperature = <110000>;
3500 hysteresis = <2000>;
3501 type = "critical";
3502 };
3503 };
3504 };
3505
3506 video-thermal {
2754 polling-delay-passive = <250>;
2755 polling-delay = <1000>;
3507 polling-delay-passive = <0>;
3508 polling-delay = <0>;
2756
2757 thermal-sensors = <&tsens1 9>;
2758
2759 trips {
2760 video_alert0: trip-point0 {
2761 temperature = <90000>;
2762 hysteresis = <2000>;
2763 type = "hot";

--- 19 unchanged lines hidden --- 		3509
3510 thermal-sensors = <&tsens1 9>;
3511
3512 trips {
3513 video_alert0: trip-point0 {
3514 temperature = <90000>;
3515 hysteresis = <2000>;
3516 type = "hot";

--- 19 unchanged lines hidden ---