1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * SC7180 SoC device tree source 4 * 5 * Copyright (c) 2019, The Linux Foundation. All rights reserved. 6 */ 7 8#include <dt-bindings/clock/qcom,dispcc-sc7180.h> 9#include <dt-bindings/clock/qcom,gcc-sc7180.h> 10#include <dt-bindings/clock/qcom,gpucc-sc7180.h> 11#include <dt-bindings/clock/qcom,rpmh.h> 12#include <dt-bindings/clock/qcom,videocc-sc7180.h> 13#include <dt-bindings/interconnect/qcom,sc7180.h> 14#include <dt-bindings/interrupt-controller/arm-gic.h> 15#include <dt-bindings/phy/phy-qcom-qusb2.h> 16#include <dt-bindings/power/qcom-aoss-qmp.h> 17#include <dt-bindings/power/qcom-rpmpd.h> 18#include <dt-bindings/reset/qcom,sdm845-aoss.h> 19#include <dt-bindings/reset/qcom,sdm845-pdc.h> 20#include <dt-bindings/soc/qcom,rpmh-rsc.h> 21#include <dt-bindings/thermal/thermal.h> 22 23/ { 24 interrupt-parent = <&intc>; 25 26 #address-cells = <2>; 27 #size-cells = <2>; 28 29 chosen { }; 30 31 aliases { 32 i2c0 = &i2c0; 33 i2c1 = &i2c1; 34 i2c2 = &i2c2; 35 i2c3 = &i2c3; 36 i2c4 = &i2c4; 37 i2c5 = &i2c5; 38 i2c6 = &i2c6; 39 i2c7 = &i2c7; 40 i2c8 = &i2c8; 41 i2c9 = &i2c9; 42 i2c10 = &i2c10; 43 i2c11 = &i2c11; 44 spi0 = &spi0; 45 spi1 = &spi1; 46 spi3 = &spi3; 47 spi5 = &spi5; 48 spi6 = &spi6; 49 spi8 = &spi8; 50 spi10 = &spi10; 51 spi11 = &spi11; 52 }; 53 54 clocks { 55 xo_board: xo-board { 56 compatible = "fixed-clock"; 57 clock-frequency = <38400000>; 58 #clock-cells = <0>; 59 }; 60 61 sleep_clk: sleep-clk { 62 compatible = "fixed-clock"; 63 clock-frequency = <32764>; 64 #clock-cells = <0>; 65 }; 66 }; 67 68 reserved_memory: reserved-memory { 69 #address-cells = <2>; 70 #size-cells = <2>; 71 ranges; 72 73 hyp_mem: memory@80000000 { 74 reg = <0x0 0x80000000 0x0 0x600000>; 75 no-map; 76 }; 77 78 xbl_mem: memory@80600000 { 79 reg = <0x0 0x80600000 0x0 0x200000>; 80 no-map; 81 }; 82 83 aop_mem: memory@80800000 { 84 reg = <0x0 0x80800000 0x0 0x20000>; 85 no-map; 86 }; 87 88 aop_cmd_db_mem: memory@80820000 { 89 reg = <0x0 0x80820000 0x0 0x20000>; 90 compatible = "qcom,cmd-db"; 91 no-map; 92 }; 93 94 sec_apps_mem: memory@808ff000 { 95 reg = <0x0 0x808ff000 0x0 0x1000>; 96 no-map; 97 }; 98 99 smem_mem: memory@80900000 { 100 reg = <0x0 0x80900000 0x0 0x200000>; 101 no-map; 102 }; 103 104 tz_mem: memory@80b00000 { 105 reg = <0x0 0x80b00000 0x0 0x3900000>; 106 no-map; 107 }; 108 109 rmtfs_mem: memory@84400000 { 110 compatible = "qcom,rmtfs-mem"; 111 reg = <0x0 0x84400000 0x0 0x200000>; 112 no-map; 113 114 qcom,client-id = <1>; 115 qcom,vmid = <15>; 116 }; 117 }; 118 119 cpus { 120 #address-cells = <2>; 121 #size-cells = <0>; 122 123 CPU0: cpu@0 { 124 device_type = "cpu"; 125 compatible = "qcom,kryo468"; 126 reg = <0x0 0x0>; 127 enable-method = "psci"; 128 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 129 &LITTLE_CPU_SLEEP_1 130 &CLUSTER_SLEEP_0>; 131 capacity-dmips-mhz = <1024>; 132 dynamic-power-coefficient = <100>; 133 next-level-cache = <&L2_0>; 134 #cooling-cells = <2>; 135 qcom,freq-domain = <&cpufreq_hw 0>; 136 L2_0: l2-cache { 137 compatible = "cache"; 138 next-level-cache = <&L3_0>; 139 L3_0: l3-cache { 140 compatible = "cache"; 141 }; 142 }; 143 }; 144 145 CPU1: cpu@100 { 146 device_type = "cpu"; 147 compatible = "qcom,kryo468"; 148 reg = <0x0 0x100>; 149 enable-method = "psci"; 150 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 151 &LITTLE_CPU_SLEEP_1 152 &CLUSTER_SLEEP_0>; 153 capacity-dmips-mhz = <1024>; 154 dynamic-power-coefficient = <100>; 155 next-level-cache = <&L2_100>; 156 #cooling-cells = <2>; 157 qcom,freq-domain = <&cpufreq_hw 0>; 158 L2_100: l2-cache { 159 compatible = "cache"; 160 next-level-cache = <&L3_0>; 161 }; 162 }; 163 164 CPU2: cpu@200 { 165 device_type = "cpu"; 166 compatible = "qcom,kryo468"; 167 reg = <0x0 0x200>; 168 enable-method = "psci"; 169 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 170 &LITTLE_CPU_SLEEP_1 171 &CLUSTER_SLEEP_0>; 172 capacity-dmips-mhz = <1024>; 173 dynamic-power-coefficient = <100>; 174 next-level-cache = <&L2_200>; 175 #cooling-cells = <2>; 176 qcom,freq-domain = <&cpufreq_hw 0>; 177 L2_200: l2-cache { 178 compatible = "cache"; 179 next-level-cache = <&L3_0>; 180 }; 181 }; 182 183 CPU3: cpu@300 { 184 device_type = "cpu"; 185 compatible = "qcom,kryo468"; 186 reg = <0x0 0x300>; 187 enable-method = "psci"; 188 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 189 &LITTLE_CPU_SLEEP_1 190 &CLUSTER_SLEEP_0>; 191 capacity-dmips-mhz = <1024>; 192 dynamic-power-coefficient = <100>; 193 next-level-cache = <&L2_300>; 194 #cooling-cells = <2>; 195 qcom,freq-domain = <&cpufreq_hw 0>; 196 L2_300: l2-cache { 197 compatible = "cache"; 198 next-level-cache = <&L3_0>; 199 }; 200 }; 201 202 CPU4: cpu@400 { 203 device_type = "cpu"; 204 compatible = "qcom,kryo468"; 205 reg = <0x0 0x400>; 206 enable-method = "psci"; 207 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 208 &LITTLE_CPU_SLEEP_1 209 &CLUSTER_SLEEP_0>; 210 capacity-dmips-mhz = <1024>; 211 dynamic-power-coefficient = <100>; 212 next-level-cache = <&L2_400>; 213 #cooling-cells = <2>; 214 qcom,freq-domain = <&cpufreq_hw 0>; 215 L2_400: l2-cache { 216 compatible = "cache"; 217 next-level-cache = <&L3_0>; 218 }; 219 }; 220 221 CPU5: cpu@500 { 222 device_type = "cpu"; 223 compatible = "qcom,kryo468"; 224 reg = <0x0 0x500>; 225 enable-method = "psci"; 226 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 227 &LITTLE_CPU_SLEEP_1 228 &CLUSTER_SLEEP_0>; 229 capacity-dmips-mhz = <1024>; 230 dynamic-power-coefficient = <100>; 231 next-level-cache = <&L2_500>; 232 #cooling-cells = <2>; 233 qcom,freq-domain = <&cpufreq_hw 0>; 234 L2_500: l2-cache { 235 compatible = "cache"; 236 next-level-cache = <&L3_0>; 237 }; 238 }; 239 240 CPU6: cpu@600 { 241 device_type = "cpu"; 242 compatible = "qcom,kryo468"; 243 reg = <0x0 0x600>; 244 enable-method = "psci"; 245 cpu-idle-states = <&BIG_CPU_SLEEP_0 246 &BIG_CPU_SLEEP_1 247 &CLUSTER_SLEEP_0>; 248 capacity-dmips-mhz = <1740>; 249 dynamic-power-coefficient = <405>; 250 next-level-cache = <&L2_600>; 251 #cooling-cells = <2>; 252 qcom,freq-domain = <&cpufreq_hw 1>; 253 L2_600: l2-cache { 254 compatible = "cache"; 255 next-level-cache = <&L3_0>; 256 }; 257 }; 258 259 CPU7: cpu@700 { 260 device_type = "cpu"; 261 compatible = "qcom,kryo468"; 262 reg = <0x0 0x700>; 263 enable-method = "psci"; 264 cpu-idle-states = <&BIG_CPU_SLEEP_0 265 &BIG_CPU_SLEEP_1 266 &CLUSTER_SLEEP_0>; 267 capacity-dmips-mhz = <1740>; 268 dynamic-power-coefficient = <405>; 269 next-level-cache = <&L2_700>; 270 #cooling-cells = <2>; 271 qcom,freq-domain = <&cpufreq_hw 1>; 272 L2_700: l2-cache { 273 compatible = "cache"; 274 next-level-cache = <&L3_0>; 275 }; 276 }; 277 278 cpu-map { 279 cluster0 { 280 core0 { 281 cpu = <&CPU0>; 282 }; 283 284 core1 { 285 cpu = <&CPU1>; 286 }; 287 288 core2 { 289 cpu = <&CPU2>; 290 }; 291 292 core3 { 293 cpu = <&CPU3>; 294 }; 295 296 core4 { 297 cpu = <&CPU4>; 298 }; 299 300 core5 { 301 cpu = <&CPU5>; 302 }; 303 304 core6 { 305 cpu = <&CPU6>; 306 }; 307 308 core7 { 309 cpu = <&CPU7>; 310 }; 311 }; 312 }; 313 314 idle-states { 315 entry-method = "psci"; 316 317 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 318 compatible = "arm,idle-state"; 319 idle-state-name = "little-power-down"; 320 arm,psci-suspend-param = <0x40000003>; 321 entry-latency-us = <549>; 322 exit-latency-us = <901>; 323 min-residency-us = <1774>; 324 local-timer-stop; 325 }; 326 327 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { 328 compatible = "arm,idle-state"; 329 idle-state-name = "little-rail-power-down"; 330 arm,psci-suspend-param = <0x40000004>; 331 entry-latency-us = <702>; 332 exit-latency-us = <915>; 333 min-residency-us = <4001>; 334 local-timer-stop; 335 }; 336 337 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 338 compatible = "arm,idle-state"; 339 idle-state-name = "big-power-down"; 340 arm,psci-suspend-param = <0x40000003>; 341 entry-latency-us = <523>; 342 exit-latency-us = <1244>; 343 min-residency-us = <2207>; 344 local-timer-stop; 345 }; 346 347 BIG_CPU_SLEEP_1: cpu-sleep-1-1 { 348 compatible = "arm,idle-state"; 349 idle-state-name = "big-rail-power-down"; 350 arm,psci-suspend-param = <0x40000004>; 351 entry-latency-us = <526>; 352 exit-latency-us = <1854>; 353 min-residency-us = <5555>; 354 local-timer-stop; 355 }; 356 357 CLUSTER_SLEEP_0: cluster-sleep-0 { 358 compatible = "arm,idle-state"; 359 idle-state-name = "cluster-power-down"; 360 arm,psci-suspend-param = <0x40003444>; 361 entry-latency-us = <3263>; 362 exit-latency-us = <6562>; 363 min-residency-us = <9926>; 364 local-timer-stop; 365 }; 366 }; 367 }; 368 369 memory@80000000 { 370 device_type = "memory"; 371 /* We expect the bootloader to fill in the size */ 372 reg = <0 0x80000000 0 0>; 373 }; 374 375 pmu { 376 compatible = "arm,armv8-pmuv3"; 377 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>; 378 }; 379 380 firmware { 381 scm { 382 compatible = "qcom,scm-sc7180", "qcom,scm"; 383 }; 384 }; 385 386 tcsr_mutex: hwlock { 387 compatible = "qcom,tcsr-mutex"; 388 syscon = <&tcsr_mutex_regs 0 0x1000>; 389 #hwlock-cells = <1>; 390 }; 391 392 smem { 393 compatible = "qcom,smem"; 394 memory-region = <&smem_mem>; 395 hwlocks = <&tcsr_mutex 3>; 396 }; 397 398 smp2p-cdsp { 399 compatible = "qcom,smp2p"; 400 qcom,smem = <94>, <432>; 401 402 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>; 403 404 mboxes = <&apss_shared 6>; 405 406 qcom,local-pid = <0>; 407 qcom,remote-pid = <5>; 408 409 cdsp_smp2p_out: master-kernel { 410 qcom,entry-name = "master-kernel"; 411 #qcom,smem-state-cells = <1>; 412 }; 413 414 cdsp_smp2p_in: slave-kernel { 415 qcom,entry-name = "slave-kernel"; 416 417 interrupt-controller; 418 #interrupt-cells = <2>; 419 }; 420 }; 421 422 smp2p-lpass { 423 compatible = "qcom,smp2p"; 424 qcom,smem = <443>, <429>; 425 426 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 427 428 mboxes = <&apss_shared 10>; 429 430 qcom,local-pid = <0>; 431 qcom,remote-pid = <2>; 432 433 adsp_smp2p_out: master-kernel { 434 qcom,entry-name = "master-kernel"; 435 #qcom,smem-state-cells = <1>; 436 }; 437 438 adsp_smp2p_in: slave-kernel { 439 qcom,entry-name = "slave-kernel"; 440 441 interrupt-controller; 442 #interrupt-cells = <2>; 443 }; 444 }; 445 446 smp2p-mpss { 447 compatible = "qcom,smp2p"; 448 qcom,smem = <435>, <428>; 449 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 450 mboxes = <&apss_shared 14>; 451 qcom,local-pid = <0>; 452 qcom,remote-pid = <1>; 453 454 modem_smp2p_out: master-kernel { 455 qcom,entry-name = "master-kernel"; 456 #qcom,smem-state-cells = <1>; 457 }; 458 459 modem_smp2p_in: slave-kernel { 460 qcom,entry-name = "slave-kernel"; 461 interrupt-controller; 462 #interrupt-cells = <2>; 463 }; 464 }; 465 466 psci { 467 compatible = "arm,psci-1.0"; 468 method = "smc"; 469 }; 470 471 soc: soc@0 { 472 #address-cells = <2>; 473 #size-cells = <2>; 474 ranges = <0 0 0 0 0x10 0>; 475 dma-ranges = <0 0 0 0 0x10 0>; 476 compatible = "simple-bus"; 477 478 gcc: clock-controller@100000 { 479 compatible = "qcom,gcc-sc7180"; 480 reg = <0 0x00100000 0 0x1f0000>; 481 clocks = <&rpmhcc RPMH_CXO_CLK>, 482 <&rpmhcc RPMH_CXO_CLK_A>, 483 <&sleep_clk>; 484 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; 485 #clock-cells = <1>; 486 #reset-cells = <1>; 487 #power-domain-cells = <1>; 488 }; 489 490 qfprom@784000 { 491 compatible = "qcom,qfprom"; 492 reg = <0 0x00784000 0 0x8ff>; 493 #address-cells = <1>; 494 #size-cells = <1>; 495 496 qusb2p_hstx_trim: hstx-trim-primary@25b { 497 reg = <0x25b 0x1>; 498 bits = <1 3>; 499 }; 500 }; 501 502 sdhc_1: sdhci@7c4000 { 503 compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5"; 504 reg = <0 0x7c4000 0 0x1000>, 505 <0 0x07c5000 0 0x1000>; 506 reg-names = "hc", "cqhci"; 507 508 iommus = <&apps_smmu 0x60 0x0>; 509 interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>, 510 <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>; 511 interrupt-names = "hc_irq", "pwr_irq"; 512 513 clocks = <&gcc GCC_SDCC1_APPS_CLK>, 514 <&gcc GCC_SDCC1_AHB_CLK>; 515 clock-names = "core", "iface"; 516 517 bus-width = <8>; 518 non-removable; 519 supports-cqe; 520 521 mmc-ddr-1_8v; 522 mmc-hs200-1_8v; 523 mmc-hs400-1_8v; 524 mmc-hs400-enhanced-strobe; 525 526 status = "disabled"; 527 }; 528 529 qupv3_id_0: geniqup@8c0000 { 530 compatible = "qcom,geni-se-qup"; 531 reg = <0 0x008c0000 0 0x6000>; 532 clock-names = "m-ahb", "s-ahb"; 533 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 534 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 535 #address-cells = <2>; 536 #size-cells = <2>; 537 ranges; 538 iommus = <&apps_smmu 0x43 0x0>; 539 status = "disabled"; 540 541 i2c0: i2c@880000 { 542 compatible = "qcom,geni-i2c"; 543 reg = <0 0x00880000 0 0x4000>; 544 clock-names = "se"; 545 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 546 pinctrl-names = "default"; 547 pinctrl-0 = <&qup_i2c0_default>; 548 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 549 #address-cells = <1>; 550 #size-cells = <0>; 551 status = "disabled"; 552 }; 553 554 spi0: spi@880000 { 555 compatible = "qcom,geni-spi"; 556 reg = <0 0x00880000 0 0x4000>; 557 clock-names = "se"; 558 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 559 pinctrl-names = "default"; 560 pinctrl-0 = <&qup_spi0_default>; 561 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 562 #address-cells = <1>; 563 #size-cells = <0>; 564 status = "disabled"; 565 }; 566 567 uart0: serial@880000 { 568 compatible = "qcom,geni-uart"; 569 reg = <0 0x00880000 0 0x4000>; 570 clock-names = "se"; 571 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 572 pinctrl-names = "default"; 573 pinctrl-0 = <&qup_uart0_default>; 574 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 575 status = "disabled"; 576 }; 577 578 i2c1: i2c@884000 { 579 compatible = "qcom,geni-i2c"; 580 reg = <0 0x00884000 0 0x4000>; 581 clock-names = "se"; 582 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 583 pinctrl-names = "default"; 584 pinctrl-0 = <&qup_i2c1_default>; 585 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 586 #address-cells = <1>; 587 #size-cells = <0>; 588 status = "disabled"; 589 }; 590 591 spi1: spi@884000 { 592 compatible = "qcom,geni-spi"; 593 reg = <0 0x00884000 0 0x4000>; 594 clock-names = "se"; 595 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 596 pinctrl-names = "default"; 597 pinctrl-0 = <&qup_spi1_default>; 598 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 599 #address-cells = <1>; 600 #size-cells = <0>; 601 status = "disabled"; 602 }; 603 604 uart1: serial@884000 { 605 compatible = "qcom,geni-uart"; 606 reg = <0 0x00884000 0 0x4000>; 607 clock-names = "se"; 608 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 609 pinctrl-names = "default"; 610 pinctrl-0 = <&qup_uart1_default>; 611 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 612 status = "disabled"; 613 }; 614 615 i2c2: i2c@888000 { 616 compatible = "qcom,geni-i2c"; 617 reg = <0 0x00888000 0 0x4000>; 618 clock-names = "se"; 619 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 620 pinctrl-names = "default"; 621 pinctrl-0 = <&qup_i2c2_default>; 622 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 623 #address-cells = <1>; 624 #size-cells = <0>; 625 status = "disabled"; 626 }; 627 628 uart2: serial@888000 { 629 compatible = "qcom,geni-uart"; 630 reg = <0 0x00888000 0 0x4000>; 631 clock-names = "se"; 632 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 633 pinctrl-names = "default"; 634 pinctrl-0 = <&qup_uart2_default>; 635 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 636 status = "disabled"; 637 }; 638 639 i2c3: i2c@88c000 { 640 compatible = "qcom,geni-i2c"; 641 reg = <0 0x0088c000 0 0x4000>; 642 clock-names = "se"; 643 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 644 pinctrl-names = "default"; 645 pinctrl-0 = <&qup_i2c3_default>; 646 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 647 #address-cells = <1>; 648 #size-cells = <0>; 649 status = "disabled"; 650 }; 651 652 spi3: spi@88c000 { 653 compatible = "qcom,geni-spi"; 654 reg = <0 0x0088c000 0 0x4000>; 655 clock-names = "se"; 656 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 657 pinctrl-names = "default"; 658 pinctrl-0 = <&qup_spi3_default>; 659 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 660 #address-cells = <1>; 661 #size-cells = <0>; 662 status = "disabled"; 663 }; 664 665 uart3: serial@88c000 { 666 compatible = "qcom,geni-uart"; 667 reg = <0 0x0088c000 0 0x4000>; 668 clock-names = "se"; 669 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 670 pinctrl-names = "default"; 671 pinctrl-0 = <&qup_uart3_default>; 672 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 673 status = "disabled"; 674 }; 675 676 i2c4: i2c@890000 { 677 compatible = "qcom,geni-i2c"; 678 reg = <0 0x00890000 0 0x4000>; 679 clock-names = "se"; 680 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 681 pinctrl-names = "default"; 682 pinctrl-0 = <&qup_i2c4_default>; 683 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 684 #address-cells = <1>; 685 #size-cells = <0>; 686 status = "disabled"; 687 }; 688 689 uart4: serial@890000 { 690 compatible = "qcom,geni-uart"; 691 reg = <0 0x00890000 0 0x4000>; 692 clock-names = "se"; 693 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 694 pinctrl-names = "default"; 695 pinctrl-0 = <&qup_uart4_default>; 696 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 697 status = "disabled"; 698 }; 699 700 i2c5: i2c@894000 { 701 compatible = "qcom,geni-i2c"; 702 reg = <0 0x00894000 0 0x4000>; 703 clock-names = "se"; 704 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 705 pinctrl-names = "default"; 706 pinctrl-0 = <&qup_i2c5_default>; 707 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 708 #address-cells = <1>; 709 #size-cells = <0>; 710 status = "disabled"; 711 }; 712 713 spi5: spi@894000 { 714 compatible = "qcom,geni-spi"; 715 reg = <0 0x00894000 0 0x4000>; 716 clock-names = "se"; 717 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 718 pinctrl-names = "default"; 719 pinctrl-0 = <&qup_spi5_default>; 720 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 721 #address-cells = <1>; 722 #size-cells = <0>; 723 status = "disabled"; 724 }; 725 726 uart5: serial@894000 { 727 compatible = "qcom,geni-uart"; 728 reg = <0 0x00894000 0 0x4000>; 729 clock-names = "se"; 730 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 731 pinctrl-names = "default"; 732 pinctrl-0 = <&qup_uart5_default>; 733 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 734 status = "disabled"; 735 }; 736 }; 737 738 qupv3_id_1: geniqup@ac0000 { 739 compatible = "qcom,geni-se-qup"; 740 reg = <0 0x00ac0000 0 0x6000>; 741 clock-names = "m-ahb", "s-ahb"; 742 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 743 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 744 #address-cells = <2>; 745 #size-cells = <2>; 746 ranges; 747 iommus = <&apps_smmu 0x4c3 0x0>; 748 status = "disabled"; 749 750 i2c6: i2c@a80000 { 751 compatible = "qcom,geni-i2c"; 752 reg = <0 0x00a80000 0 0x4000>; 753 clock-names = "se"; 754 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 755 pinctrl-names = "default"; 756 pinctrl-0 = <&qup_i2c6_default>; 757 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 758 #address-cells = <1>; 759 #size-cells = <0>; 760 status = "disabled"; 761 }; 762 763 spi6: spi@a80000 { 764 compatible = "qcom,geni-spi"; 765 reg = <0 0x00a80000 0 0x4000>; 766 clock-names = "se"; 767 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 768 pinctrl-names = "default"; 769 pinctrl-0 = <&qup_spi6_default>; 770 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 771 #address-cells = <1>; 772 #size-cells = <0>; 773 status = "disabled"; 774 }; 775 776 uart6: serial@a80000 { 777 compatible = "qcom,geni-uart"; 778 reg = <0 0x00a80000 0 0x4000>; 779 clock-names = "se"; 780 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 781 pinctrl-names = "default"; 782 pinctrl-0 = <&qup_uart6_default>; 783 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 784 status = "disabled"; 785 }; 786 787 i2c7: i2c@a84000 { 788 compatible = "qcom,geni-i2c"; 789 reg = <0 0x00a84000 0 0x4000>; 790 clock-names = "se"; 791 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 792 pinctrl-names = "default"; 793 pinctrl-0 = <&qup_i2c7_default>; 794 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 795 #address-cells = <1>; 796 #size-cells = <0>; 797 status = "disabled"; 798 }; 799 800 uart7: serial@a84000 { 801 compatible = "qcom,geni-uart"; 802 reg = <0 0x00a84000 0 0x4000>; 803 clock-names = "se"; 804 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 805 pinctrl-names = "default"; 806 pinctrl-0 = <&qup_uart7_default>; 807 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 808 status = "disabled"; 809 }; 810 811 i2c8: i2c@a88000 { 812 compatible = "qcom,geni-i2c"; 813 reg = <0 0x00a88000 0 0x4000>; 814 clock-names = "se"; 815 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 816 pinctrl-names = "default"; 817 pinctrl-0 = <&qup_i2c8_default>; 818 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 819 #address-cells = <1>; 820 #size-cells = <0>; 821 status = "disabled"; 822 }; 823 824 spi8: spi@a88000 { 825 compatible = "qcom,geni-spi"; 826 reg = <0 0x00a88000 0 0x4000>; 827 clock-names = "se"; 828 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 829 pinctrl-names = "default"; 830 pinctrl-0 = <&qup_spi8_default>; 831 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 832 #address-cells = <1>; 833 #size-cells = <0>; 834 status = "disabled"; 835 }; 836 837 uart8: serial@a88000 { 838 compatible = "qcom,geni-debug-uart"; 839 reg = <0 0x00a88000 0 0x4000>; 840 clock-names = "se"; 841 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 842 pinctrl-names = "default"; 843 pinctrl-0 = <&qup_uart8_default>; 844 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 845 status = "disabled"; 846 }; 847 848 i2c9: i2c@a8c000 { 849 compatible = "qcom,geni-i2c"; 850 reg = <0 0x00a8c000 0 0x4000>; 851 clock-names = "se"; 852 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 853 pinctrl-names = "default"; 854 pinctrl-0 = <&qup_i2c9_default>; 855 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 856 #address-cells = <1>; 857 #size-cells = <0>; 858 status = "disabled"; 859 }; 860 861 uart9: serial@a8c000 { 862 compatible = "qcom,geni-uart"; 863 reg = <0 0x00a8c000 0 0x4000>; 864 clock-names = "se"; 865 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 866 pinctrl-names = "default"; 867 pinctrl-0 = <&qup_uart9_default>; 868 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 869 status = "disabled"; 870 }; 871 872 i2c10: i2c@a90000 { 873 compatible = "qcom,geni-i2c"; 874 reg = <0 0x00a90000 0 0x4000>; 875 clock-names = "se"; 876 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 877 pinctrl-names = "default"; 878 pinctrl-0 = <&qup_i2c10_default>; 879 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 880 #address-cells = <1>; 881 #size-cells = <0>; 882 status = "disabled"; 883 }; 884 885 spi10: spi@a90000 { 886 compatible = "qcom,geni-spi"; 887 reg = <0 0x00a90000 0 0x4000>; 888 clock-names = "se"; 889 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 890 pinctrl-names = "default"; 891 pinctrl-0 = <&qup_spi10_default>; 892 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 893 #address-cells = <1>; 894 #size-cells = <0>; 895 status = "disabled"; 896 }; 897 898 uart10: serial@a90000 { 899 compatible = "qcom,geni-uart"; 900 reg = <0 0x00a90000 0 0x4000>; 901 clock-names = "se"; 902 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 903 pinctrl-names = "default"; 904 pinctrl-0 = <&qup_uart10_default>; 905 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 906 status = "disabled"; 907 }; 908 909 i2c11: i2c@a94000 { 910 compatible = "qcom,geni-i2c"; 911 reg = <0 0x00a94000 0 0x4000>; 912 clock-names = "se"; 913 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 914 pinctrl-names = "default"; 915 pinctrl-0 = <&qup_i2c11_default>; 916 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 917 #address-cells = <1>; 918 #size-cells = <0>; 919 status = "disabled"; 920 }; 921 922 spi11: spi@a94000 { 923 compatible = "qcom,geni-spi"; 924 reg = <0 0x00a94000 0 0x4000>; 925 clock-names = "se"; 926 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 927 pinctrl-names = "default"; 928 pinctrl-0 = <&qup_spi11_default>; 929 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 930 #address-cells = <1>; 931 #size-cells = <0>; 932 status = "disabled"; 933 }; 934 935 uart11: serial@a94000 { 936 compatible = "qcom,geni-uart"; 937 reg = <0 0x00a94000 0 0x4000>; 938 clock-names = "se"; 939 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 940 pinctrl-names = "default"; 941 pinctrl-0 = <&qup_uart11_default>; 942 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 943 status = "disabled"; 944 }; 945 }; 946 947 config_noc: interconnect@1500000 { 948 compatible = "qcom,sc7180-config-noc"; 949 reg = <0 0x01500000 0 0x28000>; 950 #interconnect-cells = <1>; 951 qcom,bcm-voters = <&apps_bcm_voter>; 952 }; 953 954 system_noc: interconnect@1620000 { 955 compatible = "qcom,sc7180-system-noc"; 956 reg = <0 0x01620000 0 0x17080>; 957 #interconnect-cells = <1>; 958 qcom,bcm-voters = <&apps_bcm_voter>; 959 }; 960 961 mc_virt: interconnect@1638000 { 962 compatible = "qcom,sc7180-mc-virt"; 963 reg = <0 0x01638000 0 0x1000>; 964 #interconnect-cells = <1>; 965 qcom,bcm-voters = <&apps_bcm_voter>; 966 }; 967 968 qup_virt: interconnect@1650000 { 969 compatible = "qcom,sc7180-qup-virt"; 970 reg = <0 0x01650000 0 0x1000>; 971 #interconnect-cells = <1>; 972 qcom,bcm-voters = <&apps_bcm_voter>; 973 }; 974 975 aggre1_noc: interconnect@16e0000 { 976 compatible = "qcom,sc7180-aggre1-noc"; 977 reg = <0 0x016e0000 0 0x15080>; 978 #interconnect-cells = <1>; 979 qcom,bcm-voters = <&apps_bcm_voter>; 980 }; 981 982 aggre2_noc: interconnect@1705000 { 983 compatible = "qcom,sc7180-aggre2-noc"; 984 reg = <0 0x01705000 0 0x9000>; 985 #interconnect-cells = <1>; 986 qcom,bcm-voters = <&apps_bcm_voter>; 987 }; 988 989 compute_noc: interconnect@170e000 { 990 compatible = "qcom,sc7180-compute-noc"; 991 reg = <0 0x0170e000 0 0x6000>; 992 #interconnect-cells = <1>; 993 qcom,bcm-voters = <&apps_bcm_voter>; 994 }; 995 996 mmss_noc: interconnect@1740000 { 997 compatible = "qcom,sc7180-mmss-noc"; 998 reg = <0 0x01740000 0 0x1c100>; 999 #interconnect-cells = <1>; 1000 qcom,bcm-voters = <&apps_bcm_voter>; 1001 }; 1002 1003 ipa_virt: interconnect@1e00000 { 1004 compatible = "qcom,sc7180-ipa-virt"; 1005 reg = <0 0x01e00000 0 0x1000>; 1006 #interconnect-cells = <1>; 1007 qcom,bcm-voters = <&apps_bcm_voter>; 1008 }; 1009 1010 tcsr_mutex_regs: syscon@1f40000 { 1011 compatible = "syscon"; 1012 reg = <0 0x01f40000 0 0x40000>; 1013 }; 1014 1015 tcsr_regs: syscon@1fc0000 { 1016 compatible = "syscon"; 1017 reg = <0 0x01fc0000 0 0x40000>; 1018 }; 1019 1020 tlmm: pinctrl@3500000 { 1021 compatible = "qcom,sc7180-pinctrl"; 1022 reg = <0 0x03500000 0 0x300000>, 1023 <0 0x03900000 0 0x300000>, 1024 <0 0x03d00000 0 0x300000>; 1025 reg-names = "west", "north", "south"; 1026 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 1027 gpio-controller; 1028 #gpio-cells = <2>; 1029 interrupt-controller; 1030 #interrupt-cells = <2>; 1031 gpio-ranges = <&tlmm 0 0 120>; 1032 wakeup-parent = <&pdc>; 1033 1034 qspi_clk: qspi-clk { 1035 pinmux { 1036 pins = "gpio63"; 1037 function = "qspi_clk"; 1038 }; 1039 }; 1040 1041 qspi_cs0: qspi-cs0 { 1042 pinmux { 1043 pins = "gpio68"; 1044 function = "qspi_cs"; 1045 }; 1046 }; 1047 1048 qspi_cs1: qspi-cs1 { 1049 pinmux { 1050 pins = "gpio72"; 1051 function = "qspi_cs"; 1052 }; 1053 }; 1054 1055 qspi_data01: qspi-data01 { 1056 pinmux-data { 1057 pins = "gpio64", "gpio65"; 1058 function = "qspi_data"; 1059 }; 1060 }; 1061 1062 qspi_data12: qspi-data12 { 1063 pinmux-data { 1064 pins = "gpio66", "gpio67"; 1065 function = "qspi_data"; 1066 }; 1067 }; 1068 1069 qup_i2c0_default: qup-i2c0-default { 1070 pinmux { 1071 pins = "gpio34", "gpio35"; 1072 function = "qup00"; 1073 }; 1074 }; 1075 1076 qup_i2c1_default: qup-i2c1-default { 1077 pinmux { 1078 pins = "gpio0", "gpio1"; 1079 function = "qup01"; 1080 }; 1081 }; 1082 1083 qup_i2c2_default: qup-i2c2-default { 1084 pinmux { 1085 pins = "gpio15", "gpio16"; 1086 function = "qup02_i2c"; 1087 }; 1088 }; 1089 1090 qup_i2c3_default: qup-i2c3-default { 1091 pinmux { 1092 pins = "gpio38", "gpio39"; 1093 function = "qup03"; 1094 }; 1095 }; 1096 1097 qup_i2c4_default: qup-i2c4-default { 1098 pinmux { 1099 pins = "gpio115", "gpio116"; 1100 function = "qup04_i2c"; 1101 }; 1102 }; 1103 1104 qup_i2c5_default: qup-i2c5-default { 1105 pinmux { 1106 pins = "gpio25", "gpio26"; 1107 function = "qup05"; 1108 }; 1109 }; 1110 1111 qup_i2c6_default: qup-i2c6-default { 1112 pinmux { 1113 pins = "gpio59", "gpio60"; 1114 function = "qup10"; 1115 }; 1116 }; 1117 1118 qup_i2c7_default: qup-i2c7-default { 1119 pinmux { 1120 pins = "gpio6", "gpio7"; 1121 function = "qup11_i2c"; 1122 }; 1123 }; 1124 1125 qup_i2c8_default: qup-i2c8-default { 1126 pinmux { 1127 pins = "gpio42", "gpio43"; 1128 function = "qup12"; 1129 }; 1130 }; 1131 1132 qup_i2c9_default: qup-i2c9-default { 1133 pinmux { 1134 pins = "gpio46", "gpio47"; 1135 function = "qup13_i2c"; 1136 }; 1137 }; 1138 1139 qup_i2c10_default: qup-i2c10-default { 1140 pinmux { 1141 pins = "gpio86", "gpio87"; 1142 function = "qup14"; 1143 }; 1144 }; 1145 1146 qup_i2c11_default: qup-i2c11-default { 1147 pinmux { 1148 pins = "gpio53", "gpio54"; 1149 function = "qup15"; 1150 }; 1151 }; 1152 1153 qup_spi0_default: qup-spi0-default { 1154 pinmux { 1155 pins = "gpio34", "gpio35", 1156 "gpio36", "gpio37"; 1157 function = "qup00"; 1158 }; 1159 }; 1160 1161 qup_spi1_default: qup-spi1-default { 1162 pinmux { 1163 pins = "gpio0", "gpio1", 1164 "gpio2", "gpio3"; 1165 function = "qup01"; 1166 }; 1167 }; 1168 1169 qup_spi3_default: qup-spi3-default { 1170 pinmux { 1171 pins = "gpio38", "gpio39", 1172 "gpio40", "gpio41"; 1173 function = "qup03"; 1174 }; 1175 }; 1176 1177 qup_spi5_default: qup-spi5-default { 1178 pinmux { 1179 pins = "gpio25", "gpio26", 1180 "gpio27", "gpio28"; 1181 function = "qup05"; 1182 }; 1183 }; 1184 1185 qup_spi6_default: qup-spi6-default { 1186 pinmux { 1187 pins = "gpio59", "gpio60", 1188 "gpio61", "gpio62"; 1189 function = "qup10"; 1190 }; 1191 }; 1192 1193 qup_spi8_default: qup-spi8-default { 1194 pinmux { 1195 pins = "gpio42", "gpio43", 1196 "gpio44", "gpio45"; 1197 function = "qup12"; 1198 }; 1199 }; 1200 1201 qup_spi10_default: qup-spi10-default { 1202 pinmux { 1203 pins = "gpio86", "gpio87", 1204 "gpio88", "gpio89"; 1205 function = "qup14"; 1206 }; 1207 }; 1208 1209 qup_spi11_default: qup-spi11-default { 1210 pinmux { 1211 pins = "gpio53", "gpio54", 1212 "gpio55", "gpio56"; 1213 function = "qup15"; 1214 }; 1215 }; 1216 1217 qup_uart0_default: qup-uart0-default { 1218 pinmux { 1219 pins = "gpio34", "gpio35", 1220 "gpio36", "gpio37"; 1221 function = "qup00"; 1222 }; 1223 }; 1224 1225 qup_uart1_default: qup-uart1-default { 1226 pinmux { 1227 pins = "gpio0", "gpio1", 1228 "gpio2", "gpio3"; 1229 function = "qup01"; 1230 }; 1231 }; 1232 1233 qup_uart2_default: qup-uart2-default { 1234 pinmux { 1235 pins = "gpio15", "gpio16"; 1236 function = "qup02_uart"; 1237 }; 1238 }; 1239 1240 qup_uart3_default: qup-uart3-default { 1241 pinmux { 1242 pins = "gpio38", "gpio39", 1243 "gpio40", "gpio41"; 1244 function = "qup03"; 1245 }; 1246 }; 1247 1248 qup_uart4_default: qup-uart4-default { 1249 pinmux { 1250 pins = "gpio115", "gpio116"; 1251 function = "qup04_uart"; 1252 }; 1253 }; 1254 1255 qup_uart5_default: qup-uart5-default { 1256 pinmux { 1257 pins = "gpio25", "gpio26", 1258 "gpio27", "gpio28"; 1259 function = "qup05"; 1260 }; 1261 }; 1262 1263 qup_uart6_default: qup-uart6-default { 1264 pinmux { 1265 pins = "gpio59", "gpio60", 1266 "gpio61", "gpio62"; 1267 function = "qup10"; 1268 }; 1269 }; 1270 1271 qup_uart7_default: qup-uart7-default { 1272 pinmux { 1273 pins = "gpio6", "gpio7"; 1274 function = "qup11_uart"; 1275 }; 1276 }; 1277 1278 qup_uart8_default: qup-uart8-default { 1279 pinmux { 1280 pins = "gpio44", "gpio45"; 1281 function = "qup12"; 1282 }; 1283 }; 1284 1285 qup_uart9_default: qup-uart9-default { 1286 pinmux { 1287 pins = "gpio46", "gpio47"; 1288 function = "qup13_uart"; 1289 }; 1290 }; 1291 1292 qup_uart10_default: qup-uart10-default { 1293 pinmux { 1294 pins = "gpio86", "gpio87", 1295 "gpio88", "gpio89"; 1296 function = "qup14"; 1297 }; 1298 }; 1299 1300 qup_uart11_default: qup-uart11-default { 1301 pinmux { 1302 pins = "gpio53", "gpio54", 1303 "gpio55", "gpio56"; 1304 function = "qup15"; 1305 }; 1306 }; 1307 1308 sdc1_on: sdc1-on { 1309 pinconf-clk { 1310 pins = "sdc1_clk"; 1311 bias-disable; 1312 drive-strength = <16>; 1313 }; 1314 1315 pinconf-cmd { 1316 pins = "sdc1_cmd"; 1317 bias-pull-up; 1318 drive-strength = <10>; 1319 }; 1320 1321 pinconf-data { 1322 pins = "sdc1_data"; 1323 bias-pull-up; 1324 drive-strength = <10>; 1325 }; 1326 1327 pinconf-rclk { 1328 pins = "sdc1_rclk"; 1329 bias-pull-down; 1330 }; 1331 }; 1332 1333 sdc1_off: sdc1-off { 1334 pinconf-clk { 1335 pins = "sdc1_clk"; 1336 bias-disable; 1337 drive-strength = <2>; 1338 }; 1339 1340 pinconf-cmd { 1341 pins = "sdc1_cmd"; 1342 bias-pull-up; 1343 drive-strength = <2>; 1344 }; 1345 1346 pinconf-data { 1347 pins = "sdc1_data"; 1348 bias-pull-up; 1349 drive-strength = <2>; 1350 }; 1351 1352 pinconf-rclk { 1353 pins = "sdc1_rclk"; 1354 bias-pull-down; 1355 }; 1356 }; 1357 1358 sdc2_on: sdc2-on { 1359 pinconf-clk { 1360 pins = "sdc2_clk"; 1361 bias-disable; 1362 drive-strength = <16>; 1363 }; 1364 1365 pinconf-cmd { 1366 pins = "sdc2_cmd"; 1367 bias-pull-up; 1368 drive-strength = <10>; 1369 }; 1370 1371 pinconf-data { 1372 pins = "sdc2_data"; 1373 bias-pull-up; 1374 drive-strength = <10>; 1375 }; 1376 1377 pinconf-sd-cd { 1378 pins = "gpio69"; 1379 bias-pull-up; 1380 drive-strength = <2>; 1381 }; 1382 }; 1383 1384 sdc2_off: sdc2-off { 1385 pinconf-clk { 1386 pins = "sdc2_clk"; 1387 bias-disable; 1388 drive-strength = <2>; 1389 }; 1390 1391 pinconf-cmd { 1392 pins = "sdc2_cmd"; 1393 bias-pull-up; 1394 drive-strength = <2>; 1395 }; 1396 1397 pinconf-data { 1398 pins = "sdc2_data"; 1399 bias-pull-up; 1400 drive-strength = <2>; 1401 }; 1402 1403 pinconf-sd-cd { 1404 pins = "gpio69"; 1405 bias-disable; 1406 drive-strength = <2>; 1407 }; 1408 }; 1409 }; 1410 1411 gpu: gpu@5000000 { 1412 compatible = "qcom,adreno-618.0", "qcom,adreno"; 1413 #stream-id-cells = <16>; 1414 reg = <0 0x05000000 0 0x40000>, <0 0x0509e000 0 0x1000>, 1415 <0 0x05061000 0 0x800>; 1416 reg-names = "kgsl_3d0_reg_memory", "cx_mem", "cx_dbgc"; 1417 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 1418 iommus = <&adreno_smmu 0>; 1419 operating-points-v2 = <&gpu_opp_table>; 1420 qcom,gmu = <&gmu>; 1421 1422 gpu_opp_table: opp-table { 1423 compatible = "operating-points-v2"; 1424 1425 opp-800000000 { 1426 opp-hz = /bits/ 64 <800000000>; 1427 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 1428 }; 1429 1430 opp-650000000 { 1431 opp-hz = /bits/ 64 <650000000>; 1432 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 1433 }; 1434 1435 opp-565000000 { 1436 opp-hz = /bits/ 64 <565000000>; 1437 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 1438 }; 1439 1440 opp-430000000 { 1441 opp-hz = /bits/ 64 <430000000>; 1442 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 1443 }; 1444 1445 opp-355000000 { 1446 opp-hz = /bits/ 64 <355000000>; 1447 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 1448 }; 1449 1450 opp-267000000 { 1451 opp-hz = /bits/ 64 <267000000>; 1452 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 1453 }; 1454 1455 opp-180000000 { 1456 opp-hz = /bits/ 64 <180000000>; 1457 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 1458 }; 1459 }; 1460 }; 1461 1462 adreno_smmu: iommu@5040000 { 1463 compatible = "qcom,sc7180-smmu-v2", "qcom,smmu-v2"; 1464 reg = <0 0x05040000 0 0x10000>; 1465 #iommu-cells = <1>; 1466 #global-interrupts = <2>; 1467 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 1468 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 1469 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>, 1470 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>, 1471 <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>, 1472 <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>, 1473 <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>, 1474 <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>, 1475 <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>, 1476 <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>; 1477 1478 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 1479 <&gcc GCC_GPU_CFG_AHB_CLK>; 1480 clock-names = "bus", "iface"; 1481 1482 power-domains = <&gpucc CX_GDSC>; 1483 }; 1484 1485 gmu: gmu@506a000 { 1486 compatible="qcom,adreno-gmu-618.0", "qcom,adreno-gmu"; 1487 reg = <0 0x0506a000 0 0x31000>, <0 0x0b290000 0 0x10000>, 1488 <0 0x0b490000 0 0x10000>; 1489 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq"; 1490 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 1491 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 1492 interrupt-names = "hfi", "gmu"; 1493 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 1494 <&gpucc GPU_CC_CXO_CLK>, 1495 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 1496 <&gcc GCC_GPU_MEMNOC_GFX_CLK>; 1497 clock-names = "gmu", "cxo", "axi", "memnoc"; 1498 power-domains = <&gpucc CX_GDSC>, <&gpucc GX_GDSC>; 1499 power-domain-names = "cx", "gx"; 1500 iommus = <&adreno_smmu 5>; 1501 operating-points-v2 = <&gmu_opp_table>; 1502 1503 gmu_opp_table: opp-table { 1504 compatible = "operating-points-v2"; 1505 1506 opp-200000000 { 1507 opp-hz = /bits/ 64 <200000000>; 1508 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 1509 }; 1510 }; 1511 }; 1512 1513 gpucc: clock-controller@5090000 { 1514 compatible = "qcom,sc7180-gpucc"; 1515 reg = <0 0x05090000 0 0x9000>; 1516 clocks = <&rpmhcc RPMH_CXO_CLK>, 1517 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 1518 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 1519 clock-names = "bi_tcxo", 1520 "gcc_gpu_gpll0_clk_src", 1521 "gcc_gpu_gpll0_div_clk_src"; 1522 #clock-cells = <1>; 1523 #reset-cells = <1>; 1524 #power-domain-cells = <1>; 1525 }; 1526 1527 stm@6002000 { 1528 compatible = "arm,coresight-stm", "arm,primecell"; 1529 reg = <0 0x06002000 0 0x1000>, 1530 <0 0x16280000 0 0x180000>; 1531 reg-names = "stm-base", "stm-stimulus-base"; 1532 1533 clocks = <&aoss_qmp>; 1534 clock-names = "apb_pclk"; 1535 1536 out-ports { 1537 port { 1538 stm_out: endpoint { 1539 remote-endpoint = <&funnel0_in7>; 1540 }; 1541 }; 1542 }; 1543 }; 1544 1545 funnel@6041000 { 1546 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1547 reg = <0 0x06041000 0 0x1000>; 1548 1549 clocks = <&aoss_qmp>; 1550 clock-names = "apb_pclk"; 1551 1552 out-ports { 1553 port { 1554 funnel0_out: endpoint { 1555 remote-endpoint = <&merge_funnel_in0>; 1556 }; 1557 }; 1558 }; 1559 1560 in-ports { 1561 #address-cells = <1>; 1562 #size-cells = <0>; 1563 1564 port@7 { 1565 reg = <7>; 1566 funnel0_in7: endpoint { 1567 remote-endpoint = <&stm_out>; 1568 }; 1569 }; 1570 }; 1571 }; 1572 1573 funnel@6042000 { 1574 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1575 reg = <0 0x06042000 0 0x1000>; 1576 1577 clocks = <&aoss_qmp>; 1578 clock-names = "apb_pclk"; 1579 1580 out-ports { 1581 port { 1582 funnel1_out: endpoint { 1583 remote-endpoint = <&merge_funnel_in1>; 1584 }; 1585 }; 1586 }; 1587 1588 in-ports { 1589 #address-cells = <1>; 1590 #size-cells = <0>; 1591 1592 port@4 { 1593 reg = <4>; 1594 funnel1_in4: endpoint { 1595 remote-endpoint = <&apss_merge_funnel_out>; 1596 }; 1597 }; 1598 }; 1599 }; 1600 1601 funnel@6045000 { 1602 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1603 reg = <0 0x06045000 0 0x1000>; 1604 1605 clocks = <&aoss_qmp>; 1606 clock-names = "apb_pclk"; 1607 1608 out-ports { 1609 port { 1610 merge_funnel_out: endpoint { 1611 remote-endpoint = <&swao_funnel_in>; 1612 }; 1613 }; 1614 }; 1615 1616 in-ports { 1617 #address-cells = <1>; 1618 #size-cells = <0>; 1619 1620 port@0 { 1621 reg = <0>; 1622 merge_funnel_in0: endpoint { 1623 remote-endpoint = <&funnel0_out>; 1624 }; 1625 }; 1626 1627 port@1 { 1628 reg = <1>; 1629 merge_funnel_in1: endpoint { 1630 remote-endpoint = <&funnel1_out>; 1631 }; 1632 }; 1633 }; 1634 }; 1635 1636 replicator@6046000 { 1637 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 1638 reg = <0 0x06046000 0 0x1000>; 1639 1640 clocks = <&aoss_qmp>; 1641 clock-names = "apb_pclk"; 1642 1643 out-ports { 1644 port { 1645 replicator_out: endpoint { 1646 remote-endpoint = <&etr_in>; 1647 }; 1648 }; 1649 }; 1650 1651 in-ports { 1652 port { 1653 replicator_in: endpoint { 1654 remote-endpoint = <&swao_replicator_out>; 1655 }; 1656 }; 1657 }; 1658 }; 1659 1660 etr@6048000 { 1661 compatible = "arm,coresight-tmc", "arm,primecell"; 1662 reg = <0 0x06048000 0 0x1000>; 1663 1664 clocks = <&aoss_qmp>; 1665 clock-names = "apb_pclk"; 1666 arm,scatter-gather; 1667 1668 in-ports { 1669 port { 1670 etr_in: endpoint { 1671 remote-endpoint = <&replicator_out>; 1672 }; 1673 }; 1674 }; 1675 }; 1676 1677 funnel@6b04000 { 1678 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1679 reg = <0 0x06b04000 0 0x1000>; 1680 1681 clocks = <&aoss_qmp>; 1682 clock-names = "apb_pclk"; 1683 1684 out-ports { 1685 port { 1686 swao_funnel_out: endpoint { 1687 remote-endpoint = <&etf_in>; 1688 }; 1689 }; 1690 }; 1691 1692 in-ports { 1693 #address-cells = <1>; 1694 #size-cells = <0>; 1695 1696 port@7 { 1697 reg = <7>; 1698 swao_funnel_in: endpoint { 1699 remote-endpoint = <&merge_funnel_out>; 1700 }; 1701 }; 1702 }; 1703 }; 1704 1705 etf@6b05000 { 1706 compatible = "arm,coresight-tmc", "arm,primecell"; 1707 reg = <0 0x06b05000 0 0x1000>; 1708 1709 clocks = <&aoss_qmp>; 1710 clock-names = "apb_pclk"; 1711 1712 out-ports { 1713 port { 1714 etf_out: endpoint { 1715 remote-endpoint = <&swao_replicator_in>; 1716 }; 1717 }; 1718 }; 1719 1720 in-ports { 1721 port { 1722 etf_in: endpoint { 1723 remote-endpoint = <&swao_funnel_out>; 1724 }; 1725 }; 1726 }; 1727 }; 1728 1729 replicator@6b06000 { 1730 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 1731 reg = <0 0x06b06000 0 0x1000>; 1732 1733 clocks = <&aoss_qmp>; 1734 clock-names = "apb_pclk"; 1735 arm,coresight-loses-context-with-cpu; 1736 1737 out-ports { 1738 port { 1739 swao_replicator_out: endpoint { 1740 remote-endpoint = <&replicator_in>; 1741 }; 1742 }; 1743 }; 1744 1745 in-ports { 1746 port { 1747 swao_replicator_in: endpoint { 1748 remote-endpoint = <&etf_out>; 1749 }; 1750 }; 1751 }; 1752 }; 1753 1754 etm@7040000 { 1755 compatible = "arm,coresight-etm4x", "arm,primecell"; 1756 reg = <0 0x07040000 0 0x1000>; 1757 1758 cpu = <&CPU0>; 1759 1760 clocks = <&aoss_qmp>; 1761 clock-names = "apb_pclk"; 1762 arm,coresight-loses-context-with-cpu; 1763 1764 out-ports { 1765 port { 1766 etm0_out: endpoint { 1767 remote-endpoint = <&apss_funnel_in0>; 1768 }; 1769 }; 1770 }; 1771 }; 1772 1773 etm@7140000 { 1774 compatible = "arm,coresight-etm4x", "arm,primecell"; 1775 reg = <0 0x07140000 0 0x1000>; 1776 1777 cpu = <&CPU1>; 1778 1779 clocks = <&aoss_qmp>; 1780 clock-names = "apb_pclk"; 1781 arm,coresight-loses-context-with-cpu; 1782 1783 out-ports { 1784 port { 1785 etm1_out: endpoint { 1786 remote-endpoint = <&apss_funnel_in1>; 1787 }; 1788 }; 1789 }; 1790 }; 1791 1792 etm@7240000 { 1793 compatible = "arm,coresight-etm4x", "arm,primecell"; 1794 reg = <0 0x07240000 0 0x1000>; 1795 1796 cpu = <&CPU2>; 1797 1798 clocks = <&aoss_qmp>; 1799 clock-names = "apb_pclk"; 1800 arm,coresight-loses-context-with-cpu; 1801 1802 out-ports { 1803 port { 1804 etm2_out: endpoint { 1805 remote-endpoint = <&apss_funnel_in2>; 1806 }; 1807 }; 1808 }; 1809 }; 1810 1811 etm@7340000 { 1812 compatible = "arm,coresight-etm4x", "arm,primecell"; 1813 reg = <0 0x07340000 0 0x1000>; 1814 1815 cpu = <&CPU3>; 1816 1817 clocks = <&aoss_qmp>; 1818 clock-names = "apb_pclk"; 1819 arm,coresight-loses-context-with-cpu; 1820 1821 out-ports { 1822 port { 1823 etm3_out: endpoint { 1824 remote-endpoint = <&apss_funnel_in3>; 1825 }; 1826 }; 1827 }; 1828 }; 1829 1830 etm@7440000 { 1831 compatible = "arm,coresight-etm4x", "arm,primecell"; 1832 reg = <0 0x07440000 0 0x1000>; 1833 1834 cpu = <&CPU4>; 1835 1836 clocks = <&aoss_qmp>; 1837 clock-names = "apb_pclk"; 1838 arm,coresight-loses-context-with-cpu; 1839 1840 out-ports { 1841 port { 1842 etm4_out: endpoint { 1843 remote-endpoint = <&apss_funnel_in4>; 1844 }; 1845 }; 1846 }; 1847 }; 1848 1849 etm@7540000 { 1850 compatible = "arm,coresight-etm4x", "arm,primecell"; 1851 reg = <0 0x07540000 0 0x1000>; 1852 1853 cpu = <&CPU5>; 1854 1855 clocks = <&aoss_qmp>; 1856 clock-names = "apb_pclk"; 1857 arm,coresight-loses-context-with-cpu; 1858 1859 out-ports { 1860 port { 1861 etm5_out: endpoint { 1862 remote-endpoint = <&apss_funnel_in5>; 1863 }; 1864 }; 1865 }; 1866 }; 1867 1868 etm@7640000 { 1869 compatible = "arm,coresight-etm4x", "arm,primecell"; 1870 reg = <0 0x07640000 0 0x1000>; 1871 1872 cpu = <&CPU6>; 1873 1874 clocks = <&aoss_qmp>; 1875 clock-names = "apb_pclk"; 1876 arm,coresight-loses-context-with-cpu; 1877 1878 out-ports { 1879 port { 1880 etm6_out: endpoint { 1881 remote-endpoint = <&apss_funnel_in6>; 1882 }; 1883 }; 1884 }; 1885 }; 1886 1887 etm@7740000 { 1888 compatible = "arm,coresight-etm4x", "arm,primecell"; 1889 reg = <0 0x07740000 0 0x1000>; 1890 1891 cpu = <&CPU7>; 1892 1893 clocks = <&aoss_qmp>; 1894 clock-names = "apb_pclk"; 1895 1896 out-ports { 1897 port { 1898 etm7_out: endpoint { 1899 remote-endpoint = <&apss_funnel_in7>; 1900 }; 1901 }; 1902 }; 1903 }; 1904 1905 funnel@7800000 { /* APSS Funnel */ 1906 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1907 reg = <0 0x07800000 0 0x1000>; 1908 1909 clocks = <&aoss_qmp>; 1910 clock-names = "apb_pclk"; 1911 1912 out-ports { 1913 port { 1914 apss_funnel_out: endpoint { 1915 remote-endpoint = <&apss_merge_funnel_in>; 1916 }; 1917 }; 1918 }; 1919 1920 in-ports { 1921 #address-cells = <1>; 1922 #size-cells = <0>; 1923 1924 port@0 { 1925 reg = <0>; 1926 apss_funnel_in0: endpoint { 1927 remote-endpoint = <&etm0_out>; 1928 }; 1929 }; 1930 1931 port@1 { 1932 reg = <1>; 1933 apss_funnel_in1: endpoint { 1934 remote-endpoint = <&etm1_out>; 1935 }; 1936 }; 1937 1938 port@2 { 1939 reg = <2>; 1940 apss_funnel_in2: endpoint { 1941 remote-endpoint = <&etm2_out>; 1942 }; 1943 }; 1944 1945 port@3 { 1946 reg = <3>; 1947 apss_funnel_in3: endpoint { 1948 remote-endpoint = <&etm3_out>; 1949 }; 1950 }; 1951 1952 port@4 { 1953 reg = <4>; 1954 apss_funnel_in4: endpoint { 1955 remote-endpoint = <&etm4_out>; 1956 }; 1957 }; 1958 1959 port@5 { 1960 reg = <5>; 1961 apss_funnel_in5: endpoint { 1962 remote-endpoint = <&etm5_out>; 1963 }; 1964 }; 1965 1966 port@6 { 1967 reg = <6>; 1968 apss_funnel_in6: endpoint { 1969 remote-endpoint = <&etm6_out>; 1970 }; 1971 }; 1972 1973 port@7 { 1974 reg = <7>; 1975 apss_funnel_in7: endpoint { 1976 remote-endpoint = <&etm7_out>; 1977 }; 1978 }; 1979 }; 1980 }; 1981 1982 funnel@7810000 { 1983 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1984 reg = <0 0x07810000 0 0x1000>; 1985 1986 clocks = <&aoss_qmp>; 1987 clock-names = "apb_pclk"; 1988 1989 out-ports { 1990 port { 1991 apss_merge_funnel_out: endpoint { 1992 remote-endpoint = <&funnel1_in4>; 1993 }; 1994 }; 1995 }; 1996 1997 in-ports { 1998 port { 1999 apss_merge_funnel_in: endpoint { 2000 remote-endpoint = <&apss_funnel_out>; 2001 }; 2002 }; 2003 }; 2004 }; 2005 2006 remoteproc_mpss: remoteproc@4080000 { 2007 compatible = "qcom,sc7180-mpss-pas"; 2008 reg = <0 0x04080000 0 0x4040>, <0 0x04180000 0 0x48>; 2009 reg-names = "qdsp6", "rmb"; 2010 2011 interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>, 2012 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2013 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2014 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2015 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 2016 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 2017 interrupt-names = "wdog", "fatal", "ready", "handover", 2018 "stop-ack", "shutdown-ack"; 2019 2020 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, 2021 <&gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>, 2022 <&gcc GCC_MSS_NAV_AXI_CLK>, 2023 <&gcc GCC_MSS_SNOC_AXI_CLK>, 2024 <&gcc GCC_MSS_MFAB_AXIS_CLK>, 2025 <&rpmhcc RPMH_CXO_CLK>; 2026 clock-names = "iface", "bus", "nav", "snoc_axi", 2027 "mnoc_axi", "xo"; 2028 2029 power-domains = <&aoss_qmp AOSS_QMP_LS_MODEM>, 2030 <&rpmhpd SC7180_CX>, 2031 <&rpmhpd SC7180_MX>, 2032 <&rpmhpd SC7180_MSS>; 2033 power-domain-names = "load_state", "cx", "mx", "mss"; 2034 2035 memory-region = <&mpss_mem>; 2036 2037 qcom,smem-states = <&modem_smp2p_out 0>; 2038 qcom,smem-state-names = "stop"; 2039 2040 resets = <&aoss_reset AOSS_CC_MSS_RESTART>, 2041 <&pdc_reset PDC_MODEM_SYNC_RESET>; 2042 reset-names = "mss_restart", "pdc_reset"; 2043 2044 qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>; 2045 qcom,spare-regs = <&tcsr_regs 0xb3e4>; 2046 2047 status = "disabled"; 2048 2049 glink-edge { 2050 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; 2051 label = "modem"; 2052 qcom,remote-pid = <1>; 2053 mboxes = <&apss_shared 12>; 2054 }; 2055 }; 2056 2057 sdhc_2: sdhci@8804000 { 2058 compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5"; 2059 reg = <0 0x08804000 0 0x1000>; 2060 2061 iommus = <&apps_smmu 0x80 0>; 2062 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 2063 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 2064 interrupt-names = "hc_irq", "pwr_irq"; 2065 2066 clocks = <&gcc GCC_SDCC2_APPS_CLK>, 2067 <&gcc GCC_SDCC2_AHB_CLK>; 2068 clock-names = "core", "iface"; 2069 2070 bus-width = <4>; 2071 2072 status = "disabled"; 2073 }; 2074 2075 qspi: spi@88dc000 { 2076 compatible = "qcom,qspi-v1"; 2077 reg = <0 0x088dc000 0 0x600>; 2078 #address-cells = <1>; 2079 #size-cells = <0>; 2080 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 2081 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, 2082 <&gcc GCC_QSPI_CORE_CLK>; 2083 clock-names = "iface", "core"; 2084 status = "disabled"; 2085 }; 2086 2087 usb_1_hsphy: phy@88e3000 { 2088 compatible = "qcom,sc7180-qusb2-phy", "qcom,qusb2-v2-phy"; 2089 reg = <0 0x088e3000 0 0x400>; 2090 status = "disabled"; 2091 #phy-cells = <0>; 2092 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 2093 <&rpmhcc RPMH_CXO_CLK>; 2094 clock-names = "cfg_ahb", "ref"; 2095 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2096 2097 nvmem-cells = <&qusb2p_hstx_trim>; 2098 }; 2099 2100 usb_1_qmpphy: phy-wrapper@88e9000 { 2101 compatible = "qcom,sc7180-qmp-usb3-phy"; 2102 reg = <0 0x088e9000 0 0x18c>, 2103 <0 0x088e8000 0 0x38>; 2104 reg-names = "reg-base", "dp_com"; 2105 status = "disabled"; 2106 #clock-cells = <1>; 2107 #address-cells = <2>; 2108 #size-cells = <2>; 2109 ranges; 2110 2111 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2112 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 2113 <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 2114 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 2115 clock-names = "aux", "cfg_ahb", "ref", "com_aux"; 2116 2117 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 2118 <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; 2119 reset-names = "phy", "common"; 2120 2121 usb_1_ssphy: phy@88e9200 { 2122 reg = <0 0x088e9200 0 0x128>, 2123 <0 0x088e9400 0 0x200>, 2124 <0 0x088e9c00 0 0x218>, 2125 <0 0x088e9600 0 0x128>, 2126 <0 0x088e9800 0 0x200>, 2127 <0 0x088e9a00 0 0x18>; 2128 #clock-cells = <0>; 2129 #phy-cells = <0>; 2130 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2131 clock-names = "pipe0"; 2132 clock-output-names = "usb3_phy_pipe_clk_src"; 2133 }; 2134 }; 2135 2136 dc_noc: interconnect@9160000 { 2137 compatible = "qcom,sc7180-dc-noc"; 2138 reg = <0 0x09160000 0 0x03200>; 2139 #interconnect-cells = <1>; 2140 qcom,bcm-voters = <&apps_bcm_voter>; 2141 }; 2142 2143 system-cache-controller@9200000 { 2144 compatible = "qcom,sc7180-llcc"; 2145 reg = <0 0x09200000 0 0x200000>, <0 0x09600000 0 0x50000>; 2146 reg-names = "llcc_base", "llcc_broadcast_base"; 2147 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 2148 }; 2149 2150 gem_noc: interconnect@9680000 { 2151 compatible = "qcom,sc7180-gem-noc"; 2152 reg = <0 0x09680000 0 0x3e200>; 2153 #interconnect-cells = <1>; 2154 qcom,bcm-voters = <&apps_bcm_voter>; 2155 }; 2156 2157 npu_noc: interconnect@9990000 { 2158 compatible = "qcom,sc7180-npu-noc"; 2159 reg = <0 0x09990000 0 0x1600>; 2160 #interconnect-cells = <1>; 2161 qcom,bcm-voters = <&apps_bcm_voter>; 2162 }; 2163 2164 usb_1: usb@a6f8800 { 2165 compatible = "qcom,sc7180-dwc3", "qcom,dwc3"; 2166 reg = <0 0x0a6f8800 0 0x400>; 2167 status = "disabled"; 2168 #address-cells = <2>; 2169 #size-cells = <2>; 2170 ranges; 2171 dma-ranges; 2172 2173 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 2174 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 2175 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 2176 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2177 <&gcc GCC_USB30_PRIM_SLEEP_CLK>; 2178 clock-names = "cfg_noc", "core", "iface", "mock_utmi", 2179 "sleep"; 2180 2181 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2182 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 2183 assigned-clock-rates = <19200000>, <150000000>; 2184 2185 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 2186 <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>, 2187 <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>, 2188 <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>; 2189 interrupt-names = "hs_phy_irq", "ss_phy_irq", 2190 "dm_hs_phy_irq", "dp_hs_phy_irq"; 2191 2192 power-domains = <&gcc USB30_PRIM_GDSC>; 2193 2194 resets = <&gcc GCC_USB30_PRIM_BCR>; 2195 2196 usb_1_dwc3: dwc3@a600000 { 2197 compatible = "snps,dwc3"; 2198 reg = <0 0x0a600000 0 0xe000>; 2199 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 2200 iommus = <&apps_smmu 0x540 0>; 2201 snps,dis_u2_susphy_quirk; 2202 snps,dis_enblslpm_quirk; 2203 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 2204 phy-names = "usb2-phy", "usb3-phy"; 2205 }; 2206 }; 2207 2208 venus: video-codec@aa00000 { 2209 compatible = "qcom,sc7180-venus"; 2210 reg = <0 0x0aa00000 0 0xff000>; 2211 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 2212 power-domains = <&videocc VENUS_GDSC>, 2213 <&videocc VCODEC0_GDSC>; 2214 power-domain-names = "venus", "vcodec0"; 2215 clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>, 2216 <&videocc VIDEO_CC_VENUS_AHB_CLK>, 2217 <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>, 2218 <&videocc VIDEO_CC_VCODEC0_CORE_CLK>, 2219 <&videocc VIDEO_CC_VCODEC0_AXI_CLK>; 2220 clock-names = "core", "iface", "bus", 2221 "vcodec0_core", "vcodec0_bus"; 2222 iommus = <&apps_smmu 0x0c00 0x60>; 2223 memory-region = <&venus_mem>; 2224 interconnects = <&mmss_noc MASTER_VIDEO_P0 &mc_virt SLAVE_EBI1>, 2225 <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_VENUS_CFG>; 2226 interconnect-names = "video-mem", "cpu-cfg"; 2227 2228 video-decoder { 2229 compatible = "venus-decoder"; 2230 }; 2231 2232 video-encoder { 2233 compatible = "venus-encoder"; 2234 }; 2235 }; 2236 2237 videocc: clock-controller@ab00000 { 2238 compatible = "qcom,sc7180-videocc"; 2239 reg = <0 0x0ab00000 0 0x10000>; 2240 clocks = <&rpmhcc RPMH_CXO_CLK>; 2241 clock-names = "bi_tcxo"; 2242 #clock-cells = <1>; 2243 #reset-cells = <1>; 2244 #power-domain-cells = <1>; 2245 }; 2246 2247 camnoc_virt: interconnect@ac00000 { 2248 compatible = "qcom,sc7180-camnoc-virt"; 2249 reg = <0 0x0ac00000 0 0x1000>; 2250 #interconnect-cells = <1>; 2251 qcom,bcm-voters = <&apps_bcm_voter>; 2252 }; 2253 2254 mdss: mdss@ae00000 { 2255 compatible = "qcom,sc7180-mdss"; 2256 reg = <0 0x0ae00000 0 0x1000>; 2257 reg-names = "mdss"; 2258 2259 power-domains = <&dispcc MDSS_GDSC>; 2260 2261 clocks = <&gcc GCC_DISP_AHB_CLK>, 2262 <&gcc GCC_DISP_HF_AXI_CLK>, 2263 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2264 <&dispcc DISP_CC_MDSS_MDP_CLK>; 2265 clock-names = "iface", "bus", "ahb", "core"; 2266 2267 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; 2268 assigned-clock-rates = <300000000>; 2269 2270 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 2271 interrupt-controller; 2272 #interrupt-cells = <1>; 2273 2274 iommus = <&apps_smmu 0x800 0x2>; 2275 2276 #address-cells = <2>; 2277 #size-cells = <2>; 2278 ranges; 2279 2280 status = "disabled"; 2281 2282 mdp: mdp@ae01000 { 2283 compatible = "qcom,sc7180-dpu"; 2284 reg = <0 0x0ae01000 0 0x8f000>, 2285 <0 0x0aeb0000 0 0x2008>; 2286 reg-names = "mdp", "vbif"; 2287 2288 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2289 <&dispcc DISP_CC_MDSS_ROT_CLK>, 2290 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 2291 <&dispcc DISP_CC_MDSS_MDP_CLK>, 2292 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2293 clock-names = "iface", "rot", "lut", "core", 2294 "vsync"; 2295 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, 2296 <&dispcc DISP_CC_MDSS_VSYNC_CLK>, 2297 <&dispcc DISP_CC_MDSS_ROT_CLK>, 2298 <&dispcc DISP_CC_MDSS_AHB_CLK>; 2299 assigned-clock-rates = <300000000>, 2300 <19200000>, 2301 <19200000>, 2302 <19200000>; 2303 2304 interrupt-parent = <&mdss>; 2305 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; 2306 2307 status = "disabled"; 2308 2309 ports { 2310 #address-cells = <1>; 2311 #size-cells = <0>; 2312 2313 port@0 { 2314 reg = <0>; 2315 dpu_intf1_out: endpoint { 2316 remote-endpoint = <&dsi0_in>; 2317 }; 2318 }; 2319 }; 2320 }; 2321 2322 dsi0: dsi@ae94000 { 2323 compatible = "qcom,mdss-dsi-ctrl"; 2324 reg = <0 0x0ae94000 0 0x400>; 2325 reg-names = "dsi_ctrl"; 2326 2327 interrupt-parent = <&mdss>; 2328 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; 2329 2330 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 2331 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 2332 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 2333 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 2334 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2335 <&gcc GCC_DISP_HF_AXI_CLK>; 2336 clock-names = "byte", 2337 "byte_intf", 2338 "pixel", 2339 "core", 2340 "iface", 2341 "bus"; 2342 2343 phys = <&dsi_phy>; 2344 phy-names = "dsi"; 2345 2346 #address-cells = <1>; 2347 #size-cells = <0>; 2348 2349 status = "disabled"; 2350 2351 ports { 2352 #address-cells = <1>; 2353 #size-cells = <0>; 2354 2355 port@0 { 2356 reg = <0>; 2357 dsi0_in: endpoint { 2358 remote-endpoint = <&dpu_intf1_out>; 2359 }; 2360 }; 2361 2362 port@1 { 2363 reg = <1>; 2364 dsi0_out: endpoint { 2365 }; 2366 }; 2367 }; 2368 }; 2369 2370 dsi_phy: dsi-phy@ae94400 { 2371 compatible = "qcom,dsi-phy-10nm"; 2372 reg = <0 0x0ae94400 0 0x200>, 2373 <0 0x0ae94600 0 0x280>, 2374 <0 0x0ae94a00 0 0x1e0>; 2375 reg-names = "dsi_phy", 2376 "dsi_phy_lane", 2377 "dsi_pll"; 2378 2379 #clock-cells = <1>; 2380 #phy-cells = <0>; 2381 2382 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2383 <&rpmhcc RPMH_CXO_CLK>; 2384 clock-names = "iface", "ref"; 2385 2386 status = "disabled"; 2387 }; 2388 }; 2389 2390 dispcc: clock-controller@af00000 { 2391 compatible = "qcom,sc7180-dispcc"; 2392 reg = <0 0x0af00000 0 0x200000>; 2393 clocks = <&rpmhcc RPMH_CXO_CLK>, 2394 <&gcc GCC_DISP_GPLL0_CLK_SRC>, 2395 <&dsi_phy 0>, 2396 <&dsi_phy 1>, 2397 <0>, 2398 <0>; 2399 clock-names = "bi_tcxo", 2400 "gcc_disp_gpll0_clk_src", 2401 "dsi0_phy_pll_out_byteclk", 2402 "dsi0_phy_pll_out_dsiclk", 2403 "dp_phy_pll_link_clk", 2404 "dp_phy_pll_vco_div_clk"; 2405 #clock-cells = <1>; 2406 #reset-cells = <1>; 2407 #power-domain-cells = <1>; 2408 }; 2409 2410 pdc: interrupt-controller@b220000 { 2411 compatible = "qcom,sc7180-pdc", "qcom,pdc"; 2412 reg = <0 0x0b220000 0 0x30000>; 2413 qcom,pdc-ranges = <0 480 15>, <17 497 98>, 2414 <119 634 4>, <124 639 1>; 2415 #interrupt-cells = <2>; 2416 interrupt-parent = <&intc>; 2417 interrupt-controller; 2418 }; 2419 2420 pdc_reset: reset-controller@b2e0000 { 2421 compatible = "qcom,sc7180-pdc-global", "qcom,sdm845-pdc-global"; 2422 reg = <0 0x0b2e0000 0 0x20000>; 2423 #reset-cells = <1>; 2424 }; 2425 2426 tsens0: thermal-sensor@c263000 { 2427 compatible = "qcom,sc7180-tsens","qcom,tsens-v2"; 2428 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 2429 <0 0x0c222000 0 0x1ff>; /* SROT */ 2430 #qcom,sensors = <15>; 2431 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 2432 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 2433 interrupt-names = "uplow","critical"; 2434 #thermal-sensor-cells = <1>; 2435 }; 2436 2437 tsens1: thermal-sensor@c265000 { 2438 compatible = "qcom,sc7180-tsens","qcom,tsens-v2"; 2439 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 2440 <0 0x0c223000 0 0x1ff>; /* SROT */ 2441 #qcom,sensors = <10>; 2442 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 2443 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 2444 interrupt-names = "uplow","critical"; 2445 #thermal-sensor-cells = <1>; 2446 }; 2447 2448 aoss_reset: reset-controller@c2a0000 { 2449 compatible = "qcom,sc7180-aoss-cc", "qcom,sdm845-aoss-cc"; 2450 reg = <0 0x0c2a0000 0 0x31000>; 2451 #reset-cells = <1>; 2452 }; 2453 2454 aoss_qmp: qmp@c300000 { 2455 compatible = "qcom,sc7180-aoss-qmp"; 2456 reg = <0 0x0c300000 0 0x100000>; 2457 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>; 2458 mboxes = <&apss_shared 0>; 2459 2460 #clock-cells = <0>; 2461 #power-domain-cells = <1>; 2462 }; 2463 2464 spmi_bus: spmi@c440000 { 2465 compatible = "qcom,spmi-pmic-arb"; 2466 reg = <0 0x0c440000 0 0x1100>, 2467 <0 0x0c600000 0 0x2000000>, 2468 <0 0x0e600000 0 0x100000>, 2469 <0 0x0e700000 0 0xa0000>, 2470 <0 0x0c40a000 0 0x26000>; 2471 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 2472 interrupt-names = "periph_irq"; 2473 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 2474 qcom,ee = <0>; 2475 qcom,channel = <0>; 2476 #address-cells = <1>; 2477 #size-cells = <1>; 2478 interrupt-controller; 2479 #interrupt-cells = <4>; 2480 cell-index = <0>; 2481 }; 2482 2483 apps_smmu: iommu@15000000 { 2484 compatible = "qcom,sc7180-smmu-500", "arm,mmu-500"; 2485 reg = <0 0x15000000 0 0x100000>; 2486 #iommu-cells = <2>; 2487 #global-interrupts = <1>; 2488 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 2489 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 2490 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 2491 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 2492 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 2493 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 2494 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 2495 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 2496 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 2497 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 2498 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 2499 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 2500 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 2501 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 2502 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 2503 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 2504 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 2505 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 2506 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 2507 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 2508 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 2509 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 2510 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 2511 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 2512 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 2513 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 2514 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 2515 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 2516 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 2517 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 2518 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 2519 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 2520 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 2521 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 2522 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 2523 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 2524 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 2525 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 2526 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 2527 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 2528 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 2529 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 2530 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 2531 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 2532 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 2533 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 2534 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 2535 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 2536 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 2537 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 2538 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 2539 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 2540 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 2541 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 2542 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 2543 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 2544 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 2545 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 2546 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 2547 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 2548 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 2549 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 2550 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 2551 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 2552 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 2553 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 2554 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 2555 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 2556 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 2557 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 2558 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 2559 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 2560 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 2561 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 2562 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 2563 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 2564 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 2565 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 2566 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, 2567 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>, 2568 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>; 2569 }; 2570 2571 intc: interrupt-controller@17a00000 { 2572 compatible = "arm,gic-v3"; 2573 #address-cells = <2>; 2574 #size-cells = <2>; 2575 ranges; 2576 #interrupt-cells = <3>; 2577 interrupt-controller; 2578 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 2579 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 2580 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 2581 2582 msi-controller@17a40000 { 2583 compatible = "arm,gic-v3-its"; 2584 msi-controller; 2585 #msi-cells = <1>; 2586 reg = <0 0x17a40000 0 0x20000>; 2587 status = "disabled"; 2588 }; 2589 }; 2590 2591 apss_shared: mailbox@17c00000 { 2592 compatible = "qcom,sc7180-apss-shared"; 2593 reg = <0 0x17c00000 0 0x10000>; 2594 #mbox-cells = <1>; 2595 }; 2596 2597 watchdog@17c10000 { 2598 compatible = "qcom,apss-wdt-sc7180", "qcom,kpss-wdt"; 2599 reg = <0 0x17c10000 0 0x1000>; 2600 clocks = <&sleep_clk>; 2601 }; 2602 2603 timer@17c20000{ 2604 #address-cells = <2>; 2605 #size-cells = <2>; 2606 ranges; 2607 compatible = "arm,armv7-timer-mem"; 2608 reg = <0 0x17c20000 0 0x1000>; 2609 2610 frame@17c21000 { 2611 frame-number = <0>; 2612 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 2613 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 2614 reg = <0 0x17c21000 0 0x1000>, 2615 <0 0x17c22000 0 0x1000>; 2616 }; 2617 2618 frame@17c23000 { 2619 frame-number = <1>; 2620 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 2621 reg = <0 0x17c23000 0 0x1000>; 2622 status = "disabled"; 2623 }; 2624 2625 frame@17c25000 { 2626 frame-number = <2>; 2627 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 2628 reg = <0 0x17c25000 0 0x1000>; 2629 status = "disabled"; 2630 }; 2631 2632 frame@17c27000 { 2633 frame-number = <3>; 2634 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 2635 reg = <0 0x17c27000 0 0x1000>; 2636 status = "disabled"; 2637 }; 2638 2639 frame@17c29000 { 2640 frame-number = <4>; 2641 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 2642 reg = <0 0x17c29000 0 0x1000>; 2643 status = "disabled"; 2644 }; 2645 2646 frame@17c2b000 { 2647 frame-number = <5>; 2648 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 2649 reg = <0 0x17c2b000 0 0x1000>; 2650 status = "disabled"; 2651 }; 2652 2653 frame@17c2d000 { 2654 frame-number = <6>; 2655 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 2656 reg = <0 0x17c2d000 0 0x1000>; 2657 status = "disabled"; 2658 }; 2659 }; 2660 2661 apps_rsc: rsc@18200000 { 2662 compatible = "qcom,rpmh-rsc"; 2663 reg = <0 0x18200000 0 0x10000>, 2664 <0 0x18210000 0 0x10000>, 2665 <0 0x18220000 0 0x10000>; 2666 reg-names = "drv-0", "drv-1", "drv-2"; 2667 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 2668 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 2669 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 2670 qcom,tcs-offset = <0xd00>; 2671 qcom,drv-id = <2>; 2672 qcom,tcs-config = <ACTIVE_TCS 2>, 2673 <SLEEP_TCS 3>, 2674 <WAKE_TCS 3>, 2675 <CONTROL_TCS 1>; 2676 2677 rpmhcc: clock-controller { 2678 compatible = "qcom,sc7180-rpmh-clk"; 2679 clocks = <&xo_board>; 2680 clock-names = "xo"; 2681 #clock-cells = <1>; 2682 }; 2683 2684 rpmhpd: power-controller { 2685 compatible = "qcom,sc7180-rpmhpd"; 2686 #power-domain-cells = <1>; 2687 operating-points-v2 = <&rpmhpd_opp_table>; 2688 2689 rpmhpd_opp_table: opp-table { 2690 compatible = "operating-points-v2"; 2691 2692 rpmhpd_opp_ret: opp1 { 2693 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 2694 }; 2695 2696 rpmhpd_opp_min_svs: opp2 { 2697 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2698 }; 2699 2700 rpmhpd_opp_low_svs: opp3 { 2701 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2702 }; 2703 2704 rpmhpd_opp_svs: opp4 { 2705 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2706 }; 2707 2708 rpmhpd_opp_svs_l1: opp5 { 2709 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2710 }; 2711 2712 rpmhpd_opp_svs_l2: opp6 { 2713 opp-level = <224>; 2714 }; 2715 2716 rpmhpd_opp_nom: opp7 { 2717 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2718 }; 2719 2720 rpmhpd_opp_nom_l1: opp8 { 2721 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2722 }; 2723 2724 rpmhpd_opp_nom_l2: opp9 { 2725 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 2726 }; 2727 2728 rpmhpd_opp_turbo: opp10 { 2729 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 2730 }; 2731 2732 rpmhpd_opp_turbo_l1: opp11 { 2733 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 2734 }; 2735 }; 2736 }; 2737 2738 apps_bcm_voter: bcm_voter { 2739 compatible = "qcom,bcm-voter"; 2740 }; 2741 }; 2742 2743 osm_l3: interconnect@18321000 { 2744 compatible = "qcom,sc7180-osm-l3"; 2745 reg = <0 0x18321000 0 0x1400>; 2746 2747 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 2748 clock-names = "xo", "alternate"; 2749 2750 #interconnect-cells = <1>; 2751 }; 2752 2753 cpufreq_hw: cpufreq@18323000 { 2754 compatible = "qcom,cpufreq-hw"; 2755 reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>; 2756 reg-names = "freq-domain0", "freq-domain1"; 2757 2758 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 2759 clock-names = "xo", "alternate"; 2760 2761 #freq-domain-cells = <1>; 2762 }; 2763 }; 2764 2765 thermal-zones { 2766 cpu0-thermal { 2767 polling-delay-passive = <0>; 2768 polling-delay = <0>; 2769 2770 thermal-sensors = <&tsens0 1>; 2771 2772 trips { 2773 cpu0_alert0: trip-point0 { 2774 temperature = <90000>; 2775 hysteresis = <2000>; 2776 type = "passive"; 2777 }; 2778 2779 cpu0_alert1: trip-point1 { 2780 temperature = <95000>; 2781 hysteresis = <2000>; 2782 type = "passive"; 2783 }; 2784 2785 cpu0_crit: cpu_crit { 2786 temperature = <110000>; 2787 hysteresis = <1000>; 2788 type = "critical"; 2789 }; 2790 }; 2791 2792 cooling-maps { 2793 map0 { 2794 trip = <&cpu0_alert0>; 2795 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2796 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2797 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2798 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2799 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2800 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2801 }; 2802 map1 { 2803 trip = <&cpu0_alert1>; 2804 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2805 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2806 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2807 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2808 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2809 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2810 }; 2811 }; 2812 }; 2813 2814 cpu1-thermal { 2815 polling-delay-passive = <0>; 2816 polling-delay = <0>; 2817 2818 thermal-sensors = <&tsens0 2>; 2819 2820 trips { 2821 cpu1_alert0: trip-point0 { 2822 temperature = <90000>; 2823 hysteresis = <2000>; 2824 type = "passive"; 2825 }; 2826 2827 cpu1_alert1: trip-point1 { 2828 temperature = <95000>; 2829 hysteresis = <2000>; 2830 type = "passive"; 2831 }; 2832 2833 cpu1_crit: cpu_crit { 2834 temperature = <110000>; 2835 hysteresis = <1000>; 2836 type = "critical"; 2837 }; 2838 }; 2839 2840 cooling-maps { 2841 map0 { 2842 trip = <&cpu1_alert0>; 2843 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2844 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2845 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2846 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2847 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2848 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2849 }; 2850 map1 { 2851 trip = <&cpu1_alert1>; 2852 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2853 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2854 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2855 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2856 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2857 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2858 }; 2859 }; 2860 }; 2861 2862 cpu2-thermal { 2863 polling-delay-passive = <0>; 2864 polling-delay = <0>; 2865 2866 thermal-sensors = <&tsens0 3>; 2867 2868 trips { 2869 cpu2_alert0: trip-point0 { 2870 temperature = <90000>; 2871 hysteresis = <2000>; 2872 type = "passive"; 2873 }; 2874 2875 cpu2_alert1: trip-point1 { 2876 temperature = <95000>; 2877 hysteresis = <2000>; 2878 type = "passive"; 2879 }; 2880 2881 cpu2_crit: cpu_crit { 2882 temperature = <110000>; 2883 hysteresis = <1000>; 2884 type = "critical"; 2885 }; 2886 }; 2887 2888 cooling-maps { 2889 map0 { 2890 trip = <&cpu2_alert0>; 2891 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2892 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2893 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2894 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2895 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2896 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2897 }; 2898 map1 { 2899 trip = <&cpu2_alert1>; 2900 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2901 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2902 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2903 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2904 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2905 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2906 }; 2907 }; 2908 }; 2909 2910 cpu3-thermal { 2911 polling-delay-passive = <0>; 2912 polling-delay = <0>; 2913 2914 thermal-sensors = <&tsens0 4>; 2915 2916 trips { 2917 cpu3_alert0: trip-point0 { 2918 temperature = <90000>; 2919 hysteresis = <2000>; 2920 type = "passive"; 2921 }; 2922 2923 cpu3_alert1: trip-point1 { 2924 temperature = <95000>; 2925 hysteresis = <2000>; 2926 type = "passive"; 2927 }; 2928 2929 cpu3_crit: cpu_crit { 2930 temperature = <110000>; 2931 hysteresis = <1000>; 2932 type = "critical"; 2933 }; 2934 }; 2935 2936 cooling-maps { 2937 map0 { 2938 trip = <&cpu3_alert0>; 2939 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2940 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2941 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2942 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2943 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2944 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2945 }; 2946 map1 { 2947 trip = <&cpu3_alert1>; 2948 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2949 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2950 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2951 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2952 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2953 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2954 }; 2955 }; 2956 }; 2957 2958 cpu4-thermal { 2959 polling-delay-passive = <0>; 2960 polling-delay = <0>; 2961 2962 thermal-sensors = <&tsens0 5>; 2963 2964 trips { 2965 cpu4_alert0: trip-point0 { 2966 temperature = <90000>; 2967 hysteresis = <2000>; 2968 type = "passive"; 2969 }; 2970 2971 cpu4_alert1: trip-point1 { 2972 temperature = <95000>; 2973 hysteresis = <2000>; 2974 type = "passive"; 2975 }; 2976 2977 cpu4_crit: cpu_crit { 2978 temperature = <110000>; 2979 hysteresis = <1000>; 2980 type = "critical"; 2981 }; 2982 }; 2983 2984 cooling-maps { 2985 map0 { 2986 trip = <&cpu4_alert0>; 2987 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2988 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2989 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2990 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2991 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2992 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2993 }; 2994 map1 { 2995 trip = <&cpu4_alert1>; 2996 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2997 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2998 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2999 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3000 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3001 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3002 }; 3003 }; 3004 }; 3005 3006 cpu5-thermal { 3007 polling-delay-passive = <0>; 3008 polling-delay = <0>; 3009 3010 thermal-sensors = <&tsens0 6>; 3011 3012 trips { 3013 cpu5_alert0: trip-point0 { 3014 temperature = <90000>; 3015 hysteresis = <2000>; 3016 type = "passive"; 3017 }; 3018 3019 cpu5_alert1: trip-point1 { 3020 temperature = <95000>; 3021 hysteresis = <2000>; 3022 type = "passive"; 3023 }; 3024 3025 cpu5_crit: cpu_crit { 3026 temperature = <110000>; 3027 hysteresis = <1000>; 3028 type = "critical"; 3029 }; 3030 }; 3031 3032 cooling-maps { 3033 map0 { 3034 trip = <&cpu5_alert0>; 3035 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3036 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3037 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3038 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3039 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3040 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3041 }; 3042 map1 { 3043 trip = <&cpu5_alert1>; 3044 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3045 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3046 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3047 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3048 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3049 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3050 }; 3051 }; 3052 }; 3053 3054 cpu6-thermal { 3055 polling-delay-passive = <0>; 3056 polling-delay = <0>; 3057 3058 thermal-sensors = <&tsens0 9>; 3059 3060 trips { 3061 cpu6_alert0: trip-point0 { 3062 temperature = <90000>; 3063 hysteresis = <2000>; 3064 type = "passive"; 3065 }; 3066 3067 cpu6_alert1: trip-point1 { 3068 temperature = <95000>; 3069 hysteresis = <2000>; 3070 type = "passive"; 3071 }; 3072 3073 cpu6_crit: cpu_crit { 3074 temperature = <110000>; 3075 hysteresis = <1000>; 3076 type = "critical"; 3077 }; 3078 }; 3079 3080 cooling-maps { 3081 map0 { 3082 trip = <&cpu6_alert0>; 3083 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3084 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3085 }; 3086 map1 { 3087 trip = <&cpu6_alert1>; 3088 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3089 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3090 }; 3091 }; 3092 }; 3093 3094 cpu7-thermal { 3095 polling-delay-passive = <0>; 3096 polling-delay = <0>; 3097 3098 thermal-sensors = <&tsens0 10>; 3099 3100 trips { 3101 cpu7_alert0: trip-point0 { 3102 temperature = <90000>; 3103 hysteresis = <2000>; 3104 type = "passive"; 3105 }; 3106 3107 cpu7_alert1: trip-point1 { 3108 temperature = <95000>; 3109 hysteresis = <2000>; 3110 type = "passive"; 3111 }; 3112 3113 cpu7_crit: cpu_crit { 3114 temperature = <110000>; 3115 hysteresis = <1000>; 3116 type = "critical"; 3117 }; 3118 }; 3119 3120 cooling-maps { 3121 map0 { 3122 trip = <&cpu7_alert0>; 3123 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3124 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3125 }; 3126 map1 { 3127 trip = <&cpu7_alert1>; 3128 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3129 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3130 }; 3131 }; 3132 }; 3133 3134 cpu8-thermal { 3135 polling-delay-passive = <0>; 3136 polling-delay = <0>; 3137 3138 thermal-sensors = <&tsens0 11>; 3139 3140 trips { 3141 cpu8_alert0: trip-point0 { 3142 temperature = <90000>; 3143 hysteresis = <2000>; 3144 type = "passive"; 3145 }; 3146 3147 cpu8_alert1: trip-point1 { 3148 temperature = <95000>; 3149 hysteresis = <2000>; 3150 type = "passive"; 3151 }; 3152 3153 cpu8_crit: cpu_crit { 3154 temperature = <110000>; 3155 hysteresis = <1000>; 3156 type = "critical"; 3157 }; 3158 }; 3159 3160 cooling-maps { 3161 map0 { 3162 trip = <&cpu8_alert0>; 3163 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3164 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3165 }; 3166 map1 { 3167 trip = <&cpu8_alert1>; 3168 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3169 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3170 }; 3171 }; 3172 }; 3173 3174 cpu9-thermal { 3175 polling-delay-passive = <0>; 3176 polling-delay = <0>; 3177 3178 thermal-sensors = <&tsens0 12>; 3179 3180 trips { 3181 cpu9_alert0: trip-point0 { 3182 temperature = <90000>; 3183 hysteresis = <2000>; 3184 type = "passive"; 3185 }; 3186 3187 cpu9_alert1: trip-point1 { 3188 temperature = <95000>; 3189 hysteresis = <2000>; 3190 type = "passive"; 3191 }; 3192 3193 cpu9_crit: cpu_crit { 3194 temperature = <110000>; 3195 hysteresis = <1000>; 3196 type = "critical"; 3197 }; 3198 }; 3199 3200 cooling-maps { 3201 map0 { 3202 trip = <&cpu9_alert0>; 3203 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3204 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3205 }; 3206 map1 { 3207 trip = <&cpu9_alert1>; 3208 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3209 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3210 }; 3211 }; 3212 }; 3213 3214 aoss0-thermal { 3215 polling-delay-passive = <0>; 3216 polling-delay = <0>; 3217 3218 thermal-sensors = <&tsens0 0>; 3219 3220 trips { 3221 aoss0_alert0: trip-point0 { 3222 temperature = <90000>; 3223 hysteresis = <2000>; 3224 type = "hot"; 3225 }; 3226 3227 aoss0_crit: aoss0_crit { 3228 temperature = <110000>; 3229 hysteresis = <2000>; 3230 type = "critical"; 3231 }; 3232 }; 3233 }; 3234 3235 cpuss0-thermal { 3236 polling-delay-passive = <0>; 3237 polling-delay = <0>; 3238 3239 thermal-sensors = <&tsens0 7>; 3240 3241 trips { 3242 cpuss0_alert0: trip-point0 { 3243 temperature = <90000>; 3244 hysteresis = <2000>; 3245 type = "hot"; 3246 }; 3247 cpuss0_crit: cluster0_crit { 3248 temperature = <110000>; 3249 hysteresis = <2000>; 3250 type = "critical"; 3251 }; 3252 }; 3253 }; 3254 3255 cpuss1-thermal { 3256 polling-delay-passive = <0>; 3257 polling-delay = <0>; 3258 3259 thermal-sensors = <&tsens0 8>; 3260 3261 trips { 3262 cpuss1_alert0: trip-point0 { 3263 temperature = <90000>; 3264 hysteresis = <2000>; 3265 type = "hot"; 3266 }; 3267 cpuss1_crit: cluster0_crit { 3268 temperature = <110000>; 3269 hysteresis = <2000>; 3270 type = "critical"; 3271 }; 3272 }; 3273 }; 3274 3275 gpuss0-thermal { 3276 polling-delay-passive = <0>; 3277 polling-delay = <0>; 3278 3279 thermal-sensors = <&tsens0 13>; 3280 3281 trips { 3282 gpuss0_alert0: trip-point0 { 3283 temperature = <90000>; 3284 hysteresis = <2000>; 3285 type = "hot"; 3286 }; 3287 3288 gpuss0_crit: gpuss0_crit { 3289 temperature = <110000>; 3290 hysteresis = <2000>; 3291 type = "critical"; 3292 }; 3293 }; 3294 }; 3295 3296 gpuss1-thermal { 3297 polling-delay-passive = <0>; 3298 polling-delay = <0>; 3299 3300 thermal-sensors = <&tsens0 14>; 3301 3302 trips { 3303 gpuss1_alert0: trip-point0 { 3304 temperature = <90000>; 3305 hysteresis = <2000>; 3306 type = "hot"; 3307 }; 3308 3309 gpuss1_crit: gpuss1_crit { 3310 temperature = <110000>; 3311 hysteresis = <2000>; 3312 type = "critical"; 3313 }; 3314 }; 3315 }; 3316 3317 aoss1-thermal { 3318 polling-delay-passive = <0>; 3319 polling-delay = <0>; 3320 3321 thermal-sensors = <&tsens1 0>; 3322 3323 trips { 3324 aoss1_alert0: trip-point0 { 3325 temperature = <90000>; 3326 hysteresis = <2000>; 3327 type = "hot"; 3328 }; 3329 3330 aoss1_crit: aoss1_crit { 3331 temperature = <110000>; 3332 hysteresis = <2000>; 3333 type = "critical"; 3334 }; 3335 }; 3336 }; 3337 3338 cwlan-thermal { 3339 polling-delay-passive = <0>; 3340 polling-delay = <0>; 3341 3342 thermal-sensors = <&tsens1 1>; 3343 3344 trips { 3345 cwlan_alert0: trip-point0 { 3346 temperature = <90000>; 3347 hysteresis = <2000>; 3348 type = "hot"; 3349 }; 3350 3351 cwlan_crit: cwlan_crit { 3352 temperature = <110000>; 3353 hysteresis = <2000>; 3354 type = "critical"; 3355 }; 3356 }; 3357 }; 3358 3359 audio-thermal { 3360 polling-delay-passive = <0>; 3361 polling-delay = <0>; 3362 3363 thermal-sensors = <&tsens1 2>; 3364 3365 trips { 3366 audio_alert0: trip-point0 { 3367 temperature = <90000>; 3368 hysteresis = <2000>; 3369 type = "hot"; 3370 }; 3371 3372 audio_crit: audio_crit { 3373 temperature = <110000>; 3374 hysteresis = <2000>; 3375 type = "critical"; 3376 }; 3377 }; 3378 }; 3379 3380 ddr-thermal { 3381 polling-delay-passive = <0>; 3382 polling-delay = <0>; 3383 3384 thermal-sensors = <&tsens1 3>; 3385 3386 trips { 3387 ddr_alert0: trip-point0 { 3388 temperature = <90000>; 3389 hysteresis = <2000>; 3390 type = "hot"; 3391 }; 3392 3393 ddr_crit: ddr_crit { 3394 temperature = <110000>; 3395 hysteresis = <2000>; 3396 type = "critical"; 3397 }; 3398 }; 3399 }; 3400 3401 q6-hvx-thermal { 3402 polling-delay-passive = <0>; 3403 polling-delay = <0>; 3404 3405 thermal-sensors = <&tsens1 4>; 3406 3407 trips { 3408 q6_hvx_alert0: trip-point0 { 3409 temperature = <90000>; 3410 hysteresis = <2000>; 3411 type = "hot"; 3412 }; 3413 3414 q6_hvx_crit: q6_hvx_crit { 3415 temperature = <110000>; 3416 hysteresis = <2000>; 3417 type = "critical"; 3418 }; 3419 }; 3420 }; 3421 3422 camera-thermal { 3423 polling-delay-passive = <0>; 3424 polling-delay = <0>; 3425 3426 thermal-sensors = <&tsens1 5>; 3427 3428 trips { 3429 camera_alert0: trip-point0 { 3430 temperature = <90000>; 3431 hysteresis = <2000>; 3432 type = "hot"; 3433 }; 3434 3435 camera_crit: camera_crit { 3436 temperature = <110000>; 3437 hysteresis = <2000>; 3438 type = "critical"; 3439 }; 3440 }; 3441 }; 3442 3443 mdm-core-thermal { 3444 polling-delay-passive = <0>; 3445 polling-delay = <0>; 3446 3447 thermal-sensors = <&tsens1 6>; 3448 3449 trips { 3450 mdm_alert0: trip-point0 { 3451 temperature = <90000>; 3452 hysteresis = <2000>; 3453 type = "hot"; 3454 }; 3455 3456 mdm_crit: mdm_crit { 3457 temperature = <110000>; 3458 hysteresis = <2000>; 3459 type = "critical"; 3460 }; 3461 }; 3462 }; 3463 3464 mdm-dsp-thermal { 3465 polling-delay-passive = <0>; 3466 polling-delay = <0>; 3467 3468 thermal-sensors = <&tsens1 7>; 3469 3470 trips { 3471 mdm_dsp_alert0: trip-point0 { 3472 temperature = <90000>; 3473 hysteresis = <2000>; 3474 type = "hot"; 3475 }; 3476 3477 mdm_dsp_crit: mdm_dsp_crit { 3478 temperature = <110000>; 3479 hysteresis = <2000>; 3480 type = "critical"; 3481 }; 3482 }; 3483 }; 3484 3485 npu-thermal { 3486 polling-delay-passive = <0>; 3487 polling-delay = <0>; 3488 3489 thermal-sensors = <&tsens1 8>; 3490 3491 trips { 3492 npu_alert0: trip-point0 { 3493 temperature = <90000>; 3494 hysteresis = <2000>; 3495 type = "hot"; 3496 }; 3497 3498 npu_crit: npu_crit { 3499 temperature = <110000>; 3500 hysteresis = <2000>; 3501 type = "critical"; 3502 }; 3503 }; 3504 }; 3505 3506 video-thermal { 3507 polling-delay-passive = <0>; 3508 polling-delay = <0>; 3509 3510 thermal-sensors = <&tsens1 9>; 3511 3512 trips { 3513 video_alert0: trip-point0 { 3514 temperature = <90000>; 3515 hysteresis = <2000>; 3516 type = "hot"; 3517 }; 3518 3519 video_crit: video_crit { 3520 temperature = <110000>; 3521 hysteresis = <2000>; 3522 type = "critical"; 3523 }; 3524 }; 3525 }; 3526 }; 3527 3528 timer { 3529 compatible = "arm,armv8-timer"; 3530 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, 3531 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, 3532 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, 3533 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; 3534 }; 3535}; 3536