sc7180.dtsi (29c5cb641b59057bae0fe243da5b3b1a1e760227) sc7180.dtsi (f5ab220d162c20c105e7e38852fffe5767679bec)
1// SPDX-License-Identifier: BSD-3-Clause
2/*
3 * SC7180 SoC device tree source
4 *
5 * Copyright (c) 2019, The Linux Foundation. All rights reserved.
6 */
7
8#include <dt-bindings/clock/qcom,gcc-sc7180.h>
9#include <dt-bindings/clock/qcom,rpmh.h>
10#include <dt-bindings/interrupt-controller/arm-gic.h>
11#include <dt-bindings/phy/phy-qcom-qusb2.h>
1// SPDX-License-Identifier: BSD-3-Clause
2/*
3 * SC7180 SoC device tree source
4 *
5 * Copyright (c) 2019, The Linux Foundation. All rights reserved.
6 */
7
8#include <dt-bindings/clock/qcom,gcc-sc7180.h>
9#include <dt-bindings/clock/qcom,rpmh.h>
10#include <dt-bindings/interrupt-controller/arm-gic.h>
11#include <dt-bindings/phy/phy-qcom-qusb2.h>
12#include <dt-bindings/power/qcom-aoss-qmp.h>
13#include <dt-bindings/reset/qcom,sdm845-aoss.h>
14#include <dt-bindings/reset/qcom,sdm845-pdc.h>
12#include <dt-bindings/soc/qcom,rpmh-rsc.h>
13
14/ {
15 interrupt-parent = <&intc>;
16
17 #address-cells = <2>;
18 #size-cells = <2>;
19

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59 reserved_memory: reserved-memory {
60 #address-cells = <2>;
61 #size-cells = <2>;
62 ranges;
63
64 aop_cmd_db_mem: memory@80820000 {
65 reg = <0x0 0x80820000 0x0 0x20000>;
66 compatible = "qcom,cmd-db";
15#include <dt-bindings/soc/qcom,rpmh-rsc.h>
16
17/ {
18 interrupt-parent = <&intc>;
19
20 #address-cells = <2>;
21 #size-cells = <2>;
22

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62 reserved_memory: reserved-memory {
63 #address-cells = <2>;
64 #size-cells = <2>;
65 ranges;
66
67 aop_cmd_db_mem: memory@80820000 {
68 reg = <0x0 0x80820000 0x0 0x20000>;
69 compatible = "qcom,cmd-db";
70 };
71
72 smem_mem: memory@80900000 {
73 reg = <0x0 0x80900000 0x0 0x200000>;
67 no-map;
68 };
69 };
70
71 cpus {
72 #address-cells = <2>;
73 #size-cells = <0>;
74

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186 reg = <0 0x80000000 0 0>;
187 };
188
189 pmu {
190 compatible = "arm,armv8-pmuv3";
191 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
192 };
193
74 no-map;
75 };
76 };
77
78 cpus {
79 #address-cells = <2>;
80 #size-cells = <0>;
81

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193 reg = <0 0x80000000 0 0>;
194 };
195
196 pmu {
197 compatible = "arm,armv8-pmuv3";
198 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
199 };
200
201 firmware {
202 scm {
203 compatible = "qcom,scm-sc7180", "qcom,scm";
204 };
205 };
206
207 tcsr_mutex: hwlock {
208 compatible = "qcom,tcsr-mutex";
209 syscon = <&tcsr_mutex_regs 0 0x1000>;
210 #hwlock-cells = <1>;
211 };
212
213 smem {
214 compatible = "qcom,smem";
215 memory-region = <&smem_mem>;
216 hwlocks = <&tcsr_mutex 3>;
217 };
218
219 smp2p-cdsp {
220 compatible = "qcom,smp2p";
221 qcom,smem = <94>, <432>;
222
223 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>;
224
225 mboxes = <&apss_shared 6>;
226
227 qcom,local-pid = <0>;
228 qcom,remote-pid = <5>;
229
230 cdsp_smp2p_out: master-kernel {
231 qcom,entry-name = "master-kernel";
232 #qcom,smem-state-cells = <1>;
233 };
234
235 cdsp_smp2p_in: slave-kernel {
236 qcom,entry-name = "slave-kernel";
237
238 interrupt-controller;
239 #interrupt-cells = <2>;
240 };
241 };
242
243 smp2p-lpass {
244 compatible = "qcom,smp2p";
245 qcom,smem = <443>, <429>;
246
247 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
248
249 mboxes = <&apss_shared 10>;
250
251 qcom,local-pid = <0>;
252 qcom,remote-pid = <2>;
253
254 adsp_smp2p_out: master-kernel {
255 qcom,entry-name = "master-kernel";
256 #qcom,smem-state-cells = <1>;
257 };
258
259 adsp_smp2p_in: slave-kernel {
260 qcom,entry-name = "slave-kernel";
261
262 interrupt-controller;
263 #interrupt-cells = <2>;
264 };
265 };
266
267 smp2p-mpss {
268 compatible = "qcom,smp2p";
269 qcom,smem = <435>, <428>;
270 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
271 mboxes = <&apss_shared 14>;
272 qcom,local-pid = <0>;
273 qcom,remote-pid = <1>;
274
275 modem_smp2p_out: master-kernel {
276 qcom,entry-name = "master-kernel";
277 #qcom,smem-state-cells = <1>;
278 };
279
280 modem_smp2p_in: slave-kernel {
281 qcom,entry-name = "slave-kernel";
282 interrupt-controller;
283 #interrupt-cells = <2>;
284 };
285 };
286
194 psci {
195 compatible = "arm,psci-1.0";
196 method = "smc";
197 };
198
199 soc: soc {
200 #address-cells = <2>;
201 #size-cells = <2>;

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637 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
638 pinctrl-names = "default";
639 pinctrl-0 = <&qup_uart11_default>;
640 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
641 status = "disabled";
642 };
643 };
644
287 psci {
288 compatible = "arm,psci-1.0";
289 method = "smc";
290 };
291
292 soc: soc {
293 #address-cells = <2>;
294 #size-cells = <2>;

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730 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
731 pinctrl-names = "default";
732 pinctrl-0 = <&qup_uart11_default>;
733 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
734 status = "disabled";
735 };
736 };
737
738 tcsr_mutex_regs: syscon@1f40000 {
739 compatible = "syscon";
740 reg = <0 0x01f40000 0 0x40000>;
741 };
742
645 tlmm: pinctrl@3500000 {
646 compatible = "qcom,sc7180-pinctrl";
647 reg = <0 0x03500000 0 0x300000>,
648 <0 0x03900000 0 0x300000>,
649 <0 0x03d00000 0 0x300000>;
650 reg-names = "west", "north", "south";
651 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
652 gpio-controller;

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1048 reg = <0 0x0b220000 0 0x30000>;
1049 qcom,pdc-ranges = <0 480 15>, <17 497 98>,
1050 <119 634 4>, <124 639 1>;
1051 #interrupt-cells = <2>;
1052 interrupt-parent = <&intc>;
1053 interrupt-controller;
1054 };
1055
743 tlmm: pinctrl@3500000 {
744 compatible = "qcom,sc7180-pinctrl";
745 reg = <0 0x03500000 0 0x300000>,
746 <0 0x03900000 0 0x300000>,
747 <0 0x03d00000 0 0x300000>;
748 reg-names = "west", "north", "south";
749 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
750 gpio-controller;

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1146 reg = <0 0x0b220000 0 0x30000>;
1147 qcom,pdc-ranges = <0 480 15>, <17 497 98>,
1148 <119 634 4>, <124 639 1>;
1149 #interrupt-cells = <2>;
1150 interrupt-parent = <&intc>;
1151 interrupt-controller;
1152 };
1153
1154 pdc_reset: reset-controller@b2e0000 {
1155 compatible = "qcom,sc7180-pdc-global", "qcom,sdm845-pdc-global";
1156 reg = <0 0x0b2e0000 0 0x20000>;
1157 #reset-cells = <1>;
1158 };
1159
1056 tsens0: thermal-sensor@c263000 {
1057 compatible = "qcom,sc7180-tsens","qcom,tsens-v2";
1058 reg = <0 0x0c263000 0 0x1ff>, /* TM */
1059 <0 0x0c222000 0 0x1ff>; /* SROT */
1060 #qcom,sensors = <15>;
1061 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>;
1062 interrupt-names = "uplow";
1063 #thermal-sensor-cells = <1>;

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1068 reg = <0 0x0c265000 0 0x1ff>, /* TM */
1069 <0 0x0c223000 0 0x1ff>; /* SROT */
1070 #qcom,sensors = <10>;
1071 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>;
1072 interrupt-names = "uplow";
1073 #thermal-sensor-cells = <1>;
1074 };
1075
1160 tsens0: thermal-sensor@c263000 {
1161 compatible = "qcom,sc7180-tsens","qcom,tsens-v2";
1162 reg = <0 0x0c263000 0 0x1ff>, /* TM */
1163 <0 0x0c222000 0 0x1ff>; /* SROT */
1164 #qcom,sensors = <15>;
1165 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>;
1166 interrupt-names = "uplow";
1167 #thermal-sensor-cells = <1>;

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1172 reg = <0 0x0c265000 0 0x1ff>, /* TM */
1173 <0 0x0c223000 0 0x1ff>; /* SROT */
1174 #qcom,sensors = <10>;
1175 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>;
1176 interrupt-names = "uplow";
1177 #thermal-sensor-cells = <1>;
1178 };
1179
1180 aoss_reset: reset-controller@c2a0000 {
1181 compatible = "qcom,sc7180-aoss-cc", "qcom,sdm845-aoss-cc";
1182 reg = <0 0x0c2a0000 0 0x31000>;
1183 #reset-cells = <1>;
1184 };
1185
1186 aoss_qmp: qmp@c300000 {
1187 compatible = "qcom,sc7180-aoss-qmp";
1188 reg = <0 0x0c300000 0 0x100000>;
1189 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
1190 mboxes = <&apss_shared 0>;
1191
1192 #clock-cells = <0>;
1193 #power-domain-cells = <1>;
1194 };
1195
1076 spmi_bus: spmi@c440000 {
1077 compatible = "qcom,spmi-pmic-arb";
1078 reg = <0 0x0c440000 0 0x1100>,
1079 <0 0x0c600000 0 0x2000000>,
1080 <0 0x0e600000 0 0x100000>,
1081 <0 0x0e700000 0 0xa0000>,
1082 <0 0x0c40a000 0 0x26000>;
1083 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";

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1195 compatible = "arm,gic-v3-its";
1196 msi-controller;
1197 #msi-cells = <1>;
1198 reg = <0 0x17a40000 0 0x20000>;
1199 status = "disabled";
1200 };
1201 };
1202
1196 spmi_bus: spmi@c440000 {
1197 compatible = "qcom,spmi-pmic-arb";
1198 reg = <0 0x0c440000 0 0x1100>,
1199 <0 0x0c600000 0 0x2000000>,
1200 <0 0x0e600000 0 0x100000>,
1201 <0 0x0e700000 0 0xa0000>,
1202 <0 0x0c40a000 0 0x26000>;
1203 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";

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1315 compatible = "arm,gic-v3-its";
1316 msi-controller;
1317 #msi-cells = <1>;
1318 reg = <0 0x17a40000 0 0x20000>;
1319 status = "disabled";
1320 };
1321 };
1322
1323 apss_shared: mailbox@17c00000 {
1324 compatible = "qcom,sc7180-apss-shared";
1325 reg = <0 0x17c00000 0 0x10000>;
1326 #mbox-cells = <1>;
1327 };
1328
1203 watchdog@17c10000 {
1204 compatible = "qcom,apss-wdt-sc7180", "qcom,kpss-wdt";
1205 reg = <0 0x17c10000 0 0x1000>;
1206 clocks = <&sleep_clk>;
1207 };
1208
1209 timer@17c20000{
1210 #address-cells = <2>;

--- 607 unchanged lines hidden --- 		1329 watchdog@17c10000 {
1330 compatible = "qcom,apss-wdt-sc7180", "qcom,kpss-wdt";
1331 reg = <0 0x17c10000 0 0x1000>;
1332 clocks = <&sleep_clk>;
1333 };
1334
1335 timer@17c20000{
1336 #address-cells = <2>;

--- 607 unchanged lines hidden ---