1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * SC7180 SoC device tree source 4 * 5 * Copyright (c) 2019, The Linux Foundation. All rights reserved. 6 */ 7 8#include <dt-bindings/clock/qcom,gcc-sc7180.h> 9#include <dt-bindings/clock/qcom,rpmh.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/phy/phy-qcom-qusb2.h> 12#include <dt-bindings/soc/qcom,rpmh-rsc.h> 13 14/ { 15 interrupt-parent = <&intc>; 16 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 chosen { }; 21 22 aliases { 23 i2c0 = &i2c0; 24 i2c1 = &i2c1; 25 i2c2 = &i2c2; 26 i2c3 = &i2c3; 27 i2c4 = &i2c4; 28 i2c5 = &i2c5; 29 i2c6 = &i2c6; 30 i2c7 = &i2c7; 31 i2c8 = &i2c8; 32 i2c9 = &i2c9; 33 i2c10 = &i2c10; 34 i2c11 = &i2c11; 35 spi0 = &spi0; 36 spi1 = &spi1; 37 spi3 = &spi3; 38 spi5 = &spi5; 39 spi6 = &spi6; 40 spi8 = &spi8; 41 spi10 = &spi10; 42 spi11 = &spi11; 43 }; 44 45 clocks { 46 xo_board: xo-board { 47 compatible = "fixed-clock"; 48 clock-frequency = <38400000>; 49 #clock-cells = <0>; 50 }; 51 52 sleep_clk: sleep-clk { 53 compatible = "fixed-clock"; 54 clock-frequency = <32764>; 55 #clock-cells = <0>; 56 }; 57 }; 58 59 reserved_memory: reserved-memory { 60 #address-cells = <2>; 61 #size-cells = <2>; 62 ranges; 63 64 aop_cmd_db_mem: memory@80820000 { 65 reg = <0x0 0x80820000 0x0 0x20000>; 66 compatible = "qcom,cmd-db"; 67 no-map; 68 }; 69 }; 70 71 cpus { 72 #address-cells = <2>; 73 #size-cells = <0>; 74 75 CPU0: cpu@0 { 76 device_type = "cpu"; 77 compatible = "arm,armv8"; 78 reg = <0x0 0x0>; 79 enable-method = "psci"; 80 next-level-cache = <&L2_0>; 81 qcom,freq-domain = <&cpufreq_hw 0>; 82 L2_0: l2-cache { 83 compatible = "cache"; 84 next-level-cache = <&L3_0>; 85 L3_0: l3-cache { 86 compatible = "cache"; 87 }; 88 }; 89 }; 90 91 CPU1: cpu@100 { 92 device_type = "cpu"; 93 compatible = "arm,armv8"; 94 reg = <0x0 0x100>; 95 enable-method = "psci"; 96 next-level-cache = <&L2_100>; 97 qcom,freq-domain = <&cpufreq_hw 0>; 98 L2_100: l2-cache { 99 compatible = "cache"; 100 next-level-cache = <&L3_0>; 101 }; 102 }; 103 104 CPU2: cpu@200 { 105 device_type = "cpu"; 106 compatible = "arm,armv8"; 107 reg = <0x0 0x200>; 108 enable-method = "psci"; 109 next-level-cache = <&L2_200>; 110 qcom,freq-domain = <&cpufreq_hw 0>; 111 L2_200: l2-cache { 112 compatible = "cache"; 113 next-level-cache = <&L3_0>; 114 }; 115 }; 116 117 CPU3: cpu@300 { 118 device_type = "cpu"; 119 compatible = "arm,armv8"; 120 reg = <0x0 0x300>; 121 enable-method = "psci"; 122 next-level-cache = <&L2_300>; 123 qcom,freq-domain = <&cpufreq_hw 0>; 124 L2_300: l2-cache { 125 compatible = "cache"; 126 next-level-cache = <&L3_0>; 127 }; 128 }; 129 130 CPU4: cpu@400 { 131 device_type = "cpu"; 132 compatible = "arm,armv8"; 133 reg = <0x0 0x400>; 134 enable-method = "psci"; 135 next-level-cache = <&L2_400>; 136 qcom,freq-domain = <&cpufreq_hw 0>; 137 L2_400: l2-cache { 138 compatible = "cache"; 139 next-level-cache = <&L3_0>; 140 }; 141 }; 142 143 CPU5: cpu@500 { 144 device_type = "cpu"; 145 compatible = "arm,armv8"; 146 reg = <0x0 0x500>; 147 enable-method = "psci"; 148 next-level-cache = <&L2_500>; 149 qcom,freq-domain = <&cpufreq_hw 0>; 150 L2_500: l2-cache { 151 compatible = "cache"; 152 next-level-cache = <&L3_0>; 153 }; 154 }; 155 156 CPU6: cpu@600 { 157 device_type = "cpu"; 158 compatible = "arm,armv8"; 159 reg = <0x0 0x600>; 160 enable-method = "psci"; 161 next-level-cache = <&L2_600>; 162 qcom,freq-domain = <&cpufreq_hw 1>; 163 L2_600: l2-cache { 164 compatible = "cache"; 165 next-level-cache = <&L3_0>; 166 }; 167 }; 168 169 CPU7: cpu@700 { 170 device_type = "cpu"; 171 compatible = "arm,armv8"; 172 reg = <0x0 0x700>; 173 enable-method = "psci"; 174 next-level-cache = <&L2_700>; 175 qcom,freq-domain = <&cpufreq_hw 1>; 176 L2_700: l2-cache { 177 compatible = "cache"; 178 next-level-cache = <&L3_0>; 179 }; 180 }; 181 }; 182 183 memory@80000000 { 184 device_type = "memory"; 185 /* We expect the bootloader to fill in the size */ 186 reg = <0 0x80000000 0 0>; 187 }; 188 189 pmu { 190 compatible = "arm,armv8-pmuv3"; 191 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>; 192 }; 193 194 psci { 195 compatible = "arm,psci-1.0"; 196 method = "smc"; 197 }; 198 199 soc: soc { 200 #address-cells = <2>; 201 #size-cells = <2>; 202 ranges = <0 0 0 0 0x10 0>; 203 dma-ranges = <0 0 0 0 0x10 0>; 204 compatible = "simple-bus"; 205 206 gcc: clock-controller@100000 { 207 compatible = "qcom,gcc-sc7180"; 208 reg = <0 0x00100000 0 0x1f0000>; 209 clocks = <&rpmhcc RPMH_CXO_CLK>, 210 <&rpmhcc RPMH_CXO_CLK_A>; 211 clock-names = "bi_tcxo", "bi_tcxo_ao"; 212 #clock-cells = <1>; 213 #reset-cells = <1>; 214 #power-domain-cells = <1>; 215 }; 216 217 qfprom@784000 { 218 compatible = "qcom,qfprom"; 219 reg = <0 0x00784000 0 0x8ff>; 220 #address-cells = <1>; 221 #size-cells = <1>; 222 223 qusb2p_hstx_trim: hstx-trim-primary@25b { 224 reg = <0x25b 0x1>; 225 bits = <1 3>; 226 }; 227 }; 228 229 qupv3_id_0: geniqup@8c0000 { 230 compatible = "qcom,geni-se-qup"; 231 reg = <0 0x008c0000 0 0x6000>; 232 clock-names = "m-ahb", "s-ahb"; 233 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 234 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 235 #address-cells = <2>; 236 #size-cells = <2>; 237 ranges; 238 status = "disabled"; 239 240 i2c0: i2c@880000 { 241 compatible = "qcom,geni-i2c"; 242 reg = <0 0x00880000 0 0x4000>; 243 clock-names = "se"; 244 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 245 pinctrl-names = "default"; 246 pinctrl-0 = <&qup_i2c0_default>; 247 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 248 #address-cells = <1>; 249 #size-cells = <0>; 250 status = "disabled"; 251 }; 252 253 spi0: spi@880000 { 254 compatible = "qcom,geni-spi"; 255 reg = <0 0x00880000 0 0x4000>; 256 clock-names = "se"; 257 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 258 pinctrl-names = "default"; 259 pinctrl-0 = <&qup_spi0_default>; 260 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 261 #address-cells = <1>; 262 #size-cells = <0>; 263 status = "disabled"; 264 }; 265 266 uart0: serial@880000 { 267 compatible = "qcom,geni-uart"; 268 reg = <0 0x00880000 0 0x4000>; 269 clock-names = "se"; 270 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 271 pinctrl-names = "default"; 272 pinctrl-0 = <&qup_uart0_default>; 273 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 274 status = "disabled"; 275 }; 276 277 i2c1: i2c@884000 { 278 compatible = "qcom,geni-i2c"; 279 reg = <0 0x00884000 0 0x4000>; 280 clock-names = "se"; 281 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 282 pinctrl-names = "default"; 283 pinctrl-0 = <&qup_i2c1_default>; 284 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 285 #address-cells = <1>; 286 #size-cells = <0>; 287 status = "disabled"; 288 }; 289 290 spi1: spi@884000 { 291 compatible = "qcom,geni-spi"; 292 reg = <0 0x00884000 0 0x4000>; 293 clock-names = "se"; 294 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 295 pinctrl-names = "default"; 296 pinctrl-0 = <&qup_spi1_default>; 297 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 298 #address-cells = <1>; 299 #size-cells = <0>; 300 status = "disabled"; 301 }; 302 303 uart1: serial@884000 { 304 compatible = "qcom,geni-uart"; 305 reg = <0 0x00884000 0 0x4000>; 306 clock-names = "se"; 307 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 308 pinctrl-names = "default"; 309 pinctrl-0 = <&qup_uart1_default>; 310 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 311 status = "disabled"; 312 }; 313 314 i2c2: i2c@888000 { 315 compatible = "qcom,geni-i2c"; 316 reg = <0 0x00888000 0 0x4000>; 317 clock-names = "se"; 318 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 319 pinctrl-names = "default"; 320 pinctrl-0 = <&qup_i2c2_default>; 321 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 322 #address-cells = <1>; 323 #size-cells = <0>; 324 status = "disabled"; 325 }; 326 327 uart2: serial@888000 { 328 compatible = "qcom,geni-uart"; 329 reg = <0 0x00888000 0 0x4000>; 330 clock-names = "se"; 331 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 332 pinctrl-names = "default"; 333 pinctrl-0 = <&qup_uart2_default>; 334 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 335 status = "disabled"; 336 }; 337 338 i2c3: i2c@88c000 { 339 compatible = "qcom,geni-i2c"; 340 reg = <0 0x0088c000 0 0x4000>; 341 clock-names = "se"; 342 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 343 pinctrl-names = "default"; 344 pinctrl-0 = <&qup_i2c3_default>; 345 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 346 #address-cells = <1>; 347 #size-cells = <0>; 348 status = "disabled"; 349 }; 350 351 spi3: spi@88c000 { 352 compatible = "qcom,geni-spi"; 353 reg = <0 0x0088c000 0 0x4000>; 354 clock-names = "se"; 355 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 356 pinctrl-names = "default"; 357 pinctrl-0 = <&qup_spi3_default>; 358 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 359 #address-cells = <1>; 360 #size-cells = <0>; 361 status = "disabled"; 362 }; 363 364 uart3: serial@88c000 { 365 compatible = "qcom,geni-uart"; 366 reg = <0 0x0088c000 0 0x4000>; 367 clock-names = "se"; 368 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 369 pinctrl-names = "default"; 370 pinctrl-0 = <&qup_uart3_default>; 371 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 372 status = "disabled"; 373 }; 374 375 i2c4: i2c@890000 { 376 compatible = "qcom,geni-i2c"; 377 reg = <0 0x00890000 0 0x4000>; 378 clock-names = "se"; 379 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 380 pinctrl-names = "default"; 381 pinctrl-0 = <&qup_i2c4_default>; 382 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 383 #address-cells = <1>; 384 #size-cells = <0>; 385 status = "disabled"; 386 }; 387 388 uart4: serial@890000 { 389 compatible = "qcom,geni-uart"; 390 reg = <0 0x00890000 0 0x4000>; 391 clock-names = "se"; 392 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 393 pinctrl-names = "default"; 394 pinctrl-0 = <&qup_uart4_default>; 395 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 396 status = "disabled"; 397 }; 398 399 i2c5: i2c@894000 { 400 compatible = "qcom,geni-i2c"; 401 reg = <0 0x00894000 0 0x4000>; 402 clock-names = "se"; 403 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 404 pinctrl-names = "default"; 405 pinctrl-0 = <&qup_i2c5_default>; 406 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 407 #address-cells = <1>; 408 #size-cells = <0>; 409 status = "disabled"; 410 }; 411 412 spi5: spi@894000 { 413 compatible = "qcom,geni-spi"; 414 reg = <0 0x00894000 0 0x4000>; 415 clock-names = "se"; 416 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 417 pinctrl-names = "default"; 418 pinctrl-0 = <&qup_spi5_default>; 419 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 420 #address-cells = <1>; 421 #size-cells = <0>; 422 status = "disabled"; 423 }; 424 425 uart5: serial@894000 { 426 compatible = "qcom,geni-uart"; 427 reg = <0 0x00894000 0 0x4000>; 428 clock-names = "se"; 429 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 430 pinctrl-names = "default"; 431 pinctrl-0 = <&qup_uart5_default>; 432 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 433 status = "disabled"; 434 }; 435 }; 436 437 qupv3_id_1: geniqup@ac0000 { 438 compatible = "qcom,geni-se-qup"; 439 reg = <0 0x00ac0000 0 0x6000>; 440 clock-names = "m-ahb", "s-ahb"; 441 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 442 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 443 #address-cells = <2>; 444 #size-cells = <2>; 445 ranges; 446 status = "disabled"; 447 448 i2c6: i2c@a80000 { 449 compatible = "qcom,geni-i2c"; 450 reg = <0 0x00a80000 0 0x4000>; 451 clock-names = "se"; 452 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 453 pinctrl-names = "default"; 454 pinctrl-0 = <&qup_i2c6_default>; 455 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 456 #address-cells = <1>; 457 #size-cells = <0>; 458 status = "disabled"; 459 }; 460 461 spi6: spi@a80000 { 462 compatible = "qcom,geni-spi"; 463 reg = <0 0x00a80000 0 0x4000>; 464 clock-names = "se"; 465 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 466 pinctrl-names = "default"; 467 pinctrl-0 = <&qup_spi6_default>; 468 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 469 #address-cells = <1>; 470 #size-cells = <0>; 471 status = "disabled"; 472 }; 473 474 uart6: serial@a80000 { 475 compatible = "qcom,geni-uart"; 476 reg = <0 0x00a80000 0 0x4000>; 477 clock-names = "se"; 478 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 479 pinctrl-names = "default"; 480 pinctrl-0 = <&qup_uart6_default>; 481 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 482 status = "disabled"; 483 }; 484 485 i2c7: i2c@a84000 { 486 compatible = "qcom,geni-i2c"; 487 reg = <0 0x00a84000 0 0x4000>; 488 clock-names = "se"; 489 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 490 pinctrl-names = "default"; 491 pinctrl-0 = <&qup_i2c7_default>; 492 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 493 #address-cells = <1>; 494 #size-cells = <0>; 495 status = "disabled"; 496 }; 497 498 uart7: serial@a84000 { 499 compatible = "qcom,geni-uart"; 500 reg = <0 0x00a84000 0 0x4000>; 501 clock-names = "se"; 502 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 503 pinctrl-names = "default"; 504 pinctrl-0 = <&qup_uart7_default>; 505 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 506 status = "disabled"; 507 }; 508 509 i2c8: i2c@a88000 { 510 compatible = "qcom,geni-i2c"; 511 reg = <0 0x00a88000 0 0x4000>; 512 clock-names = "se"; 513 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 514 pinctrl-names = "default"; 515 pinctrl-0 = <&qup_i2c8_default>; 516 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 517 #address-cells = <1>; 518 #size-cells = <0>; 519 status = "disabled"; 520 }; 521 522 spi8: spi@a88000 { 523 compatible = "qcom,geni-spi"; 524 reg = <0 0x00a88000 0 0x4000>; 525 clock-names = "se"; 526 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 527 pinctrl-names = "default"; 528 pinctrl-0 = <&qup_spi8_default>; 529 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 530 #address-cells = <1>; 531 #size-cells = <0>; 532 status = "disabled"; 533 }; 534 535 uart8: serial@a88000 { 536 compatible = "qcom,geni-debug-uart"; 537 reg = <0 0x00a88000 0 0x4000>; 538 clock-names = "se"; 539 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 540 pinctrl-names = "default"; 541 pinctrl-0 = <&qup_uart8_default>; 542 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 543 status = "disabled"; 544 }; 545 546 i2c9: i2c@a8c000 { 547 compatible = "qcom,geni-i2c"; 548 reg = <0 0x00a8c000 0 0x4000>; 549 clock-names = "se"; 550 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 551 pinctrl-names = "default"; 552 pinctrl-0 = <&qup_i2c9_default>; 553 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 554 #address-cells = <1>; 555 #size-cells = <0>; 556 status = "disabled"; 557 }; 558 559 uart9: serial@a8c000 { 560 compatible = "qcom,geni-uart"; 561 reg = <0 0x00a8c000 0 0x4000>; 562 clock-names = "se"; 563 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 564 pinctrl-names = "default"; 565 pinctrl-0 = <&qup_uart9_default>; 566 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 567 status = "disabled"; 568 }; 569 570 i2c10: i2c@a90000 { 571 compatible = "qcom,geni-i2c"; 572 reg = <0 0x00a90000 0 0x4000>; 573 clock-names = "se"; 574 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 575 pinctrl-names = "default"; 576 pinctrl-0 = <&qup_i2c10_default>; 577 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 578 #address-cells = <1>; 579 #size-cells = <0>; 580 status = "disabled"; 581 }; 582 583 spi10: spi@a90000 { 584 compatible = "qcom,geni-spi"; 585 reg = <0 0x00a90000 0 0x4000>; 586 clock-names = "se"; 587 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 588 pinctrl-names = "default"; 589 pinctrl-0 = <&qup_spi10_default>; 590 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 591 #address-cells = <1>; 592 #size-cells = <0>; 593 status = "disabled"; 594 }; 595 596 uart10: serial@a90000 { 597 compatible = "qcom,geni-uart"; 598 reg = <0 0x00a90000 0 0x4000>; 599 clock-names = "se"; 600 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 601 pinctrl-names = "default"; 602 pinctrl-0 = <&qup_uart10_default>; 603 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 604 status = "disabled"; 605 }; 606 607 i2c11: i2c@a94000 { 608 compatible = "qcom,geni-i2c"; 609 reg = <0 0x00a94000 0 0x4000>; 610 clock-names = "se"; 611 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 612 pinctrl-names = "default"; 613 pinctrl-0 = <&qup_i2c11_default>; 614 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 615 #address-cells = <1>; 616 #size-cells = <0>; 617 status = "disabled"; 618 }; 619 620 spi11: spi@a94000 { 621 compatible = "qcom,geni-spi"; 622 reg = <0 0x00a94000 0 0x4000>; 623 clock-names = "se"; 624 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 625 pinctrl-names = "default"; 626 pinctrl-0 = <&qup_spi11_default>; 627 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 628 #address-cells = <1>; 629 #size-cells = <0>; 630 status = "disabled"; 631 }; 632 633 uart11: serial@a94000 { 634 compatible = "qcom,geni-uart"; 635 reg = <0 0x00a94000 0 0x4000>; 636 clock-names = "se"; 637 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 638 pinctrl-names = "default"; 639 pinctrl-0 = <&qup_uart11_default>; 640 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 641 status = "disabled"; 642 }; 643 }; 644 645 tlmm: pinctrl@3500000 { 646 compatible = "qcom,sc7180-pinctrl"; 647 reg = <0 0x03500000 0 0x300000>, 648 <0 0x03900000 0 0x300000>, 649 <0 0x03d00000 0 0x300000>; 650 reg-names = "west", "north", "south"; 651 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 652 gpio-controller; 653 #gpio-cells = <2>; 654 interrupt-controller; 655 #interrupt-cells = <2>; 656 gpio-ranges = <&tlmm 0 0 120>; 657 wakeup-parent = <&pdc>; 658 659 qspi_clk: qspi-clk { 660 pinmux { 661 pins = "gpio63"; 662 function = "qspi_clk"; 663 }; 664 }; 665 666 qspi_cs0: qspi-cs0 { 667 pinmux { 668 pins = "gpio68"; 669 function = "qspi_cs"; 670 }; 671 }; 672 673 qspi_cs1: qspi-cs1 { 674 pinmux { 675 pins = "gpio72"; 676 function = "qspi_cs"; 677 }; 678 }; 679 680 qspi_data01: qspi-data01 { 681 pinmux-data { 682 pins = "gpio64", "gpio65"; 683 function = "qspi_data"; 684 }; 685 }; 686 687 qspi_data12: qspi-data12 { 688 pinmux-data { 689 pins = "gpio66", "gpio67"; 690 function = "qspi_data"; 691 }; 692 }; 693 694 qup_i2c0_default: qup-i2c0-default { 695 pinmux { 696 pins = "gpio34", "gpio35"; 697 function = "qup00"; 698 }; 699 }; 700 701 qup_i2c1_default: qup-i2c1-default { 702 pinmux { 703 pins = "gpio0", "gpio1"; 704 function = "qup01"; 705 }; 706 }; 707 708 qup_i2c2_default: qup-i2c2-default { 709 pinmux { 710 pins = "gpio15", "gpio16"; 711 function = "qup02_i2c"; 712 }; 713 }; 714 715 qup_i2c3_default: qup-i2c3-default { 716 pinmux { 717 pins = "gpio38", "gpio39"; 718 function = "qup03"; 719 }; 720 }; 721 722 qup_i2c4_default: qup-i2c4-default { 723 pinmux { 724 pins = "gpio115", "gpio116"; 725 function = "qup04_i2c"; 726 }; 727 }; 728 729 qup_i2c5_default: qup-i2c5-default { 730 pinmux { 731 pins = "gpio25", "gpio26"; 732 function = "qup05"; 733 }; 734 }; 735 736 qup_i2c6_default: qup-i2c6-default { 737 pinmux { 738 pins = "gpio59", "gpio60"; 739 function = "qup10"; 740 }; 741 }; 742 743 qup_i2c7_default: qup-i2c7-default { 744 pinmux { 745 pins = "gpio6", "gpio7"; 746 function = "qup11_i2c"; 747 }; 748 }; 749 750 qup_i2c8_default: qup-i2c8-default { 751 pinmux { 752 pins = "gpio42", "gpio43"; 753 function = "qup12"; 754 }; 755 }; 756 757 qup_i2c9_default: qup-i2c9-default { 758 pinmux { 759 pins = "gpio46", "gpio47"; 760 function = "qup13_i2c"; 761 }; 762 }; 763 764 qup_i2c10_default: qup-i2c10-default { 765 pinmux { 766 pins = "gpio86", "gpio87"; 767 function = "qup14"; 768 }; 769 }; 770 771 qup_i2c11_default: qup-i2c11-default { 772 pinmux { 773 pins = "gpio53", "gpio54"; 774 function = "qup15"; 775 }; 776 }; 777 778 qup_spi0_default: qup-spi0-default { 779 pinmux { 780 pins = "gpio34", "gpio35", 781 "gpio36", "gpio37"; 782 function = "qup00"; 783 }; 784 }; 785 786 qup_spi1_default: qup-spi1-default { 787 pinmux { 788 pins = "gpio0", "gpio1", 789 "gpio2", "gpio3"; 790 function = "qup01"; 791 }; 792 }; 793 794 qup_spi3_default: qup-spi3-default { 795 pinmux { 796 pins = "gpio38", "gpio39", 797 "gpio40", "gpio41"; 798 function = "qup03"; 799 }; 800 }; 801 802 qup_spi5_default: qup-spi5-default { 803 pinmux { 804 pins = "gpio25", "gpio26", 805 "gpio27", "gpio28"; 806 function = "qup05"; 807 }; 808 }; 809 810 qup_spi6_default: qup-spi6-default { 811 pinmux { 812 pins = "gpio59", "gpio60", 813 "gpio61", "gpio62"; 814 function = "qup10"; 815 }; 816 }; 817 818 qup_spi8_default: qup-spi8-default { 819 pinmux { 820 pins = "gpio42", "gpio43", 821 "gpio44", "gpio45"; 822 function = "qup12"; 823 }; 824 }; 825 826 qup_spi10_default: qup-spi10-default { 827 pinmux { 828 pins = "gpio86", "gpio87", 829 "gpio88", "gpio89"; 830 function = "qup14"; 831 }; 832 }; 833 834 qup_spi11_default: qup-spi11-default { 835 pinmux { 836 pins = "gpio53", "gpio54", 837 "gpio55", "gpio56"; 838 function = "qup15"; 839 }; 840 }; 841 842 qup_uart0_default: qup-uart0-default { 843 pinmux { 844 pins = "gpio34", "gpio35", 845 "gpio36", "gpio37"; 846 function = "qup00"; 847 }; 848 }; 849 850 qup_uart1_default: qup-uart1-default { 851 pinmux { 852 pins = "gpio0", "gpio1", 853 "gpio2", "gpio3"; 854 function = "qup01"; 855 }; 856 }; 857 858 qup_uart2_default: qup-uart2-default { 859 pinmux { 860 pins = "gpio15", "gpio16"; 861 function = "qup02_uart"; 862 }; 863 }; 864 865 qup_uart3_default: qup-uart3-default { 866 pinmux { 867 pins = "gpio38", "gpio39", 868 "gpio40", "gpio41"; 869 function = "qup03"; 870 }; 871 }; 872 873 qup_uart4_default: qup-uart4-default { 874 pinmux { 875 pins = "gpio115", "gpio116"; 876 function = "qup04_uart"; 877 }; 878 }; 879 880 qup_uart5_default: qup-uart5-default { 881 pinmux { 882 pins = "gpio25", "gpio26", 883 "gpio27", "gpio28"; 884 function = "qup05"; 885 }; 886 }; 887 888 qup_uart6_default: qup-uart6-default { 889 pinmux { 890 pins = "gpio59", "gpio60", 891 "gpio61", "gpio62"; 892 function = "qup10"; 893 }; 894 }; 895 896 qup_uart7_default: qup-uart7-default { 897 pinmux { 898 pins = "gpio6", "gpio7"; 899 function = "qup11_uart"; 900 }; 901 }; 902 903 qup_uart8_default: qup-uart8-default { 904 pinmux { 905 pins = "gpio44", "gpio45"; 906 function = "qup12"; 907 }; 908 }; 909 910 qup_uart9_default: qup-uart9-default { 911 pinmux { 912 pins = "gpio46", "gpio47"; 913 function = "qup13_uart"; 914 }; 915 }; 916 917 qup_uart10_default: qup-uart10-default { 918 pinmux { 919 pins = "gpio86", "gpio87", 920 "gpio88", "gpio89"; 921 function = "qup14"; 922 }; 923 }; 924 925 qup_uart11_default: qup-uart11-default { 926 pinmux { 927 pins = "gpio53", "gpio54", 928 "gpio55", "gpio56"; 929 function = "qup15"; 930 }; 931 }; 932 }; 933 934 qspi: spi@88dc000 { 935 compatible = "qcom,qspi-v1"; 936 reg = <0 0x088dc000 0 0x600>; 937 #address-cells = <1>; 938 #size-cells = <0>; 939 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 940 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, 941 <&gcc GCC_QSPI_CORE_CLK>; 942 clock-names = "iface", "core"; 943 status = "disabled"; 944 }; 945 946 usb_1_hsphy: phy@88e3000 { 947 compatible = "qcom,sc7180-qusb2-phy"; 948 reg = <0 0x088e3000 0 0x400>; 949 status = "disabled"; 950 #phy-cells = <0>; 951 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 952 <&rpmhcc RPMH_CXO_CLK>; 953 clock-names = "cfg_ahb", "ref"; 954 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 955 956 nvmem-cells = <&qusb2p_hstx_trim>; 957 }; 958 959 usb_1_qmpphy: phy-wrapper@88e9000 { 960 compatible = "qcom,sc7180-qmp-usb3-phy"; 961 reg = <0 0x088e9000 0 0x18c>, 962 <0 0x088e8000 0 0x38>; 963 reg-names = "reg-base", "dp_com"; 964 status = "disabled"; 965 #clock-cells = <1>; 966 #address-cells = <2>; 967 #size-cells = <2>; 968 ranges; 969 970 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 971 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 972 <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 973 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 974 clock-names = "aux", "cfg_ahb", "ref", "com_aux"; 975 976 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 977 <&gcc GCC_USB3_PHY_PRIM_BCR>; 978 reset-names = "phy", "common"; 979 980 usb_1_ssphy: phy@88e9200 { 981 reg = <0 0x088e9200 0 0x128>, 982 <0 0x088e9400 0 0x200>, 983 <0 0x088e9c00 0 0x218>, 984 <0 0x088e9600 0 0x128>, 985 <0 0x088e9800 0 0x200>, 986 <0 0x088e9a00 0 0x18>; 987 #clock-cells = <0>; 988 #phy-cells = <0>; 989 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 990 clock-names = "pipe0"; 991 clock-output-names = "usb3_phy_pipe_clk_src"; 992 }; 993 }; 994 995 system-cache-controller@9200000 { 996 compatible = "qcom,sc7180-llcc"; 997 reg = <0 0x09200000 0 0x200000>, <0 0x09600000 0 0x50000>; 998 reg-names = "llcc_base", "llcc_broadcast_base"; 999 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 1000 }; 1001 1002 usb_1: usb@a6f8800 { 1003 compatible = "qcom,sc7180-dwc3", "qcom,dwc3"; 1004 reg = <0 0x0a6f8800 0 0x400>; 1005 status = "disabled"; 1006 #address-cells = <2>; 1007 #size-cells = <2>; 1008 ranges; 1009 dma-ranges; 1010 1011 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 1012 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 1013 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 1014 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1015 <&gcc GCC_USB30_PRIM_SLEEP_CLK>; 1016 clock-names = "cfg_noc", "core", "iface", "mock_utmi", 1017 "sleep"; 1018 1019 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1020 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 1021 assigned-clock-rates = <19200000>, <150000000>; 1022 1023 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 1024 <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>, 1025 <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>, 1026 <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>; 1027 interrupt-names = "hs_phy_irq", "ss_phy_irq", 1028 "dm_hs_phy_irq", "dp_hs_phy_irq"; 1029 1030 power-domains = <&gcc USB30_PRIM_GDSC>; 1031 1032 resets = <&gcc GCC_USB30_PRIM_BCR>; 1033 1034 usb_1_dwc3: dwc3@a600000 { 1035 compatible = "snps,dwc3"; 1036 reg = <0 0x0a600000 0 0xe000>; 1037 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 1038 iommus = <&apps_smmu 0x540 0>; 1039 snps,dis_u2_susphy_quirk; 1040 snps,dis_enblslpm_quirk; 1041 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 1042 phy-names = "usb2-phy", "usb3-phy"; 1043 }; 1044 }; 1045 1046 pdc: interrupt-controller@b220000 { 1047 compatible = "qcom,sc7180-pdc", "qcom,pdc"; 1048 reg = <0 0x0b220000 0 0x30000>; 1049 qcom,pdc-ranges = <0 480 15>, <17 497 98>, 1050 <119 634 4>, <124 639 1>; 1051 #interrupt-cells = <2>; 1052 interrupt-parent = <&intc>; 1053 interrupt-controller; 1054 }; 1055 1056 tsens0: thermal-sensor@c263000 { 1057 compatible = "qcom,sc7180-tsens","qcom,tsens-v2"; 1058 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 1059 <0 0x0c222000 0 0x1ff>; /* SROT */ 1060 #qcom,sensors = <15>; 1061 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>; 1062 interrupt-names = "uplow"; 1063 #thermal-sensor-cells = <1>; 1064 }; 1065 1066 tsens1: thermal-sensor@c265000 { 1067 compatible = "qcom,sc7180-tsens","qcom,tsens-v2"; 1068 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 1069 <0 0x0c223000 0 0x1ff>; /* SROT */ 1070 #qcom,sensors = <10>; 1071 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>; 1072 interrupt-names = "uplow"; 1073 #thermal-sensor-cells = <1>; 1074 }; 1075 1076 spmi_bus: spmi@c440000 { 1077 compatible = "qcom,spmi-pmic-arb"; 1078 reg = <0 0x0c440000 0 0x1100>, 1079 <0 0x0c600000 0 0x2000000>, 1080 <0 0x0e600000 0 0x100000>, 1081 <0 0x0e700000 0 0xa0000>, 1082 <0 0x0c40a000 0 0x26000>; 1083 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 1084 interrupt-names = "periph_irq"; 1085 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 1086 qcom,ee = <0>; 1087 qcom,channel = <0>; 1088 #address-cells = <1>; 1089 #size-cells = <1>; 1090 interrupt-controller; 1091 #interrupt-cells = <4>; 1092 cell-index = <0>; 1093 }; 1094 1095 apps_smmu: iommu@15000000 { 1096 compatible = "qcom,sc7180-smmu-500", "arm,mmu-500"; 1097 reg = <0 0x15000000 0 0x100000>; 1098 #iommu-cells = <2>; 1099 #global-interrupts = <1>; 1100 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 1101 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 1102 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 1103 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 1104 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 1105 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 1106 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 1107 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 1108 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 1109 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 1110 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 1111 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 1112 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 1113 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 1114 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 1115 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 1116 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 1117 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 1118 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 1119 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 1120 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 1121 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 1122 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 1123 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1124 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 1125 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 1126 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 1127 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 1128 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 1129 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 1130 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 1131 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 1132 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 1133 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 1134 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 1135 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 1136 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 1137 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 1138 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 1139 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 1140 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 1141 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 1142 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 1143 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 1144 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 1145 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 1146 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 1147 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 1148 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 1149 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 1150 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 1151 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 1152 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 1153 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 1154 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 1155 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 1156 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 1157 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 1158 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 1159 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 1160 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 1161 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 1162 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 1163 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 1164 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 1165 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 1166 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 1167 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 1168 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 1169 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 1170 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 1171 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 1172 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 1173 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 1174 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 1175 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 1176 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 1177 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 1178 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, 1179 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>, 1180 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>; 1181 }; 1182 1183 intc: interrupt-controller@17a00000 { 1184 compatible = "arm,gic-v3"; 1185 #address-cells = <2>; 1186 #size-cells = <2>; 1187 ranges; 1188 #interrupt-cells = <3>; 1189 interrupt-controller; 1190 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 1191 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 1192 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 1193 1194 msi-controller@17a40000 { 1195 compatible = "arm,gic-v3-its"; 1196 msi-controller; 1197 #msi-cells = <1>; 1198 reg = <0 0x17a40000 0 0x20000>; 1199 status = "disabled"; 1200 }; 1201 }; 1202 1203 watchdog@17c10000 { 1204 compatible = "qcom,apss-wdt-sc7180", "qcom,kpss-wdt"; 1205 reg = <0 0x17c10000 0 0x1000>; 1206 clocks = <&sleep_clk>; 1207 }; 1208 1209 timer@17c20000{ 1210 #address-cells = <2>; 1211 #size-cells = <2>; 1212 ranges; 1213 compatible = "arm,armv7-timer-mem"; 1214 reg = <0 0x17c20000 0 0x1000>; 1215 1216 frame@17c21000 { 1217 frame-number = <0>; 1218 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 1219 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 1220 reg = <0 0x17c21000 0 0x1000>, 1221 <0 0x17c22000 0 0x1000>; 1222 }; 1223 1224 frame@17c23000 { 1225 frame-number = <1>; 1226 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 1227 reg = <0 0x17c23000 0 0x1000>; 1228 status = "disabled"; 1229 }; 1230 1231 frame@17c25000 { 1232 frame-number = <2>; 1233 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1234 reg = <0 0x17c25000 0 0x1000>; 1235 status = "disabled"; 1236 }; 1237 1238 frame@17c27000 { 1239 frame-number = <3>; 1240 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1241 reg = <0 0x17c27000 0 0x1000>; 1242 status = "disabled"; 1243 }; 1244 1245 frame@17c29000 { 1246 frame-number = <4>; 1247 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1248 reg = <0 0x17c29000 0 0x1000>; 1249 status = "disabled"; 1250 }; 1251 1252 frame@17c2b000 { 1253 frame-number = <5>; 1254 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1255 reg = <0 0x17c2b000 0 0x1000>; 1256 status = "disabled"; 1257 }; 1258 1259 frame@17c2d000 { 1260 frame-number = <6>; 1261 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1262 reg = <0 0x17c2d000 0 0x1000>; 1263 status = "disabled"; 1264 }; 1265 }; 1266 1267 apps_rsc: rsc@18200000 { 1268 compatible = "qcom,rpmh-rsc"; 1269 reg = <0 0x18200000 0 0x10000>, 1270 <0 0x18210000 0 0x10000>, 1271 <0 0x18220000 0 0x10000>; 1272 reg-names = "drv-0", "drv-1", "drv-2"; 1273 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 1274 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 1275 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 1276 qcom,tcs-offset = <0xd00>; 1277 qcom,drv-id = <2>; 1278 qcom,tcs-config = <ACTIVE_TCS 2>, 1279 <SLEEP_TCS 3>, 1280 <WAKE_TCS 3>, 1281 <CONTROL_TCS 1>; 1282 1283 rpmhcc: clock-controller { 1284 compatible = "qcom,sc7180-rpmh-clk"; 1285 clocks = <&xo_board>; 1286 clock-names = "xo"; 1287 #clock-cells = <1>; 1288 }; 1289 }; 1290 1291 cpufreq_hw: cpufreq@18323000 { 1292 compatible = "qcom,cpufreq-hw"; 1293 reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>; 1294 reg-names = "freq-domain0", "freq-domain1"; 1295 1296 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 1297 clock-names = "xo", "alternate"; 1298 1299 #freq-domain-cells = <1>; 1300 }; 1301 }; 1302 1303 thermal-zones { 1304 cpu0-thermal { 1305 polling-delay-passive = <250>; 1306 polling-delay = <1000>; 1307 1308 thermal-sensors = <&tsens0 1>; 1309 1310 trips { 1311 cpu0_alert0: trip-point0 { 1312 temperature = <90000>; 1313 hysteresis = <2000>; 1314 type = "passive"; 1315 }; 1316 1317 cpu0_alert1: trip-point1 { 1318 temperature = <95000>; 1319 hysteresis = <2000>; 1320 type = "passive"; 1321 }; 1322 1323 cpu0_crit: cpu_crit { 1324 temperature = <110000>; 1325 hysteresis = <1000>; 1326 type = "critical"; 1327 }; 1328 }; 1329 }; 1330 1331 cpu1-thermal { 1332 polling-delay-passive = <250>; 1333 polling-delay = <1000>; 1334 1335 thermal-sensors = <&tsens0 2>; 1336 1337 trips { 1338 cpu1_alert0: trip-point0 { 1339 temperature = <90000>; 1340 hysteresis = <2000>; 1341 type = "passive"; 1342 }; 1343 1344 cpu1_alert1: trip-point1 { 1345 temperature = <95000>; 1346 hysteresis = <2000>; 1347 type = "passive"; 1348 }; 1349 1350 cpu1_crit: cpu_crit { 1351 temperature = <110000>; 1352 hysteresis = <1000>; 1353 type = "critical"; 1354 }; 1355 }; 1356 }; 1357 1358 cpu2-thermal { 1359 polling-delay-passive = <250>; 1360 polling-delay = <1000>; 1361 1362 thermal-sensors = <&tsens0 3>; 1363 1364 trips { 1365 cpu2_alert0: trip-point0 { 1366 temperature = <90000>; 1367 hysteresis = <2000>; 1368 type = "passive"; 1369 }; 1370 1371 cpu2_alert1: trip-point1 { 1372 temperature = <95000>; 1373 hysteresis = <2000>; 1374 type = "passive"; 1375 }; 1376 1377 cpu2_crit: cpu_crit { 1378 temperature = <110000>; 1379 hysteresis = <1000>; 1380 type = "critical"; 1381 }; 1382 }; 1383 }; 1384 1385 cpu3-thermal { 1386 polling-delay-passive = <250>; 1387 polling-delay = <1000>; 1388 1389 thermal-sensors = <&tsens0 4>; 1390 1391 trips { 1392 cpu3_alert0: trip-point0 { 1393 temperature = <90000>; 1394 hysteresis = <2000>; 1395 type = "passive"; 1396 }; 1397 1398 cpu3_alert1: trip-point1 { 1399 temperature = <95000>; 1400 hysteresis = <2000>; 1401 type = "passive"; 1402 }; 1403 1404 cpu3_crit: cpu_crit { 1405 temperature = <110000>; 1406 hysteresis = <1000>; 1407 type = "critical"; 1408 }; 1409 }; 1410 }; 1411 1412 cpu4-thermal { 1413 polling-delay-passive = <250>; 1414 polling-delay = <1000>; 1415 1416 thermal-sensors = <&tsens0 5>; 1417 1418 trips { 1419 cpu4_alert0: trip-point0 { 1420 temperature = <90000>; 1421 hysteresis = <2000>; 1422 type = "passive"; 1423 }; 1424 1425 cpu4_alert1: trip-point1 { 1426 temperature = <95000>; 1427 hysteresis = <2000>; 1428 type = "passive"; 1429 }; 1430 1431 cpu4_crit: cpu_crit { 1432 temperature = <110000>; 1433 hysteresis = <1000>; 1434 type = "critical"; 1435 }; 1436 }; 1437 }; 1438 1439 cpu5-thermal { 1440 polling-delay-passive = <250>; 1441 polling-delay = <1000>; 1442 1443 thermal-sensors = <&tsens0 6>; 1444 1445 trips { 1446 cpu5_alert0: trip-point0 { 1447 temperature = <90000>; 1448 hysteresis = <2000>; 1449 type = "passive"; 1450 }; 1451 1452 cpu5_alert1: trip-point1 { 1453 temperature = <95000>; 1454 hysteresis = <2000>; 1455 type = "passive"; 1456 }; 1457 1458 cpu5_crit: cpu_crit { 1459 temperature = <110000>; 1460 hysteresis = <1000>; 1461 type = "critical"; 1462 }; 1463 }; 1464 }; 1465 1466 cpu6-thermal { 1467 polling-delay-passive = <250>; 1468 polling-delay = <1000>; 1469 1470 thermal-sensors = <&tsens0 9>; 1471 1472 trips { 1473 cpu6_alert0: trip-point0 { 1474 temperature = <90000>; 1475 hysteresis = <2000>; 1476 type = "passive"; 1477 }; 1478 1479 cpu6_alert1: trip-point1 { 1480 temperature = <95000>; 1481 hysteresis = <2000>; 1482 type = "passive"; 1483 }; 1484 1485 cpu6_crit: cpu_crit { 1486 temperature = <110000>; 1487 hysteresis = <1000>; 1488 type = "critical"; 1489 }; 1490 }; 1491 }; 1492 1493 cpu7-thermal { 1494 polling-delay-passive = <250>; 1495 polling-delay = <1000>; 1496 1497 thermal-sensors = <&tsens0 10>; 1498 1499 trips { 1500 cpu7_alert0: trip-point0 { 1501 temperature = <90000>; 1502 hysteresis = <2000>; 1503 type = "passive"; 1504 }; 1505 1506 cpu7_alert1: trip-point1 { 1507 temperature = <95000>; 1508 hysteresis = <2000>; 1509 type = "passive"; 1510 }; 1511 1512 cpu7_crit: cpu_crit { 1513 temperature = <110000>; 1514 hysteresis = <1000>; 1515 type = "critical"; 1516 }; 1517 }; 1518 }; 1519 1520 cpu8-thermal { 1521 polling-delay-passive = <250>; 1522 polling-delay = <1000>; 1523 1524 thermal-sensors = <&tsens0 11>; 1525 1526 trips { 1527 cpu8_alert0: trip-point0 { 1528 temperature = <90000>; 1529 hysteresis = <2000>; 1530 type = "passive"; 1531 }; 1532 1533 cpu8_alert1: trip-point1 { 1534 temperature = <95000>; 1535 hysteresis = <2000>; 1536 type = "passive"; 1537 }; 1538 1539 cpu8_crit: cpu_crit { 1540 temperature = <110000>; 1541 hysteresis = <1000>; 1542 type = "critical"; 1543 }; 1544 }; 1545 }; 1546 1547 cpu9-thermal { 1548 polling-delay-passive = <250>; 1549 polling-delay = <1000>; 1550 1551 thermal-sensors = <&tsens0 12>; 1552 1553 trips { 1554 cpu9_alert0: trip-point0 { 1555 temperature = <90000>; 1556 hysteresis = <2000>; 1557 type = "passive"; 1558 }; 1559 1560 cpu9_alert1: trip-point1 { 1561 temperature = <95000>; 1562 hysteresis = <2000>; 1563 type = "passive"; 1564 }; 1565 1566 cpu9_crit: cpu_crit { 1567 temperature = <110000>; 1568 hysteresis = <1000>; 1569 type = "critical"; 1570 }; 1571 }; 1572 }; 1573 1574 aoss0-thermal { 1575 polling-delay-passive = <250>; 1576 polling-delay = <1000>; 1577 1578 thermal-sensors = <&tsens0 0>; 1579 1580 trips { 1581 aoss0_alert0: trip-point0 { 1582 temperature = <90000>; 1583 hysteresis = <2000>; 1584 type = "hot"; 1585 }; 1586 }; 1587 }; 1588 1589 cpuss0-thermal { 1590 polling-delay-passive = <250>; 1591 polling-delay = <1000>; 1592 1593 thermal-sensors = <&tsens0 7>; 1594 1595 trips { 1596 cpuss0_alert0: trip-point0 { 1597 temperature = <90000>; 1598 hysteresis = <2000>; 1599 type = "hot"; 1600 }; 1601 cpuss0_crit: cluster0_crit { 1602 temperature = <110000>; 1603 hysteresis = <2000>; 1604 type = "critical"; 1605 }; 1606 }; 1607 }; 1608 1609 cpuss1-thermal { 1610 polling-delay-passive = <250>; 1611 polling-delay = <1000>; 1612 1613 thermal-sensors = <&tsens0 8>; 1614 1615 trips { 1616 cpuss1_alert0: trip-point0 { 1617 temperature = <90000>; 1618 hysteresis = <2000>; 1619 type = "hot"; 1620 }; 1621 cpuss1_crit: cluster0_crit { 1622 temperature = <110000>; 1623 hysteresis = <2000>; 1624 type = "critical"; 1625 }; 1626 }; 1627 }; 1628 1629 gpuss0-thermal { 1630 polling-delay-passive = <250>; 1631 polling-delay = <1000>; 1632 1633 thermal-sensors = <&tsens0 13>; 1634 1635 trips { 1636 gpuss0_alert0: trip-point0 { 1637 temperature = <90000>; 1638 hysteresis = <2000>; 1639 type = "hot"; 1640 }; 1641 }; 1642 }; 1643 1644 gpuss1-thermal { 1645 polling-delay-passive = <250>; 1646 polling-delay = <1000>; 1647 1648 thermal-sensors = <&tsens0 14>; 1649 1650 trips { 1651 gpuss1_alert0: trip-point0 { 1652 temperature = <90000>; 1653 hysteresis = <2000>; 1654 type = "hot"; 1655 }; 1656 }; 1657 }; 1658 1659 aoss1-thermal { 1660 polling-delay-passive = <250>; 1661 polling-delay = <1000>; 1662 1663 thermal-sensors = <&tsens1 0>; 1664 1665 trips { 1666 aoss1_alert0: trip-point0 { 1667 temperature = <90000>; 1668 hysteresis = <2000>; 1669 type = "hot"; 1670 }; 1671 }; 1672 }; 1673 1674 cwlan-thermal { 1675 polling-delay-passive = <250>; 1676 polling-delay = <1000>; 1677 1678 thermal-sensors = <&tsens1 1>; 1679 1680 trips { 1681 cwlan_alert0: trip-point0 { 1682 temperature = <90000>; 1683 hysteresis = <2000>; 1684 type = "hot"; 1685 }; 1686 }; 1687 }; 1688 1689 audio-thermal { 1690 polling-delay-passive = <250>; 1691 polling-delay = <1000>; 1692 1693 thermal-sensors = <&tsens1 2>; 1694 1695 trips { 1696 audio_alert0: trip-point0 { 1697 temperature = <90000>; 1698 hysteresis = <2000>; 1699 type = "hot"; 1700 }; 1701 }; 1702 }; 1703 1704 ddr-thermal { 1705 polling-delay-passive = <250>; 1706 polling-delay = <1000>; 1707 1708 thermal-sensors = <&tsens1 3>; 1709 1710 trips { 1711 ddr_alert0: trip-point0 { 1712 temperature = <90000>; 1713 hysteresis = <2000>; 1714 type = "hot"; 1715 }; 1716 }; 1717 }; 1718 1719 q6-hvx-thermal { 1720 polling-delay-passive = <250>; 1721 polling-delay = <1000>; 1722 1723 thermal-sensors = <&tsens1 4>; 1724 1725 trips { 1726 q6_hvx_alert0: trip-point0 { 1727 temperature = <90000>; 1728 hysteresis = <2000>; 1729 type = "hot"; 1730 }; 1731 }; 1732 }; 1733 1734 camera-thermal { 1735 polling-delay-passive = <250>; 1736 polling-delay = <1000>; 1737 1738 thermal-sensors = <&tsens1 5>; 1739 1740 trips { 1741 camera_alert0: trip-point0 { 1742 temperature = <90000>; 1743 hysteresis = <2000>; 1744 type = "hot"; 1745 }; 1746 }; 1747 }; 1748 1749 mdm-core-thermal { 1750 polling-delay-passive = <250>; 1751 polling-delay = <1000>; 1752 1753 thermal-sensors = <&tsens1 6>; 1754 1755 trips { 1756 mdm_alert0: trip-point0 { 1757 temperature = <90000>; 1758 hysteresis = <2000>; 1759 type = "hot"; 1760 }; 1761 }; 1762 }; 1763 1764 mdm-dsp-thermal { 1765 polling-delay-passive = <250>; 1766 polling-delay = <1000>; 1767 1768 thermal-sensors = <&tsens1 7>; 1769 1770 trips { 1771 mdm_dsp_alert0: trip-point0 { 1772 temperature = <90000>; 1773 hysteresis = <2000>; 1774 type = "hot"; 1775 }; 1776 }; 1777 }; 1778 1779 npu-thermal { 1780 polling-delay-passive = <250>; 1781 polling-delay = <1000>; 1782 1783 thermal-sensors = <&tsens1 8>; 1784 1785 trips { 1786 npu_alert0: trip-point0 { 1787 temperature = <90000>; 1788 hysteresis = <2000>; 1789 type = "hot"; 1790 }; 1791 }; 1792 }; 1793 1794 video-thermal { 1795 polling-delay-passive = <250>; 1796 polling-delay = <1000>; 1797 1798 thermal-sensors = <&tsens1 9>; 1799 1800 trips { 1801 video_alert0: trip-point0 { 1802 temperature = <90000>; 1803 hysteresis = <2000>; 1804 type = "hot"; 1805 }; 1806 }; 1807 }; 1808 }; 1809 1810 timer { 1811 compatible = "arm,armv8-timer"; 1812 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, 1813 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, 1814 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, 1815 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; 1816 }; 1817}; 1818