mt8195.dtsi (fd1c6f13cfc3db3b7bb4ab10d4599e9ed374cd53) mt8195.dtsi (7f2fc184a966c0bc46fd2e2b23d049d6bdf0e20b)
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (c) 2021 MediaTek Inc.
4 * Author: Seiya Wang <seiya.wang@mediatek.com>
5 */
6
7/dts-v1/;
8#include <dt-bindings/clock/mt8195-clk.h>
9#include <dt-bindings/gce/mt8195-gce.h>
10#include <dt-bindings/interrupt-controller/arm-gic.h>
11#include <dt-bindings/interrupt-controller/irq.h>
12#include <dt-bindings/memory/mt8195-memory-port.h>
13#include <dt-bindings/phy/phy.h>
14#include <dt-bindings/pinctrl/mt8195-pinfunc.h>
15#include <dt-bindings/power/mt8195-power.h>
16#include <dt-bindings/reset/mt8195-resets.h>
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (c) 2021 MediaTek Inc.
4 * Author: Seiya Wang <seiya.wang@mediatek.com>
5 */
6
7/dts-v1/;
8#include <dt-bindings/clock/mt8195-clk.h>
9#include <dt-bindings/gce/mt8195-gce.h>
10#include <dt-bindings/interrupt-controller/arm-gic.h>
11#include <dt-bindings/interrupt-controller/irq.h>
12#include <dt-bindings/memory/mt8195-memory-port.h>
13#include <dt-bindings/phy/phy.h>
14#include <dt-bindings/pinctrl/mt8195-pinfunc.h>
15#include <dt-bindings/power/mt8195-power.h>
16#include <dt-bindings/reset/mt8195-resets.h>
17#include <dt-bindings/thermal/thermal.h>
17#include <dt-bindings/thermal/mediatek,lvts-thermal.h>
18
19/ {
20 compatible = "mediatek,mt8195";
21 interrupt-parent = <&gic>;
22 #address-cells = <2>;
23 #size-cells = <2>;
24

--- 2972 unchanged lines hidden (view full) ---

2997 interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH 0>;
2998 max-linkrate-mhz = <8100>;
2999 status = "disabled";
3000 };
3001 };
3002
3003 thermal_zones: thermal-zones {
3004 cpu0-thermal {
18#include <dt-bindings/thermal/mediatek,lvts-thermal.h>
19
20/ {
21 compatible = "mediatek,mt8195";
22 interrupt-parent = <&gic>;
23 #address-cells = <2>;
24 #size-cells = <2>;
25

--- 2972 unchanged lines hidden (view full) ---

2998 interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH 0>;
2999 max-linkrate-mhz = <8100>;
3000 status = "disabled";
3001 };
3002 };
3003
3004 thermal_zones: thermal-zones {
3005 cpu0-thermal {
3005 polling-delay = <0>;
3006 polling-delay-passive = <0>;
3006 polling-delay = <1000>;
3007 polling-delay-passive = <250>;
3007 thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU0>;
3008 thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU0>;
3009
3008 trips {
3010 trips {
3011 cpu0_alert: trip-alert {
3012 temperature = <85000>;
3013 hysteresis = <2000>;
3014 type = "passive";
3015 };
3016
3009 cpu0_crit: trip-crit {
3010 temperature = <100000>;
3011 hysteresis = <2000>;
3012 type = "critical";
3013 };
3014 };
3017 cpu0_crit: trip-crit {
3018 temperature = <100000>;
3019 hysteresis = <2000>;
3020 type = "critical";
3021 };
3022 };
3023
3024 cooling-maps {
3025 map0 {
3026 trip = <&cpu0_alert>;
3027 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3028 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3029 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3030 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3031 };
3032 };
3015 };
3016
3017 cpu1-thermal {
3033 };
3034
3035 cpu1-thermal {
3018 polling-delay = <0>;
3019 polling-delay-passive = <0>;
3036 polling-delay = <1000>;
3037 polling-delay-passive = <250>;
3020 thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU1>;
3038 thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU1>;
3039
3021 trips {
3040 trips {
3041 cpu1_alert: trip-alert {
3042 temperature = <85000>;
3043 hysteresis = <2000>;
3044 type = "passive";
3045 };
3046
3022 cpu1_crit: trip-crit {
3023 temperature = <100000>;
3024 hysteresis = <2000>;
3025 type = "critical";
3026 };
3027 };
3047 cpu1_crit: trip-crit {
3048 temperature = <100000>;
3049 hysteresis = <2000>;
3050 type = "critical";
3051 };
3052 };
3053
3054 cooling-maps {
3055 map0 {
3056 trip = <&cpu1_alert>;
3057 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3058 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3059 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3060 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3061 };
3062 };
3028 };
3029
3030 cpu2-thermal {
3063 };
3064
3065 cpu2-thermal {
3031 polling-delay = <0>;
3032 polling-delay-passive = <0>;
3066 polling-delay = <1000>;
3067 polling-delay-passive = <250>;
3033 thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU2>;
3068 thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU2>;
3069
3034 trips {
3070 trips {
3071 cpu2_alert: trip-alert {
3072 temperature = <85000>;
3073 hysteresis = <2000>;
3074 type = "passive";
3075 };
3076
3035 cpu2_crit: trip-crit {
3036 temperature = <100000>;
3037 hysteresis = <2000>;
3038 type = "critical";
3039 };
3040 };
3077 cpu2_crit: trip-crit {
3078 temperature = <100000>;
3079 hysteresis = <2000>;
3080 type = "critical";
3081 };
3082 };
3083
3084 cooling-maps {
3085 map0 {
3086 trip = <&cpu2_alert>;
3087 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3088 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3089 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3090 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3091 };
3092 };
3041 };
3042
3043 cpu3-thermal {
3093 };
3094
3095 cpu3-thermal {
3044 polling-delay = <0>;
3045 polling-delay-passive = <0>;
3096 polling-delay = <1000>;
3097 polling-delay-passive = <250>;
3046 thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU3>;
3098 thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU3>;
3099
3047 trips {
3100 trips {
3101 cpu3_alert: trip-alert {
3102 temperature = <85000>;
3103 hysteresis = <2000>;
3104 type = "passive";
3105 };
3106
3048 cpu3_crit: trip-crit {
3049 temperature = <100000>;
3050 hysteresis = <2000>;
3051 type = "critical";
3052 };
3053 };
3107 cpu3_crit: trip-crit {
3108 temperature = <100000>;
3109 hysteresis = <2000>;
3110 type = "critical";
3111 };
3112 };
3113
3114 cooling-maps {
3115 map0 {
3116 trip = <&cpu3_alert>;
3117 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3118 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3119 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3120 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3121 };
3122 };
3054 };
3055
3056 cpu4-thermal {
3123 };
3124
3125 cpu4-thermal {
3057 polling-delay = <0>;
3058 polling-delay-passive = <0>;
3126 polling-delay = <1000>;
3127 polling-delay-passive = <250>;
3059 thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU0>;
3128 thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU0>;
3129
3060 trips {
3130 trips {
3131 cpu4_alert: trip-alert {
3132 temperature = <85000>;
3133 hysteresis = <2000>;
3134 type = "passive";
3135 };
3136
3061 cpu4_crit: trip-crit {
3062 temperature = <100000>;
3063 hysteresis = <2000>;
3064 type = "critical";
3065 };
3066 };
3137 cpu4_crit: trip-crit {
3138 temperature = <100000>;
3139 hysteresis = <2000>;
3140 type = "critical";
3141 };
3142 };
3143
3144 cooling-maps {
3145 map0 {
3146 trip = <&cpu4_alert>;
3147 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3148 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3149 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3150 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3151 };
3152 };
3067 };
3068
3069 cpu5-thermal {
3153 };
3154
3155 cpu5-thermal {
3070 polling-delay = <0>;
3071 polling-delay-passive = <0>;
3156 polling-delay = <1000>;
3157 polling-delay-passive = <250>;
3072 thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU1>;
3158 thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU1>;
3159
3073 trips {
3160 trips {
3161 cpu5_alert: trip-alert {
3162 temperature = <85000>;
3163 hysteresis = <2000>;
3164 type = "passive";
3165 };
3166
3074 cpu5_crit: trip-crit {
3075 temperature = <100000>;
3076 hysteresis = <2000>;
3077 type = "critical";
3078 };
3079 };
3167 cpu5_crit: trip-crit {
3168 temperature = <100000>;
3169 hysteresis = <2000>;
3170 type = "critical";
3171 };
3172 };
3173
3174 cooling-maps {
3175 map0 {
3176 trip = <&cpu5_alert>;
3177 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3178 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3179 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3180 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3181 };
3182 };
3080 };
3081
3082 cpu6-thermal {
3183 };
3184
3185 cpu6-thermal {
3083 polling-delay = <0>;
3084 polling-delay-passive = <0>;
3186 polling-delay = <1000>;
3187 polling-delay-passive = <250>;
3085 thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU2>;
3188 thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU2>;
3189
3086 trips {
3190 trips {
3191 cpu6_alert: trip-alert {
3192 temperature = <85000>;
3193 hysteresis = <2000>;
3194 type = "passive";
3195 };
3196
3087 cpu6_crit: trip-crit {
3088 temperature = <100000>;
3089 hysteresis = <2000>;
3090 type = "critical";
3091 };
3092 };
3197 cpu6_crit: trip-crit {
3198 temperature = <100000>;
3199 hysteresis = <2000>;
3200 type = "critical";
3201 };
3202 };
3203
3204 cooling-maps {
3205 map0 {
3206 trip = <&cpu6_alert>;
3207 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3208 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3209 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3210 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3211 };
3212 };
3093 };
3094
3095 cpu7-thermal {
3213 };
3214
3215 cpu7-thermal {
3096 polling-delay = <0>;
3097 polling-delay-passive = <0>;
3216 polling-delay = <1000>;
3217 polling-delay-passive = <250>;
3098 thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU3>;
3218 thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU3>;
3219
3099 trips {
3220 trips {
3221 cpu7_alert: trip-alert {
3222 temperature = <85000>;
3223 hysteresis = <2000>;
3224 type = "passive";
3225 };
3226
3100 cpu7_crit: trip-crit {
3101 temperature = <100000>;
3102 hysteresis = <2000>;
3103 type = "critical";
3104 };
3105 };
3227 cpu7_crit: trip-crit {
3228 temperature = <100000>;
3229 hysteresis = <2000>;
3230 type = "critical";
3231 };
3232 };
3233
3234 cooling-maps {
3235 map0 {
3236 trip = <&cpu7_alert>;
3237 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3238 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3239 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3240 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3241 };
3242 };
3106 };
3107 };
3108};
3243 };
3244 };
3245};