1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (c) 2021 MediaTek Inc. 4 * Author: Seiya Wang <seiya.wang@mediatek.com> 5 */ 6 7/dts-v1/; 8#include <dt-bindings/clock/mt8195-clk.h> 9#include <dt-bindings/gce/mt8195-gce.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/interrupt-controller/irq.h> 12#include <dt-bindings/memory/mt8195-memory-port.h> 13#include <dt-bindings/phy/phy.h> 14#include <dt-bindings/pinctrl/mt8195-pinfunc.h> 15#include <dt-bindings/power/mt8195-power.h> 16#include <dt-bindings/reset/mt8195-resets.h> 17#include <dt-bindings/thermal/mediatek,lvts-thermal.h> 18 19/ { 20 compatible = "mediatek,mt8195"; 21 interrupt-parent = <&gic>; 22 #address-cells = <2>; 23 #size-cells = <2>; 24 25 aliases { 26 gce0 = &gce0; 27 gce1 = &gce1; 28 ethdr0 = ðdr0; 29 mutex0 = &mutex; 30 mutex1 = &mutex1; 31 merge1 = &merge1; 32 merge2 = &merge2; 33 merge3 = &merge3; 34 merge4 = &merge4; 35 merge5 = &merge5; 36 vdo1-rdma0 = &vdo1_rdma0; 37 vdo1-rdma1 = &vdo1_rdma1; 38 vdo1-rdma2 = &vdo1_rdma2; 39 vdo1-rdma3 = &vdo1_rdma3; 40 vdo1-rdma4 = &vdo1_rdma4; 41 vdo1-rdma5 = &vdo1_rdma5; 42 vdo1-rdma6 = &vdo1_rdma6; 43 vdo1-rdma7 = &vdo1_rdma7; 44 }; 45 46 cpus { 47 #address-cells = <1>; 48 #size-cells = <0>; 49 50 cpu0: cpu@0 { 51 device_type = "cpu"; 52 compatible = "arm,cortex-a55"; 53 reg = <0x000>; 54 enable-method = "psci"; 55 performance-domains = <&performance 0>; 56 clock-frequency = <1701000000>; 57 capacity-dmips-mhz = <308>; 58 cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 59 i-cache-size = <32768>; 60 i-cache-line-size = <64>; 61 i-cache-sets = <128>; 62 d-cache-size = <32768>; 63 d-cache-line-size = <64>; 64 d-cache-sets = <128>; 65 next-level-cache = <&l2_0>; 66 #cooling-cells = <2>; 67 }; 68 69 cpu1: cpu@100 { 70 device_type = "cpu"; 71 compatible = "arm,cortex-a55"; 72 reg = <0x100>; 73 enable-method = "psci"; 74 performance-domains = <&performance 0>; 75 clock-frequency = <1701000000>; 76 capacity-dmips-mhz = <308>; 77 cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 78 i-cache-size = <32768>; 79 i-cache-line-size = <64>; 80 i-cache-sets = <128>; 81 d-cache-size = <32768>; 82 d-cache-line-size = <64>; 83 d-cache-sets = <128>; 84 next-level-cache = <&l2_0>; 85 #cooling-cells = <2>; 86 }; 87 88 cpu2: cpu@200 { 89 device_type = "cpu"; 90 compatible = "arm,cortex-a55"; 91 reg = <0x200>; 92 enable-method = "psci"; 93 performance-domains = <&performance 0>; 94 clock-frequency = <1701000000>; 95 capacity-dmips-mhz = <308>; 96 cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 97 i-cache-size = <32768>; 98 i-cache-line-size = <64>; 99 i-cache-sets = <128>; 100 d-cache-size = <32768>; 101 d-cache-line-size = <64>; 102 d-cache-sets = <128>; 103 next-level-cache = <&l2_0>; 104 #cooling-cells = <2>; 105 }; 106 107 cpu3: cpu@300 { 108 device_type = "cpu"; 109 compatible = "arm,cortex-a55"; 110 reg = <0x300>; 111 enable-method = "psci"; 112 performance-domains = <&performance 0>; 113 clock-frequency = <1701000000>; 114 capacity-dmips-mhz = <308>; 115 cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 116 i-cache-size = <32768>; 117 i-cache-line-size = <64>; 118 i-cache-sets = <128>; 119 d-cache-size = <32768>; 120 d-cache-line-size = <64>; 121 d-cache-sets = <128>; 122 next-level-cache = <&l2_0>; 123 #cooling-cells = <2>; 124 }; 125 126 cpu4: cpu@400 { 127 device_type = "cpu"; 128 compatible = "arm,cortex-a78"; 129 reg = <0x400>; 130 enable-method = "psci"; 131 performance-domains = <&performance 1>; 132 clock-frequency = <2171000000>; 133 capacity-dmips-mhz = <1024>; 134 cpu-idle-states = <&cpu_ret_b &cpu_off_b>; 135 i-cache-size = <65536>; 136 i-cache-line-size = <64>; 137 i-cache-sets = <256>; 138 d-cache-size = <65536>; 139 d-cache-line-size = <64>; 140 d-cache-sets = <256>; 141 next-level-cache = <&l2_1>; 142 #cooling-cells = <2>; 143 }; 144 145 cpu5: cpu@500 { 146 device_type = "cpu"; 147 compatible = "arm,cortex-a78"; 148 reg = <0x500>; 149 enable-method = "psci"; 150 performance-domains = <&performance 1>; 151 clock-frequency = <2171000000>; 152 capacity-dmips-mhz = <1024>; 153 cpu-idle-states = <&cpu_ret_b &cpu_off_b>; 154 i-cache-size = <65536>; 155 i-cache-line-size = <64>; 156 i-cache-sets = <256>; 157 d-cache-size = <65536>; 158 d-cache-line-size = <64>; 159 d-cache-sets = <256>; 160 next-level-cache = <&l2_1>; 161 #cooling-cells = <2>; 162 }; 163 164 cpu6: cpu@600 { 165 device_type = "cpu"; 166 compatible = "arm,cortex-a78"; 167 reg = <0x600>; 168 enable-method = "psci"; 169 performance-domains = <&performance 1>; 170 clock-frequency = <2171000000>; 171 capacity-dmips-mhz = <1024>; 172 cpu-idle-states = <&cpu_ret_b &cpu_off_b>; 173 i-cache-size = <65536>; 174 i-cache-line-size = <64>; 175 i-cache-sets = <256>; 176 d-cache-size = <65536>; 177 d-cache-line-size = <64>; 178 d-cache-sets = <256>; 179 next-level-cache = <&l2_1>; 180 #cooling-cells = <2>; 181 }; 182 183 cpu7: cpu@700 { 184 device_type = "cpu"; 185 compatible = "arm,cortex-a78"; 186 reg = <0x700>; 187 enable-method = "psci"; 188 performance-domains = <&performance 1>; 189 clock-frequency = <2171000000>; 190 capacity-dmips-mhz = <1024>; 191 cpu-idle-states = <&cpu_ret_b &cpu_off_b>; 192 i-cache-size = <65536>; 193 i-cache-line-size = <64>; 194 i-cache-sets = <256>; 195 d-cache-size = <65536>; 196 d-cache-line-size = <64>; 197 d-cache-sets = <256>; 198 next-level-cache = <&l2_1>; 199 #cooling-cells = <2>; 200 }; 201 202 cpu-map { 203 cluster0 { 204 core0 { 205 cpu = <&cpu0>; 206 }; 207 208 core1 { 209 cpu = <&cpu1>; 210 }; 211 212 core2 { 213 cpu = <&cpu2>; 214 }; 215 216 core3 { 217 cpu = <&cpu3>; 218 }; 219 220 core4 { 221 cpu = <&cpu4>; 222 }; 223 224 core5 { 225 cpu = <&cpu5>; 226 }; 227 228 core6 { 229 cpu = <&cpu6>; 230 }; 231 232 core7 { 233 cpu = <&cpu7>; 234 }; 235 }; 236 }; 237 238 idle-states { 239 entry-method = "psci"; 240 241 cpu_ret_l: cpu-retention-l { 242 compatible = "arm,idle-state"; 243 arm,psci-suspend-param = <0x00010001>; 244 local-timer-stop; 245 entry-latency-us = <50>; 246 exit-latency-us = <95>; 247 min-residency-us = <580>; 248 }; 249 250 cpu_ret_b: cpu-retention-b { 251 compatible = "arm,idle-state"; 252 arm,psci-suspend-param = <0x00010001>; 253 local-timer-stop; 254 entry-latency-us = <45>; 255 exit-latency-us = <140>; 256 min-residency-us = <740>; 257 }; 258 259 cpu_off_l: cpu-off-l { 260 compatible = "arm,idle-state"; 261 arm,psci-suspend-param = <0x01010002>; 262 local-timer-stop; 263 entry-latency-us = <55>; 264 exit-latency-us = <155>; 265 min-residency-us = <840>; 266 }; 267 268 cpu_off_b: cpu-off-b { 269 compatible = "arm,idle-state"; 270 arm,psci-suspend-param = <0x01010002>; 271 local-timer-stop; 272 entry-latency-us = <50>; 273 exit-latency-us = <200>; 274 min-residency-us = <1000>; 275 }; 276 }; 277 278 l2_0: l2-cache0 { 279 compatible = "cache"; 280 cache-level = <2>; 281 cache-size = <131072>; 282 cache-line-size = <64>; 283 cache-sets = <512>; 284 next-level-cache = <&l3_0>; 285 }; 286 287 l2_1: l2-cache1 { 288 compatible = "cache"; 289 cache-level = <2>; 290 cache-size = <262144>; 291 cache-line-size = <64>; 292 cache-sets = <512>; 293 next-level-cache = <&l3_0>; 294 }; 295 296 l3_0: l3-cache { 297 compatible = "cache"; 298 cache-level = <3>; 299 cache-size = <2097152>; 300 cache-line-size = <64>; 301 cache-sets = <2048>; 302 cache-unified; 303 }; 304 }; 305 306 dsu-pmu { 307 compatible = "arm,dsu-pmu"; 308 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>; 309 cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>, 310 <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>; 311 }; 312 313 dmic_codec: dmic-codec { 314 compatible = "dmic-codec"; 315 num-channels = <2>; 316 wakeup-delay-ms = <50>; 317 }; 318 319 sound: mt8195-sound { 320 mediatek,platform = <&afe>; 321 status = "disabled"; 322 }; 323 324 clk13m: fixed-factor-clock-13m { 325 compatible = "fixed-factor-clock"; 326 #clock-cells = <0>; 327 clocks = <&clk26m>; 328 clock-div = <2>; 329 clock-mult = <1>; 330 clock-output-names = "clk13m"; 331 }; 332 333 clk26m: oscillator-26m { 334 compatible = "fixed-clock"; 335 #clock-cells = <0>; 336 clock-frequency = <26000000>; 337 clock-output-names = "clk26m"; 338 }; 339 340 clk32k: oscillator-32k { 341 compatible = "fixed-clock"; 342 #clock-cells = <0>; 343 clock-frequency = <32768>; 344 clock-output-names = "clk32k"; 345 }; 346 347 performance: performance-controller@11bc10 { 348 compatible = "mediatek,cpufreq-hw"; 349 reg = <0 0x0011bc10 0 0x120>, <0 0x0011bd30 0 0x120>; 350 #performance-domain-cells = <1>; 351 }; 352 353 gpu_opp_table: opp-table-gpu { 354 compatible = "operating-points-v2"; 355 opp-shared; 356 357 opp-390000000 { 358 opp-hz = /bits/ 64 <390000000>; 359 opp-microvolt = <625000>; 360 }; 361 opp-410000000 { 362 opp-hz = /bits/ 64 <410000000>; 363 opp-microvolt = <631250>; 364 }; 365 opp-431000000 { 366 opp-hz = /bits/ 64 <431000000>; 367 opp-microvolt = <631250>; 368 }; 369 opp-473000000 { 370 opp-hz = /bits/ 64 <473000000>; 371 opp-microvolt = <637500>; 372 }; 373 opp-515000000 { 374 opp-hz = /bits/ 64 <515000000>; 375 opp-microvolt = <637500>; 376 }; 377 opp-556000000 { 378 opp-hz = /bits/ 64 <556000000>; 379 opp-microvolt = <643750>; 380 }; 381 opp-598000000 { 382 opp-hz = /bits/ 64 <598000000>; 383 opp-microvolt = <650000>; 384 }; 385 opp-640000000 { 386 opp-hz = /bits/ 64 <640000000>; 387 opp-microvolt = <650000>; 388 }; 389 opp-670000000 { 390 opp-hz = /bits/ 64 <670000000>; 391 opp-microvolt = <662500>; 392 }; 393 opp-700000000 { 394 opp-hz = /bits/ 64 <700000000>; 395 opp-microvolt = <675000>; 396 }; 397 opp-730000000 { 398 opp-hz = /bits/ 64 <730000000>; 399 opp-microvolt = <687500>; 400 }; 401 opp-760000000 { 402 opp-hz = /bits/ 64 <760000000>; 403 opp-microvolt = <700000>; 404 }; 405 opp-790000000 { 406 opp-hz = /bits/ 64 <790000000>; 407 opp-microvolt = <712500>; 408 }; 409 opp-820000000 { 410 opp-hz = /bits/ 64 <820000000>; 411 opp-microvolt = <725000>; 412 }; 413 opp-850000000 { 414 opp-hz = /bits/ 64 <850000000>; 415 opp-microvolt = <737500>; 416 }; 417 opp-880000000 { 418 opp-hz = /bits/ 64 <880000000>; 419 opp-microvolt = <750000>; 420 }; 421 }; 422 423 pmu-a55 { 424 compatible = "arm,cortex-a55-pmu"; 425 interrupt-parent = <&gic>; 426 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>; 427 }; 428 429 pmu-a78 { 430 compatible = "arm,cortex-a78-pmu"; 431 interrupt-parent = <&gic>; 432 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>; 433 }; 434 435 psci { 436 compatible = "arm,psci-1.0"; 437 method = "smc"; 438 }; 439 440 timer: timer { 441 compatible = "arm,armv8-timer"; 442 interrupt-parent = <&gic>; 443 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>, 444 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>, 445 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>, 446 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>; 447 }; 448 449 soc { 450 #address-cells = <2>; 451 #size-cells = <2>; 452 compatible = "simple-bus"; 453 ranges; 454 455 gic: interrupt-controller@c000000 { 456 compatible = "arm,gic-v3"; 457 #interrupt-cells = <4>; 458 #redistributor-regions = <1>; 459 interrupt-parent = <&gic>; 460 interrupt-controller; 461 reg = <0 0x0c000000 0 0x40000>, 462 <0 0x0c040000 0 0x200000>; 463 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 464 465 ppi-partitions { 466 ppi_cluster0: interrupt-partition-0 { 467 affinity = <&cpu0 &cpu1 &cpu2 &cpu3>; 468 }; 469 470 ppi_cluster1: interrupt-partition-1 { 471 affinity = <&cpu4 &cpu5 &cpu6 &cpu7>; 472 }; 473 }; 474 }; 475 476 topckgen: syscon@10000000 { 477 compatible = "mediatek,mt8195-topckgen", "syscon"; 478 reg = <0 0x10000000 0 0x1000>; 479 #clock-cells = <1>; 480 }; 481 482 infracfg_ao: syscon@10001000 { 483 compatible = "mediatek,mt8195-infracfg_ao", "syscon", "simple-mfd"; 484 reg = <0 0x10001000 0 0x1000>; 485 #clock-cells = <1>; 486 #reset-cells = <1>; 487 }; 488 489 pericfg: syscon@10003000 { 490 compatible = "mediatek,mt8195-pericfg", "syscon"; 491 reg = <0 0x10003000 0 0x1000>; 492 #clock-cells = <1>; 493 }; 494 495 pio: pinctrl@10005000 { 496 compatible = "mediatek,mt8195-pinctrl"; 497 reg = <0 0x10005000 0 0x1000>, 498 <0 0x11d10000 0 0x1000>, 499 <0 0x11d30000 0 0x1000>, 500 <0 0x11d40000 0 0x1000>, 501 <0 0x11e20000 0 0x1000>, 502 <0 0x11eb0000 0 0x1000>, 503 <0 0x11f40000 0 0x1000>, 504 <0 0x1000b000 0 0x1000>; 505 reg-names = "iocfg0", "iocfg_bm", "iocfg_bl", 506 "iocfg_br", "iocfg_lm", "iocfg_rb", 507 "iocfg_tl", "eint"; 508 gpio-controller; 509 #gpio-cells = <2>; 510 gpio-ranges = <&pio 0 0 144>; 511 interrupt-controller; 512 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH 0>; 513 #interrupt-cells = <2>; 514 }; 515 516 scpsys: syscon@10006000 { 517 compatible = "mediatek,mt8195-scpsys", "syscon", "simple-mfd"; 518 reg = <0 0x10006000 0 0x1000>; 519 520 /* System Power Manager */ 521 spm: power-controller { 522 compatible = "mediatek,mt8195-power-controller"; 523 #address-cells = <1>; 524 #size-cells = <0>; 525 #power-domain-cells = <1>; 526 527 /* power domain of the SoC */ 528 mfg0: power-domain@MT8195_POWER_DOMAIN_MFG0 { 529 reg = <MT8195_POWER_DOMAIN_MFG0>; 530 #address-cells = <1>; 531 #size-cells = <0>; 532 #power-domain-cells = <1>; 533 534 power-domain@MT8195_POWER_DOMAIN_MFG1 { 535 reg = <MT8195_POWER_DOMAIN_MFG1>; 536 clocks = <&apmixedsys CLK_APMIXED_MFGPLL>, 537 <&topckgen CLK_TOP_MFG_CORE_TMP>; 538 clock-names = "mfg", "alt"; 539 mediatek,infracfg = <&infracfg_ao>; 540 #address-cells = <1>; 541 #size-cells = <0>; 542 #power-domain-cells = <1>; 543 544 power-domain@MT8195_POWER_DOMAIN_MFG2 { 545 reg = <MT8195_POWER_DOMAIN_MFG2>; 546 #power-domain-cells = <0>; 547 }; 548 549 power-domain@MT8195_POWER_DOMAIN_MFG3 { 550 reg = <MT8195_POWER_DOMAIN_MFG3>; 551 #power-domain-cells = <0>; 552 }; 553 554 power-domain@MT8195_POWER_DOMAIN_MFG4 { 555 reg = <MT8195_POWER_DOMAIN_MFG4>; 556 #power-domain-cells = <0>; 557 }; 558 559 power-domain@MT8195_POWER_DOMAIN_MFG5 { 560 reg = <MT8195_POWER_DOMAIN_MFG5>; 561 #power-domain-cells = <0>; 562 }; 563 564 power-domain@MT8195_POWER_DOMAIN_MFG6 { 565 reg = <MT8195_POWER_DOMAIN_MFG6>; 566 #power-domain-cells = <0>; 567 }; 568 }; 569 }; 570 571 power-domain@MT8195_POWER_DOMAIN_VPPSYS0 { 572 reg = <MT8195_POWER_DOMAIN_VPPSYS0>; 573 clocks = <&topckgen CLK_TOP_VPP>, 574 <&topckgen CLK_TOP_CAM>, 575 <&topckgen CLK_TOP_CCU>, 576 <&topckgen CLK_TOP_IMG>, 577 <&topckgen CLK_TOP_VENC>, 578 <&topckgen CLK_TOP_VDEC>, 579 <&topckgen CLK_TOP_WPE_VPP>, 580 <&topckgen CLK_TOP_CFG_VPP0>, 581 <&vppsys0 CLK_VPP0_SMI_COMMON>, 582 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB0>, 583 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB1>, 584 <&vppsys0 CLK_VPP0_GALS_VENCSYS>, 585 <&vppsys0 CLK_VPP0_GALS_VENCSYS_CORE1>, 586 <&vppsys0 CLK_VPP0_GALS_INFRA>, 587 <&vppsys0 CLK_VPP0_GALS_CAMSYS>, 588 <&vppsys0 CLK_VPP0_GALS_VPP1_LARB5>, 589 <&vppsys0 CLK_VPP0_GALS_VPP1_LARB6>, 590 <&vppsys0 CLK_VPP0_SMI_REORDER>, 591 <&vppsys0 CLK_VPP0_SMI_IOMMU>, 592 <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>, 593 <&vppsys0 CLK_VPP0_GALS_EMI0_EMI1>, 594 <&vppsys0 CLK_VPP0_SMI_SUB_COMMON_REORDER>, 595 <&vppsys0 CLK_VPP0_SMI_RSI>, 596 <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>, 597 <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>, 598 <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>, 599 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>; 600 clock-names = "vppsys", "vppsys1", "vppsys2", "vppsys3", 601 "vppsys4", "vppsys5", "vppsys6", "vppsys7", 602 "vppsys0-0", "vppsys0-1", "vppsys0-2", "vppsys0-3", 603 "vppsys0-4", "vppsys0-5", "vppsys0-6", "vppsys0-7", 604 "vppsys0-8", "vppsys0-9", "vppsys0-10", "vppsys0-11", 605 "vppsys0-12", "vppsys0-13", "vppsys0-14", 606 "vppsys0-15", "vppsys0-16", "vppsys0-17", 607 "vppsys0-18"; 608 mediatek,infracfg = <&infracfg_ao>; 609 #address-cells = <1>; 610 #size-cells = <0>; 611 #power-domain-cells = <1>; 612 613 power-domain@MT8195_POWER_DOMAIN_VDEC1 { 614 reg = <MT8195_POWER_DOMAIN_VDEC1>; 615 clocks = <&vdecsys CLK_VDEC_LARB1>; 616 clock-names = "vdec1-0"; 617 mediatek,infracfg = <&infracfg_ao>; 618 #power-domain-cells = <0>; 619 }; 620 621 power-domain@MT8195_POWER_DOMAIN_VENC_CORE1 { 622 reg = <MT8195_POWER_DOMAIN_VENC_CORE1>; 623 mediatek,infracfg = <&infracfg_ao>; 624 #power-domain-cells = <0>; 625 }; 626 627 power-domain@MT8195_POWER_DOMAIN_VDOSYS0 { 628 reg = <MT8195_POWER_DOMAIN_VDOSYS0>; 629 clocks = <&topckgen CLK_TOP_CFG_VDO0>, 630 <&vdosys0 CLK_VDO0_SMI_GALS>, 631 <&vdosys0 CLK_VDO0_SMI_COMMON>, 632 <&vdosys0 CLK_VDO0_SMI_EMI>, 633 <&vdosys0 CLK_VDO0_SMI_IOMMU>, 634 <&vdosys0 CLK_VDO0_SMI_LARB>, 635 <&vdosys0 CLK_VDO0_SMI_RSI>; 636 clock-names = "vdosys0", "vdosys0-0", "vdosys0-1", 637 "vdosys0-2", "vdosys0-3", 638 "vdosys0-4", "vdosys0-5"; 639 mediatek,infracfg = <&infracfg_ao>; 640 #address-cells = <1>; 641 #size-cells = <0>; 642 #power-domain-cells = <1>; 643 644 power-domain@MT8195_POWER_DOMAIN_VPPSYS1 { 645 reg = <MT8195_POWER_DOMAIN_VPPSYS1>; 646 clocks = <&topckgen CLK_TOP_CFG_VPP1>, 647 <&vppsys1 CLK_VPP1_VPPSYS1_GALS>, 648 <&vppsys1 CLK_VPP1_VPPSYS1_LARB>; 649 clock-names = "vppsys1", "vppsys1-0", 650 "vppsys1-1"; 651 mediatek,infracfg = <&infracfg_ao>; 652 #power-domain-cells = <0>; 653 }; 654 655 power-domain@MT8195_POWER_DOMAIN_WPESYS { 656 reg = <MT8195_POWER_DOMAIN_WPESYS>; 657 clocks = <&wpesys CLK_WPE_SMI_LARB7>, 658 <&wpesys CLK_WPE_SMI_LARB8>, 659 <&wpesys CLK_WPE_SMI_LARB7_P>, 660 <&wpesys CLK_WPE_SMI_LARB8_P>; 661 clock-names = "wepsys-0", "wepsys-1", "wepsys-2", 662 "wepsys-3"; 663 mediatek,infracfg = <&infracfg_ao>; 664 #power-domain-cells = <0>; 665 }; 666 667 power-domain@MT8195_POWER_DOMAIN_VDEC0 { 668 reg = <MT8195_POWER_DOMAIN_VDEC0>; 669 clocks = <&vdecsys_soc CLK_VDEC_SOC_LARB1>; 670 clock-names = "vdec0-0"; 671 mediatek,infracfg = <&infracfg_ao>; 672 #power-domain-cells = <0>; 673 }; 674 675 power-domain@MT8195_POWER_DOMAIN_VDEC2 { 676 reg = <MT8195_POWER_DOMAIN_VDEC2>; 677 clocks = <&vdecsys_core1 CLK_VDEC_CORE1_LARB1>; 678 clock-names = "vdec2-0"; 679 mediatek,infracfg = <&infracfg_ao>; 680 #power-domain-cells = <0>; 681 }; 682 683 power-domain@MT8195_POWER_DOMAIN_VENC { 684 reg = <MT8195_POWER_DOMAIN_VENC>; 685 mediatek,infracfg = <&infracfg_ao>; 686 #power-domain-cells = <0>; 687 }; 688 689 power-domain@MT8195_POWER_DOMAIN_VDOSYS1 { 690 reg = <MT8195_POWER_DOMAIN_VDOSYS1>; 691 clocks = <&topckgen CLK_TOP_CFG_VDO1>, 692 <&vdosys1 CLK_VDO1_SMI_LARB2>, 693 <&vdosys1 CLK_VDO1_SMI_LARB3>, 694 <&vdosys1 CLK_VDO1_GALS>; 695 clock-names = "vdosys1", "vdosys1-0", 696 "vdosys1-1", "vdosys1-2"; 697 mediatek,infracfg = <&infracfg_ao>; 698 #address-cells = <1>; 699 #size-cells = <0>; 700 #power-domain-cells = <1>; 701 702 power-domain@MT8195_POWER_DOMAIN_DP_TX { 703 reg = <MT8195_POWER_DOMAIN_DP_TX>; 704 mediatek,infracfg = <&infracfg_ao>; 705 #power-domain-cells = <0>; 706 }; 707 708 power-domain@MT8195_POWER_DOMAIN_EPD_TX { 709 reg = <MT8195_POWER_DOMAIN_EPD_TX>; 710 mediatek,infracfg = <&infracfg_ao>; 711 #power-domain-cells = <0>; 712 }; 713 714 power-domain@MT8195_POWER_DOMAIN_HDMI_TX { 715 reg = <MT8195_POWER_DOMAIN_HDMI_TX>; 716 clocks = <&topckgen CLK_TOP_HDMI_APB>; 717 clock-names = "hdmi_tx"; 718 #power-domain-cells = <0>; 719 }; 720 }; 721 722 power-domain@MT8195_POWER_DOMAIN_IMG { 723 reg = <MT8195_POWER_DOMAIN_IMG>; 724 clocks = <&imgsys CLK_IMG_LARB9>, 725 <&imgsys CLK_IMG_GALS>; 726 clock-names = "img-0", "img-1"; 727 mediatek,infracfg = <&infracfg_ao>; 728 #address-cells = <1>; 729 #size-cells = <0>; 730 #power-domain-cells = <1>; 731 732 power-domain@MT8195_POWER_DOMAIN_DIP { 733 reg = <MT8195_POWER_DOMAIN_DIP>; 734 #power-domain-cells = <0>; 735 }; 736 737 power-domain@MT8195_POWER_DOMAIN_IPE { 738 reg = <MT8195_POWER_DOMAIN_IPE>; 739 clocks = <&topckgen CLK_TOP_IPE>, 740 <&imgsys CLK_IMG_IPE>, 741 <&ipesys CLK_IPE_SMI_LARB12>; 742 clock-names = "ipe", "ipe-0", "ipe-1"; 743 mediatek,infracfg = <&infracfg_ao>; 744 #power-domain-cells = <0>; 745 }; 746 }; 747 748 power-domain@MT8195_POWER_DOMAIN_CAM { 749 reg = <MT8195_POWER_DOMAIN_CAM>; 750 clocks = <&camsys CLK_CAM_LARB13>, 751 <&camsys CLK_CAM_LARB14>, 752 <&camsys CLK_CAM_CAM2MM0_GALS>, 753 <&camsys CLK_CAM_CAM2MM1_GALS>, 754 <&camsys CLK_CAM_CAM2SYS_GALS>; 755 clock-names = "cam-0", "cam-1", "cam-2", "cam-3", 756 "cam-4"; 757 mediatek,infracfg = <&infracfg_ao>; 758 #address-cells = <1>; 759 #size-cells = <0>; 760 #power-domain-cells = <1>; 761 762 power-domain@MT8195_POWER_DOMAIN_CAM_RAWA { 763 reg = <MT8195_POWER_DOMAIN_CAM_RAWA>; 764 #power-domain-cells = <0>; 765 }; 766 767 power-domain@MT8195_POWER_DOMAIN_CAM_RAWB { 768 reg = <MT8195_POWER_DOMAIN_CAM_RAWB>; 769 #power-domain-cells = <0>; 770 }; 771 772 power-domain@MT8195_POWER_DOMAIN_CAM_MRAW { 773 reg = <MT8195_POWER_DOMAIN_CAM_MRAW>; 774 #power-domain-cells = <0>; 775 }; 776 }; 777 }; 778 }; 779 780 power-domain@MT8195_POWER_DOMAIN_PCIE_MAC_P0 { 781 reg = <MT8195_POWER_DOMAIN_PCIE_MAC_P0>; 782 mediatek,infracfg = <&infracfg_ao>; 783 #power-domain-cells = <0>; 784 }; 785 786 power-domain@MT8195_POWER_DOMAIN_PCIE_MAC_P1 { 787 reg = <MT8195_POWER_DOMAIN_PCIE_MAC_P1>; 788 mediatek,infracfg = <&infracfg_ao>; 789 #power-domain-cells = <0>; 790 }; 791 792 power-domain@MT8195_POWER_DOMAIN_PCIE_PHY { 793 reg = <MT8195_POWER_DOMAIN_PCIE_PHY>; 794 #power-domain-cells = <0>; 795 }; 796 797 power-domain@MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY { 798 reg = <MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY>; 799 #power-domain-cells = <0>; 800 }; 801 802 power-domain@MT8195_POWER_DOMAIN_CSI_RX_TOP { 803 reg = <MT8195_POWER_DOMAIN_CSI_RX_TOP>; 804 clocks = <&topckgen CLK_TOP_SENINF>, 805 <&topckgen CLK_TOP_SENINF2>; 806 clock-names = "csi_rx_top", "csi_rx_top1"; 807 #power-domain-cells = <0>; 808 }; 809 810 power-domain@MT8195_POWER_DOMAIN_ETHER { 811 reg = <MT8195_POWER_DOMAIN_ETHER>; 812 clocks = <&pericfg_ao CLK_PERI_AO_ETHERNET_MAC>; 813 clock-names = "ether"; 814 #power-domain-cells = <0>; 815 }; 816 817 power-domain@MT8195_POWER_DOMAIN_ADSP { 818 reg = <MT8195_POWER_DOMAIN_ADSP>; 819 clocks = <&topckgen CLK_TOP_ADSP>, 820 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>; 821 clock-names = "adsp", "adsp1"; 822 #address-cells = <1>; 823 #size-cells = <0>; 824 mediatek,infracfg = <&infracfg_ao>; 825 #power-domain-cells = <1>; 826 827 power-domain@MT8195_POWER_DOMAIN_AUDIO { 828 reg = <MT8195_POWER_DOMAIN_AUDIO>; 829 clocks = <&topckgen CLK_TOP_A1SYS_HP>, 830 <&topckgen CLK_TOP_AUD_INTBUS>, 831 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>, 832 <&infracfg_ao CLK_INFRA_AO_AUDIO_26M_B>; 833 clock-names = "audio", "audio1", "audio2", 834 "audio3"; 835 mediatek,infracfg = <&infracfg_ao>; 836 #power-domain-cells = <0>; 837 }; 838 }; 839 }; 840 }; 841 842 watchdog: watchdog@10007000 { 843 compatible = "mediatek,mt8195-wdt"; 844 mediatek,disable-extrst; 845 reg = <0 0x10007000 0 0x100>; 846 #reset-cells = <1>; 847 }; 848 849 apmixedsys: syscon@1000c000 { 850 compatible = "mediatek,mt8195-apmixedsys", "syscon"; 851 reg = <0 0x1000c000 0 0x1000>; 852 #clock-cells = <1>; 853 }; 854 855 systimer: timer@10017000 { 856 compatible = "mediatek,mt8195-timer", 857 "mediatek,mt6765-timer"; 858 reg = <0 0x10017000 0 0x1000>; 859 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>; 860 clocks = <&clk13m>; 861 }; 862 863 pwrap: pwrap@10024000 { 864 compatible = "mediatek,mt8195-pwrap", "syscon"; 865 reg = <0 0x10024000 0 0x1000>; 866 reg-names = "pwrap"; 867 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH 0>; 868 clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>, 869 <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>; 870 clock-names = "spi", "wrap"; 871 assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC>; 872 assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>; 873 }; 874 875 spmi: spmi@10027000 { 876 compatible = "mediatek,mt8195-spmi"; 877 reg = <0 0x10027000 0 0x000e00>, 878 <0 0x10029000 0 0x000100>; 879 reg-names = "pmif", "spmimst"; 880 clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>, 881 <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>, 882 <&topckgen CLK_TOP_SPMI_M_MST>; 883 clock-names = "pmif_sys_ck", 884 "pmif_tmr_ck", 885 "spmimst_clk_mux"; 886 assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC>; 887 assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>; 888 }; 889 890 iommu_infra: infra-iommu@10315000 { 891 compatible = "mediatek,mt8195-iommu-infra"; 892 reg = <0 0x10315000 0 0x5000>; 893 interrupts = <GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH 0>, 894 <GIC_SPI 796 IRQ_TYPE_LEVEL_HIGH 0>, 895 <GIC_SPI 797 IRQ_TYPE_LEVEL_HIGH 0>, 896 <GIC_SPI 798 IRQ_TYPE_LEVEL_HIGH 0>, 897 <GIC_SPI 799 IRQ_TYPE_LEVEL_HIGH 0>; 898 #iommu-cells = <1>; 899 }; 900 901 gce0: mailbox@10320000 { 902 compatible = "mediatek,mt8195-gce"; 903 reg = <0 0x10320000 0 0x4000>; 904 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH 0>; 905 #mbox-cells = <2>; 906 clocks = <&infracfg_ao CLK_INFRA_AO_GCE>; 907 }; 908 909 gce1: mailbox@10330000 { 910 compatible = "mediatek,mt8195-gce"; 911 reg = <0 0x10330000 0 0x4000>; 912 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH 0>; 913 #mbox-cells = <2>; 914 clocks = <&infracfg_ao CLK_INFRA_AO_GCE2>; 915 }; 916 917 scp: scp@10500000 { 918 compatible = "mediatek,mt8195-scp"; 919 reg = <0 0x10500000 0 0x100000>, 920 <0 0x10720000 0 0xe0000>, 921 <0 0x10700000 0 0x8000>; 922 reg-names = "sram", "cfg", "l1tcm"; 923 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH 0>; 924 status = "disabled"; 925 }; 926 927 scp_adsp: clock-controller@10720000 { 928 compatible = "mediatek,mt8195-scp_adsp"; 929 reg = <0 0x10720000 0 0x1000>; 930 #clock-cells = <1>; 931 }; 932 933 adsp: dsp@10803000 { 934 compatible = "mediatek,mt8195-dsp"; 935 reg = <0 0x10803000 0 0x1000>, 936 <0 0x10840000 0 0x40000>; 937 reg-names = "cfg", "sram"; 938 clocks = <&topckgen CLK_TOP_ADSP>, 939 <&clk26m>, 940 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>, 941 <&topckgen CLK_TOP_MAINPLL_D7_D2>, 942 <&scp_adsp CLK_SCP_ADSP_AUDIODSP>, 943 <&topckgen CLK_TOP_AUDIO_H>; 944 clock-names = "adsp_sel", 945 "clk26m_ck", 946 "audio_local_bus", 947 "mainpll_d7_d2", 948 "scp_adsp_audiodsp", 949 "audio_h"; 950 power-domains = <&spm MT8195_POWER_DOMAIN_ADSP>; 951 mbox-names = "rx", "tx"; 952 mboxes = <&adsp_mailbox0>, <&adsp_mailbox1>; 953 status = "disabled"; 954 }; 955 956 adsp_mailbox0: mailbox@10816000 { 957 compatible = "mediatek,mt8195-adsp-mbox"; 958 #mbox-cells = <0>; 959 reg = <0 0x10816000 0 0x1000>; 960 interrupts = <GIC_SPI 702 IRQ_TYPE_LEVEL_HIGH 0>; 961 }; 962 963 adsp_mailbox1: mailbox@10817000 { 964 compatible = "mediatek,mt8195-adsp-mbox"; 965 #mbox-cells = <0>; 966 reg = <0 0x10817000 0 0x1000>; 967 interrupts = <GIC_SPI 703 IRQ_TYPE_LEVEL_HIGH 0>; 968 }; 969 970 afe: mt8195-afe-pcm@10890000 { 971 compatible = "mediatek,mt8195-audio"; 972 reg = <0 0x10890000 0 0x10000>; 973 mediatek,topckgen = <&topckgen>; 974 power-domains = <&spm MT8195_POWER_DOMAIN_AUDIO>; 975 interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH 0>; 976 resets = <&watchdog 14>; 977 reset-names = "audiosys"; 978 clocks = <&clk26m>, 979 <&apmixedsys CLK_APMIXED_APLL1>, 980 <&apmixedsys CLK_APMIXED_APLL2>, 981 <&topckgen CLK_TOP_APLL12_DIV0>, 982 <&topckgen CLK_TOP_APLL12_DIV1>, 983 <&topckgen CLK_TOP_APLL12_DIV2>, 984 <&topckgen CLK_TOP_APLL12_DIV3>, 985 <&topckgen CLK_TOP_APLL12_DIV9>, 986 <&topckgen CLK_TOP_A1SYS_HP>, 987 <&topckgen CLK_TOP_AUD_INTBUS>, 988 <&topckgen CLK_TOP_AUDIO_H>, 989 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>, 990 <&topckgen CLK_TOP_DPTX_MCK>, 991 <&topckgen CLK_TOP_I2SO1_MCK>, 992 <&topckgen CLK_TOP_I2SO2_MCK>, 993 <&topckgen CLK_TOP_I2SI1_MCK>, 994 <&topckgen CLK_TOP_I2SI2_MCK>, 995 <&infracfg_ao CLK_INFRA_AO_AUDIO_26M_B>, 996 <&scp_adsp CLK_SCP_ADSP_AUDIODSP>; 997 clock-names = "clk26m", 998 "apll1_ck", 999 "apll2_ck", 1000 "apll12_div0", 1001 "apll12_div1", 1002 "apll12_div2", 1003 "apll12_div3", 1004 "apll12_div9", 1005 "a1sys_hp_sel", 1006 "aud_intbus_sel", 1007 "audio_h_sel", 1008 "audio_local_bus_sel", 1009 "dptx_m_sel", 1010 "i2so1_m_sel", 1011 "i2so2_m_sel", 1012 "i2si1_m_sel", 1013 "i2si2_m_sel", 1014 "infra_ao_audio_26m_b", 1015 "scp_adsp_audiodsp"; 1016 status = "disabled"; 1017 }; 1018 1019 uart0: serial@11001100 { 1020 compatible = "mediatek,mt8195-uart", 1021 "mediatek,mt6577-uart"; 1022 reg = <0 0x11001100 0 0x100>; 1023 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH 0>; 1024 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART0>; 1025 clock-names = "baud", "bus"; 1026 status = "disabled"; 1027 }; 1028 1029 uart1: serial@11001200 { 1030 compatible = "mediatek,mt8195-uart", 1031 "mediatek,mt6577-uart"; 1032 reg = <0 0x11001200 0 0x100>; 1033 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH 0>; 1034 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART1>; 1035 clock-names = "baud", "bus"; 1036 status = "disabled"; 1037 }; 1038 1039 uart2: serial@11001300 { 1040 compatible = "mediatek,mt8195-uart", 1041 "mediatek,mt6577-uart"; 1042 reg = <0 0x11001300 0 0x100>; 1043 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH 0>; 1044 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART2>; 1045 clock-names = "baud", "bus"; 1046 status = "disabled"; 1047 }; 1048 1049 uart3: serial@11001400 { 1050 compatible = "mediatek,mt8195-uart", 1051 "mediatek,mt6577-uart"; 1052 reg = <0 0x11001400 0 0x100>; 1053 interrupts = <GIC_SPI 723 IRQ_TYPE_LEVEL_HIGH 0>; 1054 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART3>; 1055 clock-names = "baud", "bus"; 1056 status = "disabled"; 1057 }; 1058 1059 uart4: serial@11001500 { 1060 compatible = "mediatek,mt8195-uart", 1061 "mediatek,mt6577-uart"; 1062 reg = <0 0x11001500 0 0x100>; 1063 interrupts = <GIC_SPI 724 IRQ_TYPE_LEVEL_HIGH 0>; 1064 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART4>; 1065 clock-names = "baud", "bus"; 1066 status = "disabled"; 1067 }; 1068 1069 uart5: serial@11001600 { 1070 compatible = "mediatek,mt8195-uart", 1071 "mediatek,mt6577-uart"; 1072 reg = <0 0x11001600 0 0x100>; 1073 interrupts = <GIC_SPI 725 IRQ_TYPE_LEVEL_HIGH 0>; 1074 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART5>; 1075 clock-names = "baud", "bus"; 1076 status = "disabled"; 1077 }; 1078 1079 auxadc: auxadc@11002000 { 1080 compatible = "mediatek,mt8195-auxadc", 1081 "mediatek,mt8173-auxadc"; 1082 reg = <0 0x11002000 0 0x1000>; 1083 clocks = <&infracfg_ao CLK_INFRA_AO_AUXADC>; 1084 clock-names = "main"; 1085 #io-channel-cells = <1>; 1086 status = "disabled"; 1087 }; 1088 1089 pericfg_ao: syscon@11003000 { 1090 compatible = "mediatek,mt8195-pericfg_ao", "syscon"; 1091 reg = <0 0x11003000 0 0x1000>; 1092 #clock-cells = <1>; 1093 }; 1094 1095 spi0: spi@1100a000 { 1096 compatible = "mediatek,mt8195-spi", 1097 "mediatek,mt6765-spi"; 1098 #address-cells = <1>; 1099 #size-cells = <0>; 1100 reg = <0 0x1100a000 0 0x1000>; 1101 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH 0>; 1102 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 1103 <&topckgen CLK_TOP_SPI>, 1104 <&infracfg_ao CLK_INFRA_AO_SPI0>; 1105 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1106 status = "disabled"; 1107 }; 1108 1109 lvts_ap: thermal-sensor@1100b000 { 1110 compatible = "mediatek,mt8195-lvts-ap"; 1111 reg = <0 0x1100b000 0 0x1000>; 1112 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH 0>; 1113 clocks = <&infracfg_ao CLK_INFRA_AO_THERM>; 1114 resets = <&infracfg_ao MT8195_INFRA_RST0_THERM_CTRL_SWRST>; 1115 nvmem-cells = <&lvts_efuse_data1 &lvts_efuse_data2>; 1116 nvmem-cell-names = "lvts-calib-data-1", "lvts-calib-data-2"; 1117 #thermal-sensor-cells = <1>; 1118 }; 1119 1120 spi1: spi@11010000 { 1121 compatible = "mediatek,mt8195-spi", 1122 "mediatek,mt6765-spi"; 1123 #address-cells = <1>; 1124 #size-cells = <0>; 1125 reg = <0 0x11010000 0 0x1000>; 1126 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH 0>; 1127 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 1128 <&topckgen CLK_TOP_SPI>, 1129 <&infracfg_ao CLK_INFRA_AO_SPI1>; 1130 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1131 status = "disabled"; 1132 }; 1133 1134 spi2: spi@11012000 { 1135 compatible = "mediatek,mt8195-spi", 1136 "mediatek,mt6765-spi"; 1137 #address-cells = <1>; 1138 #size-cells = <0>; 1139 reg = <0 0x11012000 0 0x1000>; 1140 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH 0>; 1141 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 1142 <&topckgen CLK_TOP_SPI>, 1143 <&infracfg_ao CLK_INFRA_AO_SPI2>; 1144 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1145 status = "disabled"; 1146 }; 1147 1148 spi3: spi@11013000 { 1149 compatible = "mediatek,mt8195-spi", 1150 "mediatek,mt6765-spi"; 1151 #address-cells = <1>; 1152 #size-cells = <0>; 1153 reg = <0 0x11013000 0 0x1000>; 1154 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH 0>; 1155 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 1156 <&topckgen CLK_TOP_SPI>, 1157 <&infracfg_ao CLK_INFRA_AO_SPI3>; 1158 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1159 status = "disabled"; 1160 }; 1161 1162 spi4: spi@11018000 { 1163 compatible = "mediatek,mt8195-spi", 1164 "mediatek,mt6765-spi"; 1165 #address-cells = <1>; 1166 #size-cells = <0>; 1167 reg = <0 0x11018000 0 0x1000>; 1168 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH 0>; 1169 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 1170 <&topckgen CLK_TOP_SPI>, 1171 <&infracfg_ao CLK_INFRA_AO_SPI4>; 1172 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1173 status = "disabled"; 1174 }; 1175 1176 spi5: spi@11019000 { 1177 compatible = "mediatek,mt8195-spi", 1178 "mediatek,mt6765-spi"; 1179 #address-cells = <1>; 1180 #size-cells = <0>; 1181 reg = <0 0x11019000 0 0x1000>; 1182 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH 0>; 1183 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 1184 <&topckgen CLK_TOP_SPI>, 1185 <&infracfg_ao CLK_INFRA_AO_SPI5>; 1186 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1187 status = "disabled"; 1188 }; 1189 1190 spis0: spi@1101d000 { 1191 compatible = "mediatek,mt8195-spi-slave"; 1192 reg = <0 0x1101d000 0 0x1000>; 1193 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH 0>; 1194 clocks = <&infracfg_ao CLK_INFRA_AO_SPIS0>; 1195 clock-names = "spi"; 1196 assigned-clocks = <&topckgen CLK_TOP_SPIS>; 1197 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>; 1198 status = "disabled"; 1199 }; 1200 1201 spis1: spi@1101e000 { 1202 compatible = "mediatek,mt8195-spi-slave"; 1203 reg = <0 0x1101e000 0 0x1000>; 1204 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH 0>; 1205 clocks = <&infracfg_ao CLK_INFRA_AO_SPIS1>; 1206 clock-names = "spi"; 1207 assigned-clocks = <&topckgen CLK_TOP_SPIS>; 1208 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>; 1209 status = "disabled"; 1210 }; 1211 1212 eth: ethernet@11021000 { 1213 compatible = "mediatek,mt8195-gmac", "snps,dwmac-5.10a"; 1214 reg = <0 0x11021000 0 0x4000>; 1215 interrupts = <GIC_SPI 716 IRQ_TYPE_LEVEL_HIGH 0>; 1216 interrupt-names = "macirq"; 1217 clock-names = "axi", 1218 "apb", 1219 "mac_main", 1220 "ptp_ref", 1221 "rmii_internal", 1222 "mac_cg"; 1223 clocks = <&pericfg_ao CLK_PERI_AO_ETHERNET>, 1224 <&pericfg_ao CLK_PERI_AO_ETHERNET_BUS>, 1225 <&topckgen CLK_TOP_SNPS_ETH_250M>, 1226 <&topckgen CLK_TOP_SNPS_ETH_62P4M_PTP>, 1227 <&topckgen CLK_TOP_SNPS_ETH_50M_RMII>, 1228 <&pericfg_ao CLK_PERI_AO_ETHERNET_MAC>; 1229 assigned-clocks = <&topckgen CLK_TOP_SNPS_ETH_250M>, 1230 <&topckgen CLK_TOP_SNPS_ETH_62P4M_PTP>, 1231 <&topckgen CLK_TOP_SNPS_ETH_50M_RMII>; 1232 assigned-clock-parents = <&topckgen CLK_TOP_ETHPLL_D2>, 1233 <&topckgen CLK_TOP_ETHPLL_D8>, 1234 <&topckgen CLK_TOP_ETHPLL_D10>; 1235 power-domains = <&spm MT8195_POWER_DOMAIN_ETHER>; 1236 mediatek,pericfg = <&infracfg_ao>; 1237 snps,axi-config = <&stmmac_axi_setup>; 1238 snps,mtl-rx-config = <&mtl_rx_setup>; 1239 snps,mtl-tx-config = <&mtl_tx_setup>; 1240 snps,txpbl = <16>; 1241 snps,rxpbl = <16>; 1242 snps,clk-csr = <0>; 1243 status = "disabled"; 1244 1245 mdio { 1246 compatible = "snps,dwmac-mdio"; 1247 #address-cells = <1>; 1248 #size-cells = <0>; 1249 }; 1250 1251 stmmac_axi_setup: stmmac-axi-config { 1252 snps,wr_osr_lmt = <0x7>; 1253 snps,rd_osr_lmt = <0x7>; 1254 snps,blen = <0 0 0 0 16 8 4>; 1255 }; 1256 1257 mtl_rx_setup: rx-queues-config { 1258 snps,rx-queues-to-use = <4>; 1259 snps,rx-sched-sp; 1260 queue0 { 1261 snps,dcb-algorithm; 1262 snps,map-to-dma-channel = <0x0>; 1263 }; 1264 queue1 { 1265 snps,dcb-algorithm; 1266 snps,map-to-dma-channel = <0x0>; 1267 }; 1268 queue2 { 1269 snps,dcb-algorithm; 1270 snps,map-to-dma-channel = <0x0>; 1271 }; 1272 queue3 { 1273 snps,dcb-algorithm; 1274 snps,map-to-dma-channel = <0x0>; 1275 }; 1276 }; 1277 1278 mtl_tx_setup: tx-queues-config { 1279 snps,tx-queues-to-use = <4>; 1280 snps,tx-sched-wrr; 1281 queue0 { 1282 snps,weight = <0x10>; 1283 snps,dcb-algorithm; 1284 snps,priority = <0x0>; 1285 }; 1286 queue1 { 1287 snps,weight = <0x11>; 1288 snps,dcb-algorithm; 1289 snps,priority = <0x1>; 1290 }; 1291 queue2 { 1292 snps,weight = <0x12>; 1293 snps,dcb-algorithm; 1294 snps,priority = <0x2>; 1295 }; 1296 queue3 { 1297 snps,weight = <0x13>; 1298 snps,dcb-algorithm; 1299 snps,priority = <0x3>; 1300 }; 1301 }; 1302 }; 1303 1304 xhci0: usb@11200000 { 1305 compatible = "mediatek,mt8195-xhci", 1306 "mediatek,mtk-xhci"; 1307 reg = <0 0x11200000 0 0x1000>, 1308 <0 0x11203e00 0 0x0100>; 1309 reg-names = "mac", "ippc"; 1310 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH 0>; 1311 phys = <&u2port0 PHY_TYPE_USB2>, 1312 <&u3port0 PHY_TYPE_USB3>; 1313 assigned-clocks = <&topckgen CLK_TOP_USB_TOP>, 1314 <&topckgen CLK_TOP_SSUSB_XHCI>; 1315 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, 1316 <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 1317 clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB>, 1318 <&topckgen CLK_TOP_SSUSB_REF>, 1319 <&apmixedsys CLK_APMIXED_USB1PLL>, 1320 <&clk26m>, 1321 <&infracfg_ao CLK_INFRA_AO_SSUSB_XHCI>; 1322 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", 1323 "xhci_ck"; 1324 mediatek,syscon-wakeup = <&pericfg 0x400 103>; 1325 wakeup-source; 1326 status = "disabled"; 1327 }; 1328 1329 mmc0: mmc@11230000 { 1330 compatible = "mediatek,mt8195-mmc", 1331 "mediatek,mt8183-mmc"; 1332 reg = <0 0x11230000 0 0x10000>, 1333 <0 0x11f50000 0 0x1000>; 1334 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>; 1335 clocks = <&topckgen CLK_TOP_MSDC50_0>, 1336 <&infracfg_ao CLK_INFRA_AO_MSDC0>, 1337 <&infracfg_ao CLK_INFRA_AO_MSDC0_SRC>; 1338 clock-names = "source", "hclk", "source_cg"; 1339 status = "disabled"; 1340 }; 1341 1342 mmc1: mmc@11240000 { 1343 compatible = "mediatek,mt8195-mmc", 1344 "mediatek,mt8183-mmc"; 1345 reg = <0 0x11240000 0 0x1000>, 1346 <0 0x11c70000 0 0x1000>; 1347 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH 0>; 1348 clocks = <&topckgen CLK_TOP_MSDC30_1>, 1349 <&infracfg_ao CLK_INFRA_AO_MSDC1>, 1350 <&infracfg_ao CLK_INFRA_AO_MSDC1_SRC>; 1351 clock-names = "source", "hclk", "source_cg"; 1352 assigned-clocks = <&topckgen CLK_TOP_MSDC30_1>; 1353 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>; 1354 status = "disabled"; 1355 }; 1356 1357 mmc2: mmc@11250000 { 1358 compatible = "mediatek,mt8195-mmc", 1359 "mediatek,mt8183-mmc"; 1360 reg = <0 0x11250000 0 0x1000>, 1361 <0 0x11e60000 0 0x1000>; 1362 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH 0>; 1363 clocks = <&topckgen CLK_TOP_MSDC30_2>, 1364 <&infracfg_ao CLK_INFRA_AO_CG1_MSDC2>, 1365 <&infracfg_ao CLK_INFRA_AO_CG3_MSDC2>; 1366 clock-names = "source", "hclk", "source_cg"; 1367 assigned-clocks = <&topckgen CLK_TOP_MSDC30_2>; 1368 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>; 1369 status = "disabled"; 1370 }; 1371 1372 lvts_mcu: thermal-sensor@11278000 { 1373 compatible = "mediatek,mt8195-lvts-mcu"; 1374 reg = <0 0x11278000 0 0x1000>; 1375 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH 0>; 1376 clocks = <&infracfg_ao CLK_INFRA_AO_THERM>; 1377 resets = <&infracfg_ao MT8195_INFRA_RST4_THERM_CTRL_MCU_SWRST>; 1378 nvmem-cells = <&lvts_efuse_data1 &lvts_efuse_data2>; 1379 nvmem-cell-names = "lvts-calib-data-1", "lvts-calib-data-2"; 1380 #thermal-sensor-cells = <1>; 1381 }; 1382 1383 xhci1: usb@11290000 { 1384 compatible = "mediatek,mt8195-xhci", 1385 "mediatek,mtk-xhci"; 1386 reg = <0 0x11290000 0 0x1000>, 1387 <0 0x11293e00 0 0x0100>; 1388 reg-names = "mac", "ippc"; 1389 interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH 0>; 1390 phys = <&u2port1 PHY_TYPE_USB2>; 1391 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_1P>, 1392 <&topckgen CLK_TOP_SSUSB_XHCI_1P>; 1393 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, 1394 <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 1395 clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_1P_BUS>, 1396 <&topckgen CLK_TOP_SSUSB_P1_REF>, 1397 <&apmixedsys CLK_APMIXED_USB1PLL>, 1398 <&clk26m>, 1399 <&pericfg_ao CLK_PERI_AO_SSUSB_1P_XHCI>; 1400 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", 1401 "xhci_ck"; 1402 mediatek,syscon-wakeup = <&pericfg 0x400 104>; 1403 wakeup-source; 1404 status = "disabled"; 1405 }; 1406 1407 xhci2: usb@112a0000 { 1408 compatible = "mediatek,mt8195-xhci", 1409 "mediatek,mtk-xhci"; 1410 reg = <0 0x112a0000 0 0x1000>, 1411 <0 0x112a3e00 0 0x0100>; 1412 reg-names = "mac", "ippc"; 1413 interrupts = <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH 0>; 1414 phys = <&u2port2 PHY_TYPE_USB2>; 1415 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_2P>, 1416 <&topckgen CLK_TOP_SSUSB_XHCI_2P>; 1417 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, 1418 <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 1419 clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_2P_BUS>, 1420 <&topckgen CLK_TOP_SSUSB_P2_REF>, 1421 <&clk26m>, 1422 <&clk26m>, 1423 <&pericfg_ao CLK_PERI_AO_SSUSB_2P_XHCI>; 1424 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", 1425 "xhci_ck"; 1426 mediatek,syscon-wakeup = <&pericfg 0x400 105>; 1427 wakeup-source; 1428 status = "disabled"; 1429 }; 1430 1431 xhci3: usb@112b0000 { 1432 compatible = "mediatek,mt8195-xhci", 1433 "mediatek,mtk-xhci"; 1434 reg = <0 0x112b0000 0 0x1000>, 1435 <0 0x112b3e00 0 0x0100>; 1436 reg-names = "mac", "ippc"; 1437 interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH 0>; 1438 phys = <&u2port3 PHY_TYPE_USB2>; 1439 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_3P>, 1440 <&topckgen CLK_TOP_SSUSB_XHCI_3P>; 1441 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, 1442 <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 1443 clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_3P_BUS>, 1444 <&topckgen CLK_TOP_SSUSB_P3_REF>, 1445 <&clk26m>, 1446 <&clk26m>, 1447 <&pericfg_ao CLK_PERI_AO_SSUSB_3P_XHCI>; 1448 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", 1449 "xhci_ck"; 1450 mediatek,syscon-wakeup = <&pericfg 0x400 106>; 1451 wakeup-source; 1452 status = "disabled"; 1453 }; 1454 1455 pcie0: pcie@112f0000 { 1456 compatible = "mediatek,mt8195-pcie", 1457 "mediatek,mt8192-pcie"; 1458 device_type = "pci"; 1459 #address-cells = <3>; 1460 #size-cells = <2>; 1461 reg = <0 0x112f0000 0 0x4000>; 1462 reg-names = "pcie-mac"; 1463 interrupts = <GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH 0>; 1464 bus-range = <0x00 0xff>; 1465 ranges = <0x81000000 0 0x20000000 1466 0x0 0x20000000 0 0x200000>, 1467 <0x82000000 0 0x20200000 1468 0x0 0x20200000 0 0x3e00000>; 1469 1470 iommu-map = <0 &iommu_infra IOMMU_PORT_INFRA_PCIE0 0x2>; 1471 iommu-map-mask = <0x0>; 1472 1473 clocks = <&infracfg_ao CLK_INFRA_AO_PCIE_PL_P_250M_P0>, 1474 <&infracfg_ao CLK_INFRA_AO_PCIE_TL_26M>, 1475 <&infracfg_ao CLK_INFRA_AO_PCIE_TL_96M>, 1476 <&infracfg_ao CLK_INFRA_AO_PCIE_TL_32K>, 1477 <&infracfg_ao CLK_INFRA_AO_PCIE_PERI_26M>, 1478 <&pericfg_ao CLK_PERI_AO_PCIE_P0_MEM>; 1479 clock-names = "pl_250m", "tl_26m", "tl_96m", 1480 "tl_32k", "peri_26m", "peri_mem"; 1481 assigned-clocks = <&topckgen CLK_TOP_TL>; 1482 assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4_D4>; 1483 1484 phys = <&pciephy>; 1485 phy-names = "pcie-phy"; 1486 1487 power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_MAC_P0>; 1488 1489 resets = <&infracfg_ao MT8195_INFRA_RST2_PCIE_P0_SWRST>; 1490 reset-names = "mac"; 1491 1492 #interrupt-cells = <1>; 1493 interrupt-map-mask = <0 0 0 7>; 1494 interrupt-map = <0 0 0 1 &pcie_intc0 0>, 1495 <0 0 0 2 &pcie_intc0 1>, 1496 <0 0 0 3 &pcie_intc0 2>, 1497 <0 0 0 4 &pcie_intc0 3>; 1498 status = "disabled"; 1499 1500 pcie_intc0: interrupt-controller { 1501 interrupt-controller; 1502 #address-cells = <0>; 1503 #interrupt-cells = <1>; 1504 }; 1505 }; 1506 1507 pcie1: pcie@112f8000 { 1508 compatible = "mediatek,mt8195-pcie", 1509 "mediatek,mt8192-pcie"; 1510 device_type = "pci"; 1511 #address-cells = <3>; 1512 #size-cells = <2>; 1513 reg = <0 0x112f8000 0 0x4000>; 1514 reg-names = "pcie-mac"; 1515 interrupts = <GIC_SPI 792 IRQ_TYPE_LEVEL_HIGH 0>; 1516 bus-range = <0x00 0xff>; 1517 ranges = <0x81000000 0 0x24000000 1518 0x0 0x24000000 0 0x200000>, 1519 <0x82000000 0 0x24200000 1520 0x0 0x24200000 0 0x3e00000>; 1521 1522 iommu-map = <0 &iommu_infra IOMMU_PORT_INFRA_PCIE1 0x2>; 1523 iommu-map-mask = <0x0>; 1524 1525 clocks = <&infracfg_ao CLK_INFRA_AO_PCIE_PL_P_250M_P1>, 1526 <&clk26m>, 1527 <&infracfg_ao CLK_INFRA_AO_PCIE_P1_TL_96M>, 1528 <&clk26m>, 1529 <&infracfg_ao CLK_INFRA_AO_PCIE_P1_PERI_26M>, 1530 /* Designer has connect pcie1 with peri_mem_p0 clock */ 1531 <&pericfg_ao CLK_PERI_AO_PCIE_P0_MEM>; 1532 clock-names = "pl_250m", "tl_26m", "tl_96m", 1533 "tl_32k", "peri_26m", "peri_mem"; 1534 assigned-clocks = <&topckgen CLK_TOP_TL_P1>; 1535 assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4_D4>; 1536 1537 phys = <&u3port1 PHY_TYPE_PCIE>; 1538 phy-names = "pcie-phy"; 1539 power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_MAC_P1>; 1540 1541 resets = <&infracfg_ao MT8195_INFRA_RST2_PCIE_P1_SWRST>; 1542 reset-names = "mac"; 1543 1544 #interrupt-cells = <1>; 1545 interrupt-map-mask = <0 0 0 7>; 1546 interrupt-map = <0 0 0 1 &pcie_intc1 0>, 1547 <0 0 0 2 &pcie_intc1 1>, 1548 <0 0 0 3 &pcie_intc1 2>, 1549 <0 0 0 4 &pcie_intc1 3>; 1550 status = "disabled"; 1551 1552 pcie_intc1: interrupt-controller { 1553 interrupt-controller; 1554 #address-cells = <0>; 1555 #interrupt-cells = <1>; 1556 }; 1557 }; 1558 1559 nor_flash: spi@1132c000 { 1560 compatible = "mediatek,mt8195-nor", 1561 "mediatek,mt8173-nor"; 1562 reg = <0 0x1132c000 0 0x1000>; 1563 interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH 0>; 1564 clocks = <&topckgen CLK_TOP_SPINOR>, 1565 <&pericfg_ao CLK_PERI_AO_FLASHIF_FLASH>, 1566 <&pericfg_ao CLK_PERI_AO_FLASHIF_BUS>; 1567 clock-names = "spi", "sf", "axi"; 1568 #address-cells = <1>; 1569 #size-cells = <0>; 1570 status = "disabled"; 1571 }; 1572 1573 efuse: efuse@11c10000 { 1574 compatible = "mediatek,mt8195-efuse", "mediatek,efuse"; 1575 reg = <0 0x11c10000 0 0x1000>; 1576 #address-cells = <1>; 1577 #size-cells = <1>; 1578 u3_tx_imp_p0: usb3-tx-imp@184,1 { 1579 reg = <0x184 0x1>; 1580 bits = <0 5>; 1581 }; 1582 u3_rx_imp_p0: usb3-rx-imp@184,2 { 1583 reg = <0x184 0x2>; 1584 bits = <5 5>; 1585 }; 1586 u3_intr_p0: usb3-intr@185 { 1587 reg = <0x185 0x1>; 1588 bits = <2 6>; 1589 }; 1590 comb_tx_imp_p1: usb3-tx-imp@186,1 { 1591 reg = <0x186 0x1>; 1592 bits = <0 5>; 1593 }; 1594 comb_rx_imp_p1: usb3-rx-imp@186,2 { 1595 reg = <0x186 0x2>; 1596 bits = <5 5>; 1597 }; 1598 comb_intr_p1: usb3-intr@187 { 1599 reg = <0x187 0x1>; 1600 bits = <2 6>; 1601 }; 1602 u2_intr_p0: usb2-intr-p0@188,1 { 1603 reg = <0x188 0x1>; 1604 bits = <0 5>; 1605 }; 1606 u2_intr_p1: usb2-intr-p1@188,2 { 1607 reg = <0x188 0x2>; 1608 bits = <5 5>; 1609 }; 1610 u2_intr_p2: usb2-intr-p2@189,1 { 1611 reg = <0x189 0x1>; 1612 bits = <2 5>; 1613 }; 1614 u2_intr_p3: usb2-intr-p3@189,2 { 1615 reg = <0x189 0x2>; 1616 bits = <7 5>; 1617 }; 1618 pciephy_rx_ln1: pciephy-rx-ln1@190,1 { 1619 reg = <0x190 0x1>; 1620 bits = <0 4>; 1621 }; 1622 pciephy_tx_ln1_nmos: pciephy-tx-ln1-nmos@190,2 { 1623 reg = <0x190 0x1>; 1624 bits = <4 4>; 1625 }; 1626 pciephy_tx_ln1_pmos: pciephy-tx-ln1-pmos@191,1 { 1627 reg = <0x191 0x1>; 1628 bits = <0 4>; 1629 }; 1630 pciephy_rx_ln0: pciephy-rx-ln0@191,2 { 1631 reg = <0x191 0x1>; 1632 bits = <4 4>; 1633 }; 1634 pciephy_tx_ln0_nmos: pciephy-tx-ln0-nmos@192,1 { 1635 reg = <0x192 0x1>; 1636 bits = <0 4>; 1637 }; 1638 pciephy_tx_ln0_pmos: pciephy-tx-ln0-pmos@192,2 { 1639 reg = <0x192 0x1>; 1640 bits = <4 4>; 1641 }; 1642 pciephy_glb_intr: pciephy-glb-intr@193 { 1643 reg = <0x193 0x1>; 1644 bits = <0 4>; 1645 }; 1646 dp_calibration: dp-data@1ac { 1647 reg = <0x1ac 0x10>; 1648 }; 1649 lvts_efuse_data1: lvts1-calib@1bc { 1650 reg = <0x1bc 0x14>; 1651 }; 1652 lvts_efuse_data2: lvts2-calib@1d0 { 1653 reg = <0x1d0 0x38>; 1654 }; 1655 }; 1656 1657 u3phy2: t-phy@11c40000 { 1658 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3"; 1659 #address-cells = <1>; 1660 #size-cells = <1>; 1661 ranges = <0 0 0x11c40000 0x700>; 1662 status = "disabled"; 1663 1664 u2port2: usb-phy@0 { 1665 reg = <0x0 0x700>; 1666 clocks = <&topckgen CLK_TOP_SSUSB_PHY_P2_REF>; 1667 clock-names = "ref"; 1668 #phy-cells = <1>; 1669 }; 1670 }; 1671 1672 u3phy3: t-phy@11c50000 { 1673 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3"; 1674 #address-cells = <1>; 1675 #size-cells = <1>; 1676 ranges = <0 0 0x11c50000 0x700>; 1677 status = "disabled"; 1678 1679 u2port3: usb-phy@0 { 1680 reg = <0x0 0x700>; 1681 clocks = <&topckgen CLK_TOP_SSUSB_PHY_P3_REF>; 1682 clock-names = "ref"; 1683 #phy-cells = <1>; 1684 }; 1685 }; 1686 1687 i2c5: i2c@11d00000 { 1688 compatible = "mediatek,mt8195-i2c", 1689 "mediatek,mt8192-i2c"; 1690 reg = <0 0x11d00000 0 0x1000>, 1691 <0 0x10220580 0 0x80>; 1692 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH 0>; 1693 clock-div = <1>; 1694 clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C5>, 1695 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1696 clock-names = "main", "dma"; 1697 #address-cells = <1>; 1698 #size-cells = <0>; 1699 status = "disabled"; 1700 }; 1701 1702 i2c6: i2c@11d01000 { 1703 compatible = "mediatek,mt8195-i2c", 1704 "mediatek,mt8192-i2c"; 1705 reg = <0 0x11d01000 0 0x1000>, 1706 <0 0x10220600 0 0x80>; 1707 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH 0>; 1708 clock-div = <1>; 1709 clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C6>, 1710 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1711 clock-names = "main", "dma"; 1712 #address-cells = <1>; 1713 #size-cells = <0>; 1714 status = "disabled"; 1715 }; 1716 1717 i2c7: i2c@11d02000 { 1718 compatible = "mediatek,mt8195-i2c", 1719 "mediatek,mt8192-i2c"; 1720 reg = <0 0x11d02000 0 0x1000>, 1721 <0 0x10220680 0 0x80>; 1722 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>; 1723 clock-div = <1>; 1724 clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C7>, 1725 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1726 clock-names = "main", "dma"; 1727 #address-cells = <1>; 1728 #size-cells = <0>; 1729 status = "disabled"; 1730 }; 1731 1732 imp_iic_wrap_s: clock-controller@11d03000 { 1733 compatible = "mediatek,mt8195-imp_iic_wrap_s"; 1734 reg = <0 0x11d03000 0 0x1000>; 1735 #clock-cells = <1>; 1736 }; 1737 1738 i2c0: i2c@11e00000 { 1739 compatible = "mediatek,mt8195-i2c", 1740 "mediatek,mt8192-i2c"; 1741 reg = <0 0x11e00000 0 0x1000>, 1742 <0 0x10220080 0 0x80>; 1743 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH 0>; 1744 clock-div = <1>; 1745 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C0>, 1746 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1747 clock-names = "main", "dma"; 1748 #address-cells = <1>; 1749 #size-cells = <0>; 1750 status = "disabled"; 1751 }; 1752 1753 i2c1: i2c@11e01000 { 1754 compatible = "mediatek,mt8195-i2c", 1755 "mediatek,mt8192-i2c"; 1756 reg = <0 0x11e01000 0 0x1000>, 1757 <0 0x10220200 0 0x80>; 1758 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH 0>; 1759 clock-div = <1>; 1760 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C1>, 1761 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1762 clock-names = "main", "dma"; 1763 #address-cells = <1>; 1764 #size-cells = <0>; 1765 status = "disabled"; 1766 }; 1767 1768 i2c2: i2c@11e02000 { 1769 compatible = "mediatek,mt8195-i2c", 1770 "mediatek,mt8192-i2c"; 1771 reg = <0 0x11e02000 0 0x1000>, 1772 <0 0x10220380 0 0x80>; 1773 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH 0>; 1774 clock-div = <1>; 1775 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C2>, 1776 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1777 clock-names = "main", "dma"; 1778 #address-cells = <1>; 1779 #size-cells = <0>; 1780 status = "disabled"; 1781 }; 1782 1783 i2c3: i2c@11e03000 { 1784 compatible = "mediatek,mt8195-i2c", 1785 "mediatek,mt8192-i2c"; 1786 reg = <0 0x11e03000 0 0x1000>, 1787 <0 0x10220480 0 0x80>; 1788 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH 0>; 1789 clock-div = <1>; 1790 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C3>, 1791 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1792 clock-names = "main", "dma"; 1793 #address-cells = <1>; 1794 #size-cells = <0>; 1795 status = "disabled"; 1796 }; 1797 1798 i2c4: i2c@11e04000 { 1799 compatible = "mediatek,mt8195-i2c", 1800 "mediatek,mt8192-i2c"; 1801 reg = <0 0x11e04000 0 0x1000>, 1802 <0 0x10220500 0 0x80>; 1803 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH 0>; 1804 clock-div = <1>; 1805 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C4>, 1806 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1807 clock-names = "main", "dma"; 1808 #address-cells = <1>; 1809 #size-cells = <0>; 1810 status = "disabled"; 1811 }; 1812 1813 imp_iic_wrap_w: clock-controller@11e05000 { 1814 compatible = "mediatek,mt8195-imp_iic_wrap_w"; 1815 reg = <0 0x11e05000 0 0x1000>; 1816 #clock-cells = <1>; 1817 }; 1818 1819 u3phy1: t-phy@11e30000 { 1820 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3"; 1821 #address-cells = <1>; 1822 #size-cells = <1>; 1823 ranges = <0 0 0x11e30000 0xe00>; 1824 power-domains = <&spm MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY>; 1825 status = "disabled"; 1826 1827 u2port1: usb-phy@0 { 1828 reg = <0x0 0x700>; 1829 clocks = <&topckgen CLK_TOP_SSUSB_PHY_P1_REF>, 1830 <&clk26m>; 1831 clock-names = "ref", "da_ref"; 1832 #phy-cells = <1>; 1833 }; 1834 1835 u3port1: usb-phy@700 { 1836 reg = <0x700 0x700>; 1837 clocks = <&apmixedsys CLK_APMIXED_PLL_SSUSB26M>, 1838 <&topckgen CLK_TOP_SSUSB_PHY_P1_REF>; 1839 clock-names = "ref", "da_ref"; 1840 nvmem-cells = <&comb_intr_p1>, 1841 <&comb_rx_imp_p1>, 1842 <&comb_tx_imp_p1>; 1843 nvmem-cell-names = "intr", "rx_imp", "tx_imp"; 1844 #phy-cells = <1>; 1845 }; 1846 }; 1847 1848 u3phy0: t-phy@11e40000 { 1849 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3"; 1850 #address-cells = <1>; 1851 #size-cells = <1>; 1852 ranges = <0 0 0x11e40000 0xe00>; 1853 status = "disabled"; 1854 1855 u2port0: usb-phy@0 { 1856 reg = <0x0 0x700>; 1857 clocks = <&topckgen CLK_TOP_SSUSB_PHY_REF>, 1858 <&clk26m>; 1859 clock-names = "ref", "da_ref"; 1860 #phy-cells = <1>; 1861 }; 1862 1863 u3port0: usb-phy@700 { 1864 reg = <0x700 0x700>; 1865 clocks = <&apmixedsys CLK_APMIXED_PLL_SSUSB26M>, 1866 <&topckgen CLK_TOP_SSUSB_PHY_REF>; 1867 clock-names = "ref", "da_ref"; 1868 nvmem-cells = <&u3_intr_p0>, 1869 <&u3_rx_imp_p0>, 1870 <&u3_tx_imp_p0>; 1871 nvmem-cell-names = "intr", "rx_imp", "tx_imp"; 1872 #phy-cells = <1>; 1873 }; 1874 }; 1875 1876 pciephy: phy@11e80000 { 1877 compatible = "mediatek,mt8195-pcie-phy"; 1878 reg = <0 0x11e80000 0 0x10000>; 1879 reg-names = "sif"; 1880 nvmem-cells = <&pciephy_glb_intr>, <&pciephy_tx_ln0_pmos>, 1881 <&pciephy_tx_ln0_nmos>, <&pciephy_rx_ln0>, 1882 <&pciephy_tx_ln1_pmos>, <&pciephy_tx_ln1_nmos>, 1883 <&pciephy_rx_ln1>; 1884 nvmem-cell-names = "glb_intr", "tx_ln0_pmos", 1885 "tx_ln0_nmos", "rx_ln0", 1886 "tx_ln1_pmos", "tx_ln1_nmos", 1887 "rx_ln1"; 1888 power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_PHY>; 1889 #phy-cells = <0>; 1890 status = "disabled"; 1891 }; 1892 1893 ufsphy: ufs-phy@11fa0000 { 1894 compatible = "mediatek,mt8195-ufsphy", "mediatek,mt8183-ufsphy"; 1895 reg = <0 0x11fa0000 0 0xc000>; 1896 clocks = <&clk26m>, <&clk26m>; 1897 clock-names = "unipro", "mp"; 1898 #phy-cells = <0>; 1899 status = "disabled"; 1900 }; 1901 1902 gpu: gpu@13000000 { 1903 compatible = "mediatek,mt8195-mali", "mediatek,mt8192-mali", 1904 "arm,mali-valhall-jm"; 1905 reg = <0 0x13000000 0 0x4000>; 1906 1907 clocks = <&mfgcfg CLK_MFG_BG3D>; 1908 interrupts = <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH 0>, 1909 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH 0>, 1910 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH 0>; 1911 interrupt-names = "job", "mmu", "gpu"; 1912 operating-points-v2 = <&gpu_opp_table>; 1913 power-domains = <&spm MT8195_POWER_DOMAIN_MFG2>, 1914 <&spm MT8195_POWER_DOMAIN_MFG3>, 1915 <&spm MT8195_POWER_DOMAIN_MFG4>, 1916 <&spm MT8195_POWER_DOMAIN_MFG5>, 1917 <&spm MT8195_POWER_DOMAIN_MFG6>; 1918 power-domain-names = "core0", "core1", "core2", "core3", "core4"; 1919 status = "disabled"; 1920 }; 1921 1922 mfgcfg: clock-controller@13fbf000 { 1923 compatible = "mediatek,mt8195-mfgcfg"; 1924 reg = <0 0x13fbf000 0 0x1000>; 1925 #clock-cells = <1>; 1926 }; 1927 1928 vppsys0: syscon@14000000 { 1929 compatible = "mediatek,mt8195-vppsys0", "syscon"; 1930 reg = <0 0x14000000 0 0x1000>; 1931 #clock-cells = <1>; 1932 }; 1933 1934 mutex@1400f000 { 1935 compatible = "mediatek,mt8195-vpp-mutex"; 1936 reg = <0 0x1400f000 0 0x1000>; 1937 interrupts = <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH 0>; 1938 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xf000 0x1000>; 1939 clocks = <&vppsys0 CLK_VPP0_MUTEX>; 1940 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; 1941 }; 1942 1943 smi_sub_common_vpp0_vpp1_2x1: smi@14010000 { 1944 compatible = "mediatek,mt8195-smi-sub-common"; 1945 reg = <0 0x14010000 0 0x1000>; 1946 clocks = <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>, 1947 <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>, 1948 <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>; 1949 clock-names = "apb", "smi", "gals0"; 1950 mediatek,smi = <&smi_common_vpp>; 1951 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; 1952 }; 1953 1954 smi_sub_common_vdec_vpp0_2x1: smi@14011000 { 1955 compatible = "mediatek,mt8195-smi-sub-common"; 1956 reg = <0 0x14011000 0 0x1000>; 1957 clocks = <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>, 1958 <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>, 1959 <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>; 1960 clock-names = "apb", "smi", "gals0"; 1961 mediatek,smi = <&smi_common_vpp>; 1962 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; 1963 }; 1964 1965 smi_common_vpp: smi@14012000 { 1966 compatible = "mediatek,mt8195-smi-common-vpp"; 1967 reg = <0 0x14012000 0 0x1000>; 1968 clocks = <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>, 1969 <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>, 1970 <&vppsys0 CLK_VPP0_SMI_RSI>, 1971 <&vppsys0 CLK_VPP0_SMI_RSI>; 1972 clock-names = "apb", "smi", "gals0", "gals1"; 1973 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; 1974 }; 1975 1976 larb4: larb@14013000 { 1977 compatible = "mediatek,mt8195-smi-larb"; 1978 reg = <0 0x14013000 0 0x1000>; 1979 mediatek,larb-id = <4>; 1980 mediatek,smi = <&smi_sub_common_vpp0_vpp1_2x1>; 1981 clocks = <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>, 1982 <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>; 1983 clock-names = "apb", "smi"; 1984 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; 1985 }; 1986 1987 iommu_vpp: iommu@14018000 { 1988 compatible = "mediatek,mt8195-iommu-vpp"; 1989 reg = <0 0x14018000 0 0x1000>; 1990 mediatek,larbs = <&larb1 &larb3 &larb4 &larb6 &larb8 1991 &larb12 &larb14 &larb16 &larb18 1992 &larb20 &larb22 &larb23 &larb26 1993 &larb27>; 1994 interrupts = <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH 0>; 1995 clocks = <&vppsys0 CLK_VPP0_SMI_IOMMU>; 1996 clock-names = "bclk"; 1997 #iommu-cells = <1>; 1998 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; 1999 }; 2000 2001 wpesys: clock-controller@14e00000 { 2002 compatible = "mediatek,mt8195-wpesys"; 2003 reg = <0 0x14e00000 0 0x1000>; 2004 #clock-cells = <1>; 2005 }; 2006 2007 wpesys_vpp0: clock-controller@14e02000 { 2008 compatible = "mediatek,mt8195-wpesys_vpp0"; 2009 reg = <0 0x14e02000 0 0x1000>; 2010 #clock-cells = <1>; 2011 }; 2012 2013 wpesys_vpp1: clock-controller@14e03000 { 2014 compatible = "mediatek,mt8195-wpesys_vpp1"; 2015 reg = <0 0x14e03000 0 0x1000>; 2016 #clock-cells = <1>; 2017 }; 2018 2019 larb7: larb@14e04000 { 2020 compatible = "mediatek,mt8195-smi-larb"; 2021 reg = <0 0x14e04000 0 0x1000>; 2022 mediatek,larb-id = <7>; 2023 mediatek,smi = <&smi_common_vdo>; 2024 clocks = <&wpesys CLK_WPE_SMI_LARB7>, 2025 <&wpesys CLK_WPE_SMI_LARB7>; 2026 clock-names = "apb", "smi"; 2027 power-domains = <&spm MT8195_POWER_DOMAIN_WPESYS>; 2028 }; 2029 2030 larb8: larb@14e05000 { 2031 compatible = "mediatek,mt8195-smi-larb"; 2032 reg = <0 0x14e05000 0 0x1000>; 2033 mediatek,larb-id = <8>; 2034 mediatek,smi = <&smi_common_vpp>; 2035 clocks = <&wpesys CLK_WPE_SMI_LARB8>, 2036 <&wpesys CLK_WPE_SMI_LARB8>, 2037 <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>; 2038 clock-names = "apb", "smi", "gals"; 2039 power-domains = <&spm MT8195_POWER_DOMAIN_WPESYS>; 2040 }; 2041 2042 vppsys1: syscon@14f00000 { 2043 compatible = "mediatek,mt8195-vppsys1", "syscon"; 2044 reg = <0 0x14f00000 0 0x1000>; 2045 #clock-cells = <1>; 2046 }; 2047 2048 mutex@14f01000 { 2049 compatible = "mediatek,mt8195-vpp-mutex"; 2050 reg = <0 0x14f01000 0 0x1000>; 2051 interrupts = <GIC_SPI 635 IRQ_TYPE_LEVEL_HIGH 0>; 2052 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x1000 0x1000>; 2053 clocks = <&vppsys1 CLK_VPP1_DISP_MUTEX>; 2054 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2055 }; 2056 2057 larb5: larb@14f02000 { 2058 compatible = "mediatek,mt8195-smi-larb"; 2059 reg = <0 0x14f02000 0 0x1000>; 2060 mediatek,larb-id = <5>; 2061 mediatek,smi = <&smi_common_vdo>; 2062 clocks = <&vppsys1 CLK_VPP1_VPPSYS1_LARB>, 2063 <&vppsys1 CLK_VPP1_VPPSYS1_GALS>, 2064 <&vppsys0 CLK_VPP0_GALS_VPP1_LARB5>; 2065 clock-names = "apb", "smi", "gals"; 2066 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2067 }; 2068 2069 larb6: larb@14f03000 { 2070 compatible = "mediatek,mt8195-smi-larb"; 2071 reg = <0 0x14f03000 0 0x1000>; 2072 mediatek,larb-id = <6>; 2073 mediatek,smi = <&smi_sub_common_vpp0_vpp1_2x1>; 2074 clocks = <&vppsys1 CLK_VPP1_VPPSYS1_LARB>, 2075 <&vppsys1 CLK_VPP1_VPPSYS1_GALS>, 2076 <&vppsys0 CLK_VPP0_GALS_VPP1_LARB6>; 2077 clock-names = "apb", "smi", "gals"; 2078 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2079 }; 2080 2081 imgsys: clock-controller@15000000 { 2082 compatible = "mediatek,mt8195-imgsys"; 2083 reg = <0 0x15000000 0 0x1000>; 2084 #clock-cells = <1>; 2085 }; 2086 2087 larb9: larb@15001000 { 2088 compatible = "mediatek,mt8195-smi-larb"; 2089 reg = <0 0x15001000 0 0x1000>; 2090 mediatek,larb-id = <9>; 2091 mediatek,smi = <&smi_sub_common_img1_3x1>; 2092 clocks = <&imgsys CLK_IMG_LARB9>, 2093 <&imgsys CLK_IMG_LARB9>, 2094 <&imgsys CLK_IMG_GALS>; 2095 clock-names = "apb", "smi", "gals"; 2096 power-domains = <&spm MT8195_POWER_DOMAIN_IMG>; 2097 }; 2098 2099 smi_sub_common_img0_3x1: smi@15002000 { 2100 compatible = "mediatek,mt8195-smi-sub-common"; 2101 reg = <0 0x15002000 0 0x1000>; 2102 clocks = <&imgsys CLK_IMG_IPE>, 2103 <&imgsys CLK_IMG_IPE>, 2104 <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>; 2105 clock-names = "apb", "smi", "gals0"; 2106 mediatek,smi = <&smi_common_vpp>; 2107 power-domains = <&spm MT8195_POWER_DOMAIN_IMG>; 2108 }; 2109 2110 smi_sub_common_img1_3x1: smi@15003000 { 2111 compatible = "mediatek,mt8195-smi-sub-common"; 2112 reg = <0 0x15003000 0 0x1000>; 2113 clocks = <&imgsys CLK_IMG_LARB9>, 2114 <&imgsys CLK_IMG_LARB9>, 2115 <&imgsys CLK_IMG_GALS>; 2116 clock-names = "apb", "smi", "gals0"; 2117 mediatek,smi = <&smi_common_vdo>; 2118 power-domains = <&spm MT8195_POWER_DOMAIN_IMG>; 2119 }; 2120 2121 imgsys1_dip_top: clock-controller@15110000 { 2122 compatible = "mediatek,mt8195-imgsys1_dip_top"; 2123 reg = <0 0x15110000 0 0x1000>; 2124 #clock-cells = <1>; 2125 }; 2126 2127 larb10: larb@15120000 { 2128 compatible = "mediatek,mt8195-smi-larb"; 2129 reg = <0 0x15120000 0 0x1000>; 2130 mediatek,larb-id = <10>; 2131 mediatek,smi = <&smi_sub_common_img1_3x1>; 2132 clocks = <&imgsys CLK_IMG_DIP0>, 2133 <&imgsys1_dip_top CLK_IMG1_DIP_TOP_LARB10>; 2134 clock-names = "apb", "smi"; 2135 power-domains = <&spm MT8195_POWER_DOMAIN_DIP>; 2136 }; 2137 2138 imgsys1_dip_nr: clock-controller@15130000 { 2139 compatible = "mediatek,mt8195-imgsys1_dip_nr"; 2140 reg = <0 0x15130000 0 0x1000>; 2141 #clock-cells = <1>; 2142 }; 2143 2144 imgsys1_wpe: clock-controller@15220000 { 2145 compatible = "mediatek,mt8195-imgsys1_wpe"; 2146 reg = <0 0x15220000 0 0x1000>; 2147 #clock-cells = <1>; 2148 }; 2149 2150 larb11: larb@15230000 { 2151 compatible = "mediatek,mt8195-smi-larb"; 2152 reg = <0 0x15230000 0 0x1000>; 2153 mediatek,larb-id = <11>; 2154 mediatek,smi = <&smi_sub_common_img1_3x1>; 2155 clocks = <&imgsys CLK_IMG_WPE0>, 2156 <&imgsys1_wpe CLK_IMG1_WPE_LARB11>; 2157 clock-names = "apb", "smi"; 2158 power-domains = <&spm MT8195_POWER_DOMAIN_DIP>; 2159 }; 2160 2161 ipesys: clock-controller@15330000 { 2162 compatible = "mediatek,mt8195-ipesys"; 2163 reg = <0 0x15330000 0 0x1000>; 2164 #clock-cells = <1>; 2165 }; 2166 2167 larb12: larb@15340000 { 2168 compatible = "mediatek,mt8195-smi-larb"; 2169 reg = <0 0x15340000 0 0x1000>; 2170 mediatek,larb-id = <12>; 2171 mediatek,smi = <&smi_sub_common_img0_3x1>; 2172 clocks = <&ipesys CLK_IPE_SMI_LARB12>, 2173 <&ipesys CLK_IPE_SMI_LARB12>; 2174 clock-names = "apb", "smi"; 2175 power-domains = <&spm MT8195_POWER_DOMAIN_IPE>; 2176 }; 2177 2178 camsys: clock-controller@16000000 { 2179 compatible = "mediatek,mt8195-camsys"; 2180 reg = <0 0x16000000 0 0x1000>; 2181 #clock-cells = <1>; 2182 }; 2183 2184 larb13: larb@16001000 { 2185 compatible = "mediatek,mt8195-smi-larb"; 2186 reg = <0 0x16001000 0 0x1000>; 2187 mediatek,larb-id = <13>; 2188 mediatek,smi = <&smi_sub_common_cam_4x1>; 2189 clocks = <&camsys CLK_CAM_LARB13>, 2190 <&camsys CLK_CAM_LARB13>, 2191 <&camsys CLK_CAM_CAM2MM0_GALS>; 2192 clock-names = "apb", "smi", "gals"; 2193 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>; 2194 }; 2195 2196 larb14: larb@16002000 { 2197 compatible = "mediatek,mt8195-smi-larb"; 2198 reg = <0 0x16002000 0 0x1000>; 2199 mediatek,larb-id = <14>; 2200 mediatek,smi = <&smi_sub_common_cam_7x1>; 2201 clocks = <&camsys CLK_CAM_LARB14>, 2202 <&camsys CLK_CAM_LARB14>; 2203 clock-names = "apb", "smi"; 2204 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>; 2205 }; 2206 2207 smi_sub_common_cam_4x1: smi@16004000 { 2208 compatible = "mediatek,mt8195-smi-sub-common"; 2209 reg = <0 0x16004000 0 0x1000>; 2210 clocks = <&camsys CLK_CAM_LARB13>, 2211 <&camsys CLK_CAM_LARB13>, 2212 <&camsys CLK_CAM_CAM2MM0_GALS>; 2213 clock-names = "apb", "smi", "gals0"; 2214 mediatek,smi = <&smi_common_vdo>; 2215 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>; 2216 }; 2217 2218 smi_sub_common_cam_7x1: smi@16005000 { 2219 compatible = "mediatek,mt8195-smi-sub-common"; 2220 reg = <0 0x16005000 0 0x1000>; 2221 clocks = <&camsys CLK_CAM_LARB14>, 2222 <&camsys CLK_CAM_CAM2MM1_GALS>, 2223 <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>; 2224 clock-names = "apb", "smi", "gals0"; 2225 mediatek,smi = <&smi_common_vpp>; 2226 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>; 2227 }; 2228 2229 larb16: larb@16012000 { 2230 compatible = "mediatek,mt8195-smi-larb"; 2231 reg = <0 0x16012000 0 0x1000>; 2232 mediatek,larb-id = <16>; 2233 mediatek,smi = <&smi_sub_common_cam_7x1>; 2234 clocks = <&camsys_rawa CLK_CAM_RAWA_LARBX>, 2235 <&camsys_rawa CLK_CAM_RAWA_LARBX>; 2236 clock-names = "apb", "smi"; 2237 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWA>; 2238 }; 2239 2240 larb17: larb@16013000 { 2241 compatible = "mediatek,mt8195-smi-larb"; 2242 reg = <0 0x16013000 0 0x1000>; 2243 mediatek,larb-id = <17>; 2244 mediatek,smi = <&smi_sub_common_cam_4x1>; 2245 clocks = <&camsys_yuva CLK_CAM_YUVA_LARBX>, 2246 <&camsys_yuva CLK_CAM_YUVA_LARBX>; 2247 clock-names = "apb", "smi"; 2248 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWA>; 2249 }; 2250 2251 larb27: larb@16014000 { 2252 compatible = "mediatek,mt8195-smi-larb"; 2253 reg = <0 0x16014000 0 0x1000>; 2254 mediatek,larb-id = <27>; 2255 mediatek,smi = <&smi_sub_common_cam_7x1>; 2256 clocks = <&camsys_rawb CLK_CAM_RAWB_LARBX>, 2257 <&camsys_rawb CLK_CAM_RAWB_LARBX>; 2258 clock-names = "apb", "smi"; 2259 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWB>; 2260 }; 2261 2262 larb28: larb@16015000 { 2263 compatible = "mediatek,mt8195-smi-larb"; 2264 reg = <0 0x16015000 0 0x1000>; 2265 mediatek,larb-id = <28>; 2266 mediatek,smi = <&smi_sub_common_cam_4x1>; 2267 clocks = <&camsys_yuvb CLK_CAM_YUVB_LARBX>, 2268 <&camsys_yuvb CLK_CAM_YUVB_LARBX>; 2269 clock-names = "apb", "smi"; 2270 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWB>; 2271 }; 2272 2273 camsys_rawa: clock-controller@1604f000 { 2274 compatible = "mediatek,mt8195-camsys_rawa"; 2275 reg = <0 0x1604f000 0 0x1000>; 2276 #clock-cells = <1>; 2277 }; 2278 2279 camsys_yuva: clock-controller@1606f000 { 2280 compatible = "mediatek,mt8195-camsys_yuva"; 2281 reg = <0 0x1606f000 0 0x1000>; 2282 #clock-cells = <1>; 2283 }; 2284 2285 camsys_rawb: clock-controller@1608f000 { 2286 compatible = "mediatek,mt8195-camsys_rawb"; 2287 reg = <0 0x1608f000 0 0x1000>; 2288 #clock-cells = <1>; 2289 }; 2290 2291 camsys_yuvb: clock-controller@160af000 { 2292 compatible = "mediatek,mt8195-camsys_yuvb"; 2293 reg = <0 0x160af000 0 0x1000>; 2294 #clock-cells = <1>; 2295 }; 2296 2297 camsys_mraw: clock-controller@16140000 { 2298 compatible = "mediatek,mt8195-camsys_mraw"; 2299 reg = <0 0x16140000 0 0x1000>; 2300 #clock-cells = <1>; 2301 }; 2302 2303 larb25: larb@16141000 { 2304 compatible = "mediatek,mt8195-smi-larb"; 2305 reg = <0 0x16141000 0 0x1000>; 2306 mediatek,larb-id = <25>; 2307 mediatek,smi = <&smi_sub_common_cam_4x1>; 2308 clocks = <&camsys CLK_CAM_LARB13>, 2309 <&camsys_mraw CLK_CAM_MRAW_LARBX>, 2310 <&camsys CLK_CAM_CAM2MM0_GALS>; 2311 clock-names = "apb", "smi", "gals"; 2312 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_MRAW>; 2313 }; 2314 2315 larb26: larb@16142000 { 2316 compatible = "mediatek,mt8195-smi-larb"; 2317 reg = <0 0x16142000 0 0x1000>; 2318 mediatek,larb-id = <26>; 2319 mediatek,smi = <&smi_sub_common_cam_7x1>; 2320 clocks = <&camsys_mraw CLK_CAM_MRAW_LARBX>, 2321 <&camsys_mraw CLK_CAM_MRAW_LARBX>; 2322 clock-names = "apb", "smi"; 2323 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_MRAW>; 2324 2325 }; 2326 2327 ccusys: clock-controller@17200000 { 2328 compatible = "mediatek,mt8195-ccusys"; 2329 reg = <0 0x17200000 0 0x1000>; 2330 #clock-cells = <1>; 2331 }; 2332 2333 larb18: larb@17201000 { 2334 compatible = "mediatek,mt8195-smi-larb"; 2335 reg = <0 0x17201000 0 0x1000>; 2336 mediatek,larb-id = <18>; 2337 mediatek,smi = <&smi_sub_common_cam_7x1>; 2338 clocks = <&ccusys CLK_CCU_LARB18>, 2339 <&ccusys CLK_CCU_LARB18>; 2340 clock-names = "apb", "smi"; 2341 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>; 2342 }; 2343 2344 larb24: larb@1800d000 { 2345 compatible = "mediatek,mt8195-smi-larb"; 2346 reg = <0 0x1800d000 0 0x1000>; 2347 mediatek,larb-id = <24>; 2348 mediatek,smi = <&smi_common_vdo>; 2349 clocks = <&vdecsys_soc CLK_VDEC_SOC_LARB1>, 2350 <&vdecsys_soc CLK_VDEC_SOC_LARB1>; 2351 clock-names = "apb", "smi"; 2352 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>; 2353 }; 2354 2355 larb23: larb@1800e000 { 2356 compatible = "mediatek,mt8195-smi-larb"; 2357 reg = <0 0x1800e000 0 0x1000>; 2358 mediatek,larb-id = <23>; 2359 mediatek,smi = <&smi_sub_common_vdec_vpp0_2x1>; 2360 clocks = <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>, 2361 <&vdecsys_soc CLK_VDEC_SOC_LARB1>; 2362 clock-names = "apb", "smi"; 2363 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>; 2364 }; 2365 2366 vdecsys_soc: clock-controller@1800f000 { 2367 compatible = "mediatek,mt8195-vdecsys_soc"; 2368 reg = <0 0x1800f000 0 0x1000>; 2369 #clock-cells = <1>; 2370 }; 2371 2372 larb21: larb@1802e000 { 2373 compatible = "mediatek,mt8195-smi-larb"; 2374 reg = <0 0x1802e000 0 0x1000>; 2375 mediatek,larb-id = <21>; 2376 mediatek,smi = <&smi_common_vdo>; 2377 clocks = <&vdecsys CLK_VDEC_LARB1>, 2378 <&vdecsys CLK_VDEC_LARB1>; 2379 clock-names = "apb", "smi"; 2380 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>; 2381 }; 2382 2383 vdecsys: clock-controller@1802f000 { 2384 compatible = "mediatek,mt8195-vdecsys"; 2385 reg = <0 0x1802f000 0 0x1000>; 2386 #clock-cells = <1>; 2387 }; 2388 2389 larb22: larb@1803e000 { 2390 compatible = "mediatek,mt8195-smi-larb"; 2391 reg = <0 0x1803e000 0 0x1000>; 2392 mediatek,larb-id = <22>; 2393 mediatek,smi = <&smi_sub_common_vdec_vpp0_2x1>; 2394 clocks = <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>, 2395 <&vdecsys_core1 CLK_VDEC_CORE1_LARB1>; 2396 clock-names = "apb", "smi"; 2397 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC2>; 2398 }; 2399 2400 vdecsys_core1: clock-controller@1803f000 { 2401 compatible = "mediatek,mt8195-vdecsys_core1"; 2402 reg = <0 0x1803f000 0 0x1000>; 2403 #clock-cells = <1>; 2404 }; 2405 2406 apusys_pll: clock-controller@190f3000 { 2407 compatible = "mediatek,mt8195-apusys_pll"; 2408 reg = <0 0x190f3000 0 0x1000>; 2409 #clock-cells = <1>; 2410 }; 2411 2412 vencsys: clock-controller@1a000000 { 2413 compatible = "mediatek,mt8195-vencsys"; 2414 reg = <0 0x1a000000 0 0x1000>; 2415 #clock-cells = <1>; 2416 }; 2417 2418 larb19: larb@1a010000 { 2419 compatible = "mediatek,mt8195-smi-larb"; 2420 reg = <0 0x1a010000 0 0x1000>; 2421 mediatek,larb-id = <19>; 2422 mediatek,smi = <&smi_common_vdo>; 2423 clocks = <&vencsys CLK_VENC_VENC>, 2424 <&vencsys CLK_VENC_GALS>; 2425 clock-names = "apb", "smi"; 2426 power-domains = <&spm MT8195_POWER_DOMAIN_VENC>; 2427 }; 2428 2429 venc: video-codec@1a020000 { 2430 compatible = "mediatek,mt8195-vcodec-enc"; 2431 reg = <0 0x1a020000 0 0x10000>; 2432 iommus = <&iommu_vdo M4U_PORT_L19_VENC_RCPU>, 2433 <&iommu_vdo M4U_PORT_L19_VENC_REC>, 2434 <&iommu_vdo M4U_PORT_L19_VENC_BSDMA>, 2435 <&iommu_vdo M4U_PORT_L19_VENC_SV_COMV>, 2436 <&iommu_vdo M4U_PORT_L19_VENC_RD_COMV>, 2437 <&iommu_vdo M4U_PORT_L19_VENC_CUR_LUMA>, 2438 <&iommu_vdo M4U_PORT_L19_VENC_CUR_CHROMA>, 2439 <&iommu_vdo M4U_PORT_L19_VENC_REF_LUMA>, 2440 <&iommu_vdo M4U_PORT_L19_VENC_REF_CHROMA>; 2441 interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH 0>; 2442 mediatek,scp = <&scp>; 2443 clocks = <&vencsys CLK_VENC_VENC>; 2444 clock-names = "venc_sel"; 2445 assigned-clocks = <&topckgen CLK_TOP_VENC>; 2446 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>; 2447 power-domains = <&spm MT8195_POWER_DOMAIN_VENC>; 2448 #address-cells = <2>; 2449 #size-cells = <2>; 2450 dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>; 2451 }; 2452 2453 jpgdec-master { 2454 compatible = "mediatek,mt8195-jpgdec"; 2455 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>; 2456 iommus = <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA0>, 2457 <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA0>, 2458 <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA1>, 2459 <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA1>, 2460 <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>, 2461 <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>; 2462 dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>; 2463 #address-cells = <2>; 2464 #size-cells = <2>; 2465 ranges; 2466 2467 jpgdec@1a040000 { 2468 compatible = "mediatek,mt8195-jpgdec-hw"; 2469 reg = <0 0x1a040000 0 0x10000>;/* JPGDEC_C0 */ 2470 iommus = <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA0>, 2471 <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA0>, 2472 <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA1>, 2473 <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA1>, 2474 <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>, 2475 <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>; 2476 interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH 0>; 2477 clocks = <&vencsys CLK_VENC_JPGDEC>; 2478 clock-names = "jpgdec"; 2479 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>; 2480 }; 2481 2482 jpgdec@1a050000 { 2483 compatible = "mediatek,mt8195-jpgdec-hw"; 2484 reg = <0 0x1a050000 0 0x10000>;/* JPGDEC_C1 */ 2485 iommus = <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA0>, 2486 <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA0>, 2487 <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA1>, 2488 <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA1>, 2489 <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>, 2490 <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>; 2491 interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH 0>; 2492 clocks = <&vencsys CLK_VENC_JPGDEC_C1>; 2493 clock-names = "jpgdec"; 2494 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>; 2495 }; 2496 2497 jpgdec@1b040000 { 2498 compatible = "mediatek,mt8195-jpgdec-hw"; 2499 reg = <0 0x1b040000 0 0x10000>;/* JPGDEC_C2 */ 2500 iommus = <&iommu_vpp M4U_PORT_L20_JPGDEC_WDMA0>, 2501 <&iommu_vpp M4U_PORT_L20_JPGDEC_BSDMA0>, 2502 <&iommu_vpp M4U_PORT_L20_JPGDEC_WDMA1>, 2503 <&iommu_vpp M4U_PORT_L20_JPGDEC_BSDMA1>, 2504 <&iommu_vpp M4U_PORT_L20_JPGDEC_BUFF_OFFSET1>, 2505 <&iommu_vpp M4U_PORT_L20_JPGDEC_BUFF_OFFSET0>; 2506 interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH 0>; 2507 clocks = <&vencsys_core1 CLK_VENC_CORE1_JPGDEC>; 2508 clock-names = "jpgdec"; 2509 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC2>; 2510 }; 2511 }; 2512 2513 vencsys_core1: clock-controller@1b000000 { 2514 compatible = "mediatek,mt8195-vencsys_core1"; 2515 reg = <0 0x1b000000 0 0x1000>; 2516 #clock-cells = <1>; 2517 }; 2518 2519 vdosys0: syscon@1c01a000 { 2520 compatible = "mediatek,mt8195-vdosys0", "mediatek,mt8195-mmsys", "syscon"; 2521 reg = <0 0x1c01a000 0 0x1000>; 2522 mboxes = <&gce0 0 CMDQ_THR_PRIO_4>; 2523 #clock-cells = <1>; 2524 }; 2525 2526 2527 jpgenc-master { 2528 compatible = "mediatek,mt8195-jpgenc"; 2529 power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>; 2530 iommus = <&iommu_vpp M4U_PORT_L20_JPGENC_Y_RDMA>, 2531 <&iommu_vpp M4U_PORT_L20_JPGENC_C_RDMA>, 2532 <&iommu_vpp M4U_PORT_L20_JPGENC_Q_TABLE>, 2533 <&iommu_vpp M4U_PORT_L20_JPGENC_BSDMA>; 2534 dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>; 2535 #address-cells = <2>; 2536 #size-cells = <2>; 2537 ranges; 2538 2539 jpgenc@1a030000 { 2540 compatible = "mediatek,mt8195-jpgenc-hw"; 2541 reg = <0 0x1a030000 0 0x10000>; 2542 iommus = <&iommu_vdo M4U_PORT_L19_JPGENC_Y_RDMA>, 2543 <&iommu_vdo M4U_PORT_L19_JPGENC_C_RDMA>, 2544 <&iommu_vdo M4U_PORT_L19_JPGENC_Q_TABLE>, 2545 <&iommu_vdo M4U_PORT_L19_JPGENC_BSDMA>; 2546 interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH 0>; 2547 clocks = <&vencsys CLK_VENC_JPGENC>; 2548 clock-names = "jpgenc"; 2549 power-domains = <&spm MT8195_POWER_DOMAIN_VENC>; 2550 }; 2551 2552 jpgenc@1b030000 { 2553 compatible = "mediatek,mt8195-jpgenc-hw"; 2554 reg = <0 0x1b030000 0 0x10000>; 2555 iommus = <&iommu_vpp M4U_PORT_L20_JPGENC_Y_RDMA>, 2556 <&iommu_vpp M4U_PORT_L20_JPGENC_C_RDMA>, 2557 <&iommu_vpp M4U_PORT_L20_JPGENC_Q_TABLE>, 2558 <&iommu_vpp M4U_PORT_L20_JPGENC_BSDMA>; 2559 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH 0>; 2560 clocks = <&vencsys_core1 CLK_VENC_CORE1_JPGENC>; 2561 clock-names = "jpgenc"; 2562 power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>; 2563 }; 2564 }; 2565 2566 larb20: larb@1b010000 { 2567 compatible = "mediatek,mt8195-smi-larb"; 2568 reg = <0 0x1b010000 0 0x1000>; 2569 mediatek,larb-id = <20>; 2570 mediatek,smi = <&smi_common_vpp>; 2571 clocks = <&vencsys_core1 CLK_VENC_CORE1_LARB>, 2572 <&vencsys_core1 CLK_VENC_CORE1_GALS>, 2573 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>; 2574 clock-names = "apb", "smi", "gals"; 2575 power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>; 2576 }; 2577 2578 ovl0: ovl@1c000000 { 2579 compatible = "mediatek,mt8195-disp-ovl", "mediatek,mt8183-disp-ovl"; 2580 reg = <0 0x1c000000 0 0x1000>; 2581 interrupts = <GIC_SPI 636 IRQ_TYPE_LEVEL_HIGH 0>; 2582 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2583 clocks = <&vdosys0 CLK_VDO0_DISP_OVL0>; 2584 iommus = <&iommu_vdo M4U_PORT_L0_DISP_OVL0_RDMA0>; 2585 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x0000 0x1000>; 2586 }; 2587 2588 rdma0: rdma@1c002000 { 2589 compatible = "mediatek,mt8195-disp-rdma"; 2590 reg = <0 0x1c002000 0 0x1000>; 2591 interrupts = <GIC_SPI 638 IRQ_TYPE_LEVEL_HIGH 0>; 2592 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2593 clocks = <&vdosys0 CLK_VDO0_DISP_RDMA0>; 2594 iommus = <&iommu_vdo M4U_PORT_L0_DISP_RDMA0>; 2595 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x2000 0x1000>; 2596 }; 2597 2598 color0: color@1c003000 { 2599 compatible = "mediatek,mt8195-disp-color", "mediatek,mt8173-disp-color"; 2600 reg = <0 0x1c003000 0 0x1000>; 2601 interrupts = <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH 0>; 2602 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2603 clocks = <&vdosys0 CLK_VDO0_DISP_COLOR0>; 2604 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x3000 0x1000>; 2605 }; 2606 2607 ccorr0: ccorr@1c004000 { 2608 compatible = "mediatek,mt8195-disp-ccorr", "mediatek,mt8192-disp-ccorr"; 2609 reg = <0 0x1c004000 0 0x1000>; 2610 interrupts = <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH 0>; 2611 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2612 clocks = <&vdosys0 CLK_VDO0_DISP_CCORR0>; 2613 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x4000 0x1000>; 2614 }; 2615 2616 aal0: aal@1c005000 { 2617 compatible = "mediatek,mt8195-disp-aal", "mediatek,mt8183-disp-aal"; 2618 reg = <0 0x1c005000 0 0x1000>; 2619 interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH 0>; 2620 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2621 clocks = <&vdosys0 CLK_VDO0_DISP_AAL0>; 2622 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x5000 0x1000>; 2623 }; 2624 2625 gamma0: gamma@1c006000 { 2626 compatible = "mediatek,mt8195-disp-gamma", "mediatek,mt8183-disp-gamma"; 2627 reg = <0 0x1c006000 0 0x1000>; 2628 interrupts = <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH 0>; 2629 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2630 clocks = <&vdosys0 CLK_VDO0_DISP_GAMMA0>; 2631 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x6000 0x1000>; 2632 }; 2633 2634 dither0: dither@1c007000 { 2635 compatible = "mediatek,mt8195-disp-dither", "mediatek,mt8183-disp-dither"; 2636 reg = <0 0x1c007000 0 0x1000>; 2637 interrupts = <GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH 0>; 2638 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2639 clocks = <&vdosys0 CLK_VDO0_DISP_DITHER0>; 2640 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x7000 0x1000>; 2641 }; 2642 2643 dsc0: dsc@1c009000 { 2644 compatible = "mediatek,mt8195-disp-dsc"; 2645 reg = <0 0x1c009000 0 0x1000>; 2646 interrupts = <GIC_SPI 645 IRQ_TYPE_LEVEL_HIGH 0>; 2647 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2648 clocks = <&vdosys0 CLK_VDO0_DSC_WRAP0>; 2649 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x9000 0x1000>; 2650 }; 2651 2652 merge0: merge@1c014000 { 2653 compatible = "mediatek,mt8195-disp-merge"; 2654 reg = <0 0x1c014000 0 0x1000>; 2655 interrupts = <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH 0>; 2656 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2657 clocks = <&vdosys0 CLK_VDO0_VPP_MERGE0>; 2658 mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0x4000 0x1000>; 2659 }; 2660 2661 dp_intf0: dp-intf@1c015000 { 2662 compatible = "mediatek,mt8195-dp-intf"; 2663 reg = <0 0x1c015000 0 0x1000>; 2664 interrupts = <GIC_SPI 657 IRQ_TYPE_LEVEL_HIGH 0>; 2665 clocks = <&vdosys0 CLK_VDO0_DP_INTF0>, 2666 <&vdosys0 CLK_VDO0_DP_INTF0_DP_INTF>, 2667 <&apmixedsys CLK_APMIXED_TVDPLL1>; 2668 clock-names = "engine", "pixel", "pll"; 2669 status = "disabled"; 2670 }; 2671 2672 mutex: mutex@1c016000 { 2673 compatible = "mediatek,mt8195-disp-mutex"; 2674 reg = <0 0x1c016000 0 0x1000>; 2675 interrupts = <GIC_SPI 658 IRQ_TYPE_LEVEL_HIGH 0>; 2676 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2677 clocks = <&vdosys0 CLK_VDO0_DISP_MUTEX0>; 2678 mediatek,gce-events = <CMDQ_EVENT_VDO0_DISP_STREAM_DONE_0>; 2679 }; 2680 2681 larb0: larb@1c018000 { 2682 compatible = "mediatek,mt8195-smi-larb"; 2683 reg = <0 0x1c018000 0 0x1000>; 2684 mediatek,larb-id = <0>; 2685 mediatek,smi = <&smi_common_vdo>; 2686 clocks = <&vdosys0 CLK_VDO0_SMI_LARB>, 2687 <&vdosys0 CLK_VDO0_SMI_LARB>, 2688 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB0>; 2689 clock-names = "apb", "smi", "gals"; 2690 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2691 }; 2692 2693 larb1: larb@1c019000 { 2694 compatible = "mediatek,mt8195-smi-larb"; 2695 reg = <0 0x1c019000 0 0x1000>; 2696 mediatek,larb-id = <1>; 2697 mediatek,smi = <&smi_common_vpp>; 2698 clocks = <&vdosys0 CLK_VDO0_SMI_LARB>, 2699 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>, 2700 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB1>; 2701 clock-names = "apb", "smi", "gals"; 2702 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2703 }; 2704 2705 vdosys1: syscon@1c100000 { 2706 compatible = "mediatek,mt8195-vdosys1", "syscon"; 2707 reg = <0 0x1c100000 0 0x1000>; 2708 mboxes = <&gce0 1 CMDQ_THR_PRIO_4>; 2709 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x0000 0x1000>; 2710 #clock-cells = <1>; 2711 #reset-cells = <1>; 2712 }; 2713 2714 smi_common_vdo: smi@1c01b000 { 2715 compatible = "mediatek,mt8195-smi-common-vdo"; 2716 reg = <0 0x1c01b000 0 0x1000>; 2717 clocks = <&vdosys0 CLK_VDO0_SMI_COMMON>, 2718 <&vdosys0 CLK_VDO0_SMI_EMI>, 2719 <&vdosys0 CLK_VDO0_SMI_RSI>, 2720 <&vdosys0 CLK_VDO0_SMI_GALS>; 2721 clock-names = "apb", "smi", "gals0", "gals1"; 2722 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2723 2724 }; 2725 2726 iommu_vdo: iommu@1c01f000 { 2727 compatible = "mediatek,mt8195-iommu-vdo"; 2728 reg = <0 0x1c01f000 0 0x1000>; 2729 mediatek,larbs = <&larb0 &larb2 &larb5 &larb7 &larb9 2730 &larb10 &larb11 &larb13 &larb17 2731 &larb19 &larb21 &larb24 &larb25 2732 &larb28>; 2733 interrupts = <GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH 0>; 2734 #iommu-cells = <1>; 2735 clocks = <&vdosys0 CLK_VDO0_SMI_IOMMU>; 2736 clock-names = "bclk"; 2737 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2738 }; 2739 2740 mutex1: mutex@1c101000 { 2741 compatible = "mediatek,mt8195-disp-mutex"; 2742 reg = <0 0x1c101000 0 0x1000>; 2743 reg-names = "vdo1_mutex"; 2744 interrupts = <GIC_SPI 494 IRQ_TYPE_LEVEL_HIGH 0>; 2745 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 2746 clocks = <&vdosys1 CLK_VDO1_DISP_MUTEX>; 2747 clock-names = "vdo1_mutex"; 2748 mediatek,gce-events = <CMDQ_EVENT_VDO1_STREAM_DONE_ENG_0>; 2749 }; 2750 2751 larb2: larb@1c102000 { 2752 compatible = "mediatek,mt8195-smi-larb"; 2753 reg = <0 0x1c102000 0 0x1000>; 2754 mediatek,larb-id = <2>; 2755 mediatek,smi = <&smi_common_vdo>; 2756 clocks = <&vdosys1 CLK_VDO1_SMI_LARB2>, 2757 <&vdosys1 CLK_VDO1_SMI_LARB2>, 2758 <&vdosys1 CLK_VDO1_GALS>; 2759 clock-names = "apb", "smi", "gals"; 2760 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 2761 }; 2762 2763 larb3: larb@1c103000 { 2764 compatible = "mediatek,mt8195-smi-larb"; 2765 reg = <0 0x1c103000 0 0x1000>; 2766 mediatek,larb-id = <3>; 2767 mediatek,smi = <&smi_common_vpp>; 2768 clocks = <&vdosys1 CLK_VDO1_SMI_LARB3>, 2769 <&vdosys1 CLK_VDO1_GALS>, 2770 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>; 2771 clock-names = "apb", "smi", "gals"; 2772 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 2773 }; 2774 2775 vdo1_rdma0: rdma@1c104000 { 2776 compatible = "mediatek,mt8195-vdo1-rdma"; 2777 reg = <0 0x1c104000 0 0x1000>; 2778 interrupts = <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH 0>; 2779 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA0>; 2780 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 2781 iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA0>; 2782 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x4000 0x1000>; 2783 }; 2784 2785 vdo1_rdma1: rdma@1c105000 { 2786 compatible = "mediatek,mt8195-vdo1-rdma"; 2787 reg = <0 0x1c105000 0 0x1000>; 2788 interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH 0>; 2789 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA1>; 2790 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 2791 iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA1>; 2792 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x5000 0x1000>; 2793 }; 2794 2795 vdo1_rdma2: rdma@1c106000 { 2796 compatible = "mediatek,mt8195-vdo1-rdma"; 2797 reg = <0 0x1c106000 0 0x1000>; 2798 interrupts = <GIC_SPI 497 IRQ_TYPE_LEVEL_HIGH 0>; 2799 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA2>; 2800 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 2801 iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA2>; 2802 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x6000 0x1000>; 2803 }; 2804 2805 vdo1_rdma3: rdma@1c107000 { 2806 compatible = "mediatek,mt8195-vdo1-rdma"; 2807 reg = <0 0x1c107000 0 0x1000>; 2808 interrupts = <GIC_SPI 498 IRQ_TYPE_LEVEL_HIGH 0>; 2809 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA3>; 2810 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 2811 iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA3>; 2812 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x7000 0x1000>; 2813 }; 2814 2815 vdo1_rdma4: rdma@1c108000 { 2816 compatible = "mediatek,mt8195-vdo1-rdma"; 2817 reg = <0 0x1c108000 0 0x1000>; 2818 interrupts = <GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH 0>; 2819 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA4>; 2820 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 2821 iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA4>; 2822 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x8000 0x1000>; 2823 }; 2824 2825 vdo1_rdma5: rdma@1c109000 { 2826 compatible = "mediatek,mt8195-vdo1-rdma"; 2827 reg = <0 0x1c109000 0 0x1000>; 2828 interrupts = <GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH 0>; 2829 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA5>; 2830 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 2831 iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA5>; 2832 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x9000 0x1000>; 2833 }; 2834 2835 vdo1_rdma6: rdma@1c10a000 { 2836 compatible = "mediatek,mt8195-vdo1-rdma"; 2837 reg = <0 0x1c10a000 0 0x1000>; 2838 interrupts = <GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH 0>; 2839 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA6>; 2840 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 2841 iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA6>; 2842 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xa000 0x1000>; 2843 }; 2844 2845 vdo1_rdma7: rdma@1c10b000 { 2846 compatible = "mediatek,mt8195-vdo1-rdma"; 2847 reg = <0 0x1c10b000 0 0x1000>; 2848 interrupts = <GIC_SPI 502 IRQ_TYPE_LEVEL_HIGH 0>; 2849 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA7>; 2850 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 2851 iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA7>; 2852 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xb000 0x1000>; 2853 }; 2854 2855 merge1: vpp-merge@1c10c000 { 2856 compatible = "mediatek,mt8195-disp-merge"; 2857 reg = <0 0x1c10c000 0 0x1000>; 2858 interrupts = <GIC_SPI 503 IRQ_TYPE_LEVEL_HIGH 0>; 2859 clocks = <&vdosys1 CLK_VDO1_VPP_MERGE0>, 2860 <&vdosys1 CLK_VDO1_MERGE0_DL_ASYNC>; 2861 clock-names = "merge","merge_async"; 2862 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 2863 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xc000 0x1000>; 2864 mediatek,merge-mute = <1>; 2865 resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE0_DL_ASYNC>; 2866 }; 2867 2868 merge2: vpp-merge@1c10d000 { 2869 compatible = "mediatek,mt8195-disp-merge"; 2870 reg = <0 0x1c10d000 0 0x1000>; 2871 interrupts = <GIC_SPI 504 IRQ_TYPE_LEVEL_HIGH 0>; 2872 clocks = <&vdosys1 CLK_VDO1_VPP_MERGE1>, 2873 <&vdosys1 CLK_VDO1_MERGE1_DL_ASYNC>; 2874 clock-names = "merge","merge_async"; 2875 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 2876 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xd000 0x1000>; 2877 mediatek,merge-mute = <1>; 2878 resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE1_DL_ASYNC>; 2879 }; 2880 2881 merge3: vpp-merge@1c10e000 { 2882 compatible = "mediatek,mt8195-disp-merge"; 2883 reg = <0 0x1c10e000 0 0x1000>; 2884 interrupts = <GIC_SPI 505 IRQ_TYPE_LEVEL_HIGH 0>; 2885 clocks = <&vdosys1 CLK_VDO1_VPP_MERGE2>, 2886 <&vdosys1 CLK_VDO1_MERGE2_DL_ASYNC>; 2887 clock-names = "merge","merge_async"; 2888 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 2889 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xe000 0x1000>; 2890 mediatek,merge-mute = <1>; 2891 resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE2_DL_ASYNC>; 2892 }; 2893 2894 merge4: vpp-merge@1c10f000 { 2895 compatible = "mediatek,mt8195-disp-merge"; 2896 reg = <0 0x1c10f000 0 0x1000>; 2897 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH 0>; 2898 clocks = <&vdosys1 CLK_VDO1_VPP_MERGE3>, 2899 <&vdosys1 CLK_VDO1_MERGE3_DL_ASYNC>; 2900 clock-names = "merge","merge_async"; 2901 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 2902 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xf000 0x1000>; 2903 mediatek,merge-mute = <1>; 2904 resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE3_DL_ASYNC>; 2905 }; 2906 2907 merge5: vpp-merge@1c110000 { 2908 compatible = "mediatek,mt8195-disp-merge"; 2909 reg = <0 0x1c110000 0 0x1000>; 2910 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH 0>; 2911 clocks = <&vdosys1 CLK_VDO1_VPP_MERGE4>, 2912 <&vdosys1 CLK_VDO1_MERGE4_DL_ASYNC>; 2913 clock-names = "merge","merge_async"; 2914 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 2915 mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0x0000 0x1000>; 2916 mediatek,merge-fifo-en = <1>; 2917 resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE4_DL_ASYNC>; 2918 }; 2919 2920 dp_intf1: dp-intf@1c113000 { 2921 compatible = "mediatek,mt8195-dp-intf"; 2922 reg = <0 0x1c113000 0 0x1000>; 2923 interrupts = <GIC_SPI 513 IRQ_TYPE_LEVEL_HIGH 0>; 2924 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 2925 clocks = <&vdosys1 CLK_VDO1_DP_INTF0_MM>, 2926 <&vdosys1 CLK_VDO1_DPINTF>, 2927 <&apmixedsys CLK_APMIXED_TVDPLL2>; 2928 clock-names = "engine", "pixel", "pll"; 2929 status = "disabled"; 2930 }; 2931 2932 ethdr0: hdr-engine@1c114000 { 2933 compatible = "mediatek,mt8195-disp-ethdr"; 2934 reg = <0 0x1c114000 0 0x1000>, 2935 <0 0x1c115000 0 0x1000>, 2936 <0 0x1c117000 0 0x1000>, 2937 <0 0x1c119000 0 0x1000>, 2938 <0 0x1c11a000 0 0x1000>, 2939 <0 0x1c11b000 0 0x1000>, 2940 <0 0x1c11c000 0 0x1000>; 2941 reg-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1", 2942 "vdo_be", "adl_ds"; 2943 mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0x4000 0x1000>, 2944 <&gce0 SUBSYS_1c11XXXX 0x5000 0x1000>, 2945 <&gce0 SUBSYS_1c11XXXX 0x7000 0x1000>, 2946 <&gce0 SUBSYS_1c11XXXX 0x9000 0x1000>, 2947 <&gce0 SUBSYS_1c11XXXX 0xa000 0x1000>, 2948 <&gce0 SUBSYS_1c11XXXX 0xb000 0x1000>, 2949 <&gce0 SUBSYS_1c11XXXX 0xc000 0x1000>; 2950 clocks = <&vdosys1 CLK_VDO1_DISP_MIXER>, 2951 <&vdosys1 CLK_VDO1_HDR_VDO_FE0>, 2952 <&vdosys1 CLK_VDO1_HDR_VDO_FE1>, 2953 <&vdosys1 CLK_VDO1_HDR_GFX_FE0>, 2954 <&vdosys1 CLK_VDO1_HDR_GFX_FE1>, 2955 <&vdosys1 CLK_VDO1_HDR_VDO_BE>, 2956 <&vdosys1 CLK_VDO1_26M_SLOW>, 2957 <&vdosys1 CLK_VDO1_HDR_VDO_FE0_DL_ASYNC>, 2958 <&vdosys1 CLK_VDO1_HDR_VDO_FE1_DL_ASYNC>, 2959 <&vdosys1 CLK_VDO1_HDR_GFX_FE0_DL_ASYNC>, 2960 <&vdosys1 CLK_VDO1_HDR_GFX_FE1_DL_ASYNC>, 2961 <&vdosys1 CLK_VDO1_HDR_VDO_BE_DL_ASYNC>, 2962 <&topckgen CLK_TOP_ETHDR>; 2963 clock-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1", 2964 "vdo_be", "adl_ds", "vdo_fe0_async", "vdo_fe1_async", 2965 "gfx_fe0_async", "gfx_fe1_async","vdo_be_async", 2966 "ethdr_top"; 2967 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 2968 iommus = <&iommu_vpp M4U_PORT_L3_HDR_DS>, 2969 <&iommu_vpp M4U_PORT_L3_HDR_ADL>; 2970 interrupts = <GIC_SPI 517 IRQ_TYPE_LEVEL_HIGH 0>; /* disp mixer */ 2971 resets = <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE0_DL_ASYNC>, 2972 <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE1_DL_ASYNC>, 2973 <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE0_DL_ASYNC>, 2974 <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE1_DL_ASYNC>, 2975 <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_BE_DL_ASYNC>; 2976 reset-names = "vdo_fe0_async", "vdo_fe1_async", "gfx_fe0_async", 2977 "gfx_fe1_async", "vdo_be_async"; 2978 }; 2979 2980 edp_tx: edp-tx@1c500000 { 2981 compatible = "mediatek,mt8195-edp-tx"; 2982 reg = <0 0x1c500000 0 0x8000>; 2983 nvmem-cells = <&dp_calibration>; 2984 nvmem-cell-names = "dp_calibration_data"; 2985 power-domains = <&spm MT8195_POWER_DOMAIN_EPD_TX>; 2986 interrupts = <GIC_SPI 676 IRQ_TYPE_LEVEL_HIGH 0>; 2987 max-linkrate-mhz = <8100>; 2988 status = "disabled"; 2989 }; 2990 2991 dp_tx: dp-tx@1c600000 { 2992 compatible = "mediatek,mt8195-dp-tx"; 2993 reg = <0 0x1c600000 0 0x8000>; 2994 nvmem-cells = <&dp_calibration>; 2995 nvmem-cell-names = "dp_calibration_data"; 2996 power-domains = <&spm MT8195_POWER_DOMAIN_DP_TX>; 2997 interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH 0>; 2998 max-linkrate-mhz = <8100>; 2999 status = "disabled"; 3000 }; 3001 }; 3002 3003 thermal_zones: thermal-zones { 3004 cpu0-thermal { 3005 polling-delay = <0>; 3006 polling-delay-passive = <0>; 3007 thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU0>; 3008 trips { 3009 cpu0_crit: trip-crit { 3010 temperature = <100000>; 3011 hysteresis = <2000>; 3012 type = "critical"; 3013 }; 3014 }; 3015 }; 3016 3017 cpu1-thermal { 3018 polling-delay = <0>; 3019 polling-delay-passive = <0>; 3020 thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU1>; 3021 trips { 3022 cpu1_crit: trip-crit { 3023 temperature = <100000>; 3024 hysteresis = <2000>; 3025 type = "critical"; 3026 }; 3027 }; 3028 }; 3029 3030 cpu2-thermal { 3031 polling-delay = <0>; 3032 polling-delay-passive = <0>; 3033 thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU2>; 3034 trips { 3035 cpu2_crit: trip-crit { 3036 temperature = <100000>; 3037 hysteresis = <2000>; 3038 type = "critical"; 3039 }; 3040 }; 3041 }; 3042 3043 cpu3-thermal { 3044 polling-delay = <0>; 3045 polling-delay-passive = <0>; 3046 thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU3>; 3047 trips { 3048 cpu3_crit: trip-crit { 3049 temperature = <100000>; 3050 hysteresis = <2000>; 3051 type = "critical"; 3052 }; 3053 }; 3054 }; 3055 3056 cpu4-thermal { 3057 polling-delay = <0>; 3058 polling-delay-passive = <0>; 3059 thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU0>; 3060 trips { 3061 cpu4_crit: trip-crit { 3062 temperature = <100000>; 3063 hysteresis = <2000>; 3064 type = "critical"; 3065 }; 3066 }; 3067 }; 3068 3069 cpu5-thermal { 3070 polling-delay = <0>; 3071 polling-delay-passive = <0>; 3072 thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU1>; 3073 trips { 3074 cpu5_crit: trip-crit { 3075 temperature = <100000>; 3076 hysteresis = <2000>; 3077 type = "critical"; 3078 }; 3079 }; 3080 }; 3081 3082 cpu6-thermal { 3083 polling-delay = <0>; 3084 polling-delay-passive = <0>; 3085 thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU2>; 3086 trips { 3087 cpu6_crit: trip-crit { 3088 temperature = <100000>; 3089 hysteresis = <2000>; 3090 type = "critical"; 3091 }; 3092 }; 3093 }; 3094 3095 cpu7-thermal { 3096 polling-delay = <0>; 3097 polling-delay-passive = <0>; 3098 thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU3>; 3099 trips { 3100 cpu7_crit: trip-crit { 3101 temperature = <100000>; 3102 hysteresis = <2000>; 3103 type = "critical"; 3104 }; 3105 }; 3106 }; 3107 }; 3108}; 3109