mt8195.dtsi (e39e72cffea3288d3b1f27e0e05ce6c2d18b8735) mt8195.dtsi (6aa5b46d1755a2e3db86fa6bd3f3d15d3c012594)
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (c) 2021 MediaTek Inc.
4 * Author: Seiya Wang <seiya.wang@mediatek.com>
5 */
6
7/dts-v1/;
8#include <dt-bindings/clock/mt8195-clk.h>

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978 };
979
980 mfgcfg: clock-controller@13fbf000 {
981 compatible = "mediatek,mt8195-mfgcfg";
982 reg = <0 0x13fbf000 0 0x1000>;
983 #clock-cells = <1>;
984 };
985
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (c) 2021 MediaTek Inc.
4 * Author: Seiya Wang <seiya.wang@mediatek.com>
5 */
6
7/dts-v1/;
8#include <dt-bindings/clock/mt8195-clk.h>

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978 };
979
980 mfgcfg: clock-controller@13fbf000 {
981 compatible = "mediatek,mt8195-mfgcfg";
982 reg = <0 0x13fbf000 0 0x1000>;
983 #clock-cells = <1>;
984 };
985
986 vppsys0: clock-controller@14000000 {
987 compatible = "mediatek,mt8195-vppsys0";
988 reg = <0 0x14000000 0 0x1000>;
989 #clock-cells = <1>;
990 };
991
986 wpesys: clock-controller@14e00000 {
987 compatible = "mediatek,mt8195-wpesys";
988 reg = <0 0x14e00000 0 0x1000>;
989 #clock-cells = <1>;
990 };
991
992 wpesys_vpp0: clock-controller@14e02000 {
993 compatible = "mediatek,mt8195-wpesys_vpp0";
994 reg = <0 0x14e02000 0 0x1000>;
995 #clock-cells = <1>;
996 };
997
998 wpesys_vpp1: clock-controller@14e03000 {
999 compatible = "mediatek,mt8195-wpesys_vpp1";
1000 reg = <0 0x14e03000 0 0x1000>;
1001 #clock-cells = <1>;
1002 };
1003
992 wpesys: clock-controller@14e00000 {
993 compatible = "mediatek,mt8195-wpesys";
994 reg = <0 0x14e00000 0 0x1000>;
995 #clock-cells = <1>;
996 };
997
998 wpesys_vpp0: clock-controller@14e02000 {
999 compatible = "mediatek,mt8195-wpesys_vpp0";
1000 reg = <0 0x14e02000 0 0x1000>;
1001 #clock-cells = <1>;
1002 };
1003
1004 wpesys_vpp1: clock-controller@14e03000 {
1005 compatible = "mediatek,mt8195-wpesys_vpp1";
1006 reg = <0 0x14e03000 0 0x1000>;
1007 #clock-cells = <1>;
1008 };
1009
1010 vppsys1: clock-controller@14f00000 {
1011 compatible = "mediatek,mt8195-vppsys1";
1012 reg = <0 0x14f00000 0 0x1000>;
1013 #clock-cells = <1>;
1014 };
1015
1004 imgsys: clock-controller@15000000 {
1005 compatible = "mediatek,mt8195-imgsys";
1006 reg = <0 0x15000000 0 0x1000>;
1007 #clock-cells = <1>;
1008 };
1009
1010 imgsys1_dip_top: clock-controller@15110000 {
1011 compatible = "mediatek,mt8195-imgsys1_dip_top";

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1103 #clock-cells = <1>;
1104 };
1105
1106 vencsys_core1: clock-controller@1b000000 {
1107 compatible = "mediatek,mt8195-vencsys_core1";
1108 reg = <0 0x1b000000 0 0x1000>;
1109 #clock-cells = <1>;
1110 };
1016 imgsys: clock-controller@15000000 {
1017 compatible = "mediatek,mt8195-imgsys";
1018 reg = <0 0x15000000 0 0x1000>;
1019 #clock-cells = <1>;
1020 };
1021
1022 imgsys1_dip_top: clock-controller@15110000 {
1023 compatible = "mediatek,mt8195-imgsys1_dip_top";

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1115 #clock-cells = <1>;
1116 };
1117
1118 vencsys_core1: clock-controller@1b000000 {
1119 compatible = "mediatek,mt8195-vencsys_core1";
1120 reg = <0 0x1b000000 0 0x1000>;
1121 #clock-cells = <1>;
1122 };
1123
1124 vdosys0: syscon@1c01a000 {
1125 compatible = "mediatek,mt8195-mmsys", "syscon";
1126 reg = <0 0x1c01a000 0 0x1000>;
1127 #clock-cells = <1>;
1128 };
1129
1130 vdosys1: syscon@1c100000 {
1131 compatible = "mediatek,mt8195-mmsys", "syscon";
1132 reg = <0 0x1c100000 0 0x1000>;
1133 #clock-cells = <1>;
1134 };
1111 };
1112};
1135 };
1136};