mt8195.dtsi (cc4f0b13a887b483faa45084616998a21b63889d) mt8195.dtsi (66fe2431faa227e75a16c2ee2f90b2bb6665b2b3)
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (c) 2021 MediaTek Inc.
4 * Author: Seiya Wang <seiya.wang@mediatek.com>
5 */
6
7/dts-v1/;
8#include <dt-bindings/clock/mt8195-clk.h>

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33 cpu0: cpu@0 {
34 device_type = "cpu";
35 compatible = "arm,cortex-a55";
36 reg = <0x000>;
37 enable-method = "psci";
38 performance-domains = <&performance 0>;
39 clock-frequency = <1701000000>;
40 capacity-dmips-mhz = <308>;
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (c) 2021 MediaTek Inc.
4 * Author: Seiya Wang <seiya.wang@mediatek.com>
5 */
6
7/dts-v1/;
8#include <dt-bindings/clock/mt8195-clk.h>

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33 cpu0: cpu@0 {
34 device_type = "cpu";
35 compatible = "arm,cortex-a55";
36 reg = <0x000>;
37 enable-method = "psci";
38 performance-domains = <&performance 0>;
39 clock-frequency = <1701000000>;
40 capacity-dmips-mhz = <308>;
41 cpu-idle-states = <&cpu_off_l &cluster_off_l>;
41 cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
42 i-cache-size = <32768>;
43 i-cache-line-size = <64>;
44 i-cache-sets = <128>;
45 d-cache-size = <32768>;
46 d-cache-line-size = <64>;
47 d-cache-sets = <128>;
48 next-level-cache = <&l2_0>;
49 #cooling-cells = <2>;
50 };
51
52 cpu1: cpu@100 {
53 device_type = "cpu";
54 compatible = "arm,cortex-a55";
55 reg = <0x100>;
56 enable-method = "psci";
57 performance-domains = <&performance 0>;
58 clock-frequency = <1701000000>;
59 capacity-dmips-mhz = <308>;
42 i-cache-size = <32768>;
43 i-cache-line-size = <64>;
44 i-cache-sets = <128>;
45 d-cache-size = <32768>;
46 d-cache-line-size = <64>;
47 d-cache-sets = <128>;
48 next-level-cache = <&l2_0>;
49 #cooling-cells = <2>;
50 };
51
52 cpu1: cpu@100 {
53 device_type = "cpu";
54 compatible = "arm,cortex-a55";
55 reg = <0x100>;
56 enable-method = "psci";
57 performance-domains = <&performance 0>;
58 clock-frequency = <1701000000>;
59 capacity-dmips-mhz = <308>;
60 cpu-idle-states = <&cpu_off_l &cluster_off_l>;
60 cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
61 i-cache-size = <32768>;
62 i-cache-line-size = <64>;
63 i-cache-sets = <128>;
64 d-cache-size = <32768>;
65 d-cache-line-size = <64>;
66 d-cache-sets = <128>;
67 next-level-cache = <&l2_0>;
68 #cooling-cells = <2>;
69 };
70
71 cpu2: cpu@200 {
72 device_type = "cpu";
73 compatible = "arm,cortex-a55";
74 reg = <0x200>;
75 enable-method = "psci";
76 performance-domains = <&performance 0>;
77 clock-frequency = <1701000000>;
78 capacity-dmips-mhz = <308>;
61 i-cache-size = <32768>;
62 i-cache-line-size = <64>;
63 i-cache-sets = <128>;
64 d-cache-size = <32768>;
65 d-cache-line-size = <64>;
66 d-cache-sets = <128>;
67 next-level-cache = <&l2_0>;
68 #cooling-cells = <2>;
69 };
70
71 cpu2: cpu@200 {
72 device_type = "cpu";
73 compatible = "arm,cortex-a55";
74 reg = <0x200>;
75 enable-method = "psci";
76 performance-domains = <&performance 0>;
77 clock-frequency = <1701000000>;
78 capacity-dmips-mhz = <308>;
79 cpu-idle-states = <&cpu_off_l &cluster_off_l>;
79 cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
80 i-cache-size = <32768>;
81 i-cache-line-size = <64>;
82 i-cache-sets = <128>;
83 d-cache-size = <32768>;
84 d-cache-line-size = <64>;
85 d-cache-sets = <128>;
86 next-level-cache = <&l2_0>;
87 #cooling-cells = <2>;
88 };
89
90 cpu3: cpu@300 {
91 device_type = "cpu";
92 compatible = "arm,cortex-a55";
93 reg = <0x300>;
94 enable-method = "psci";
95 performance-domains = <&performance 0>;
96 clock-frequency = <1701000000>;
97 capacity-dmips-mhz = <308>;
80 i-cache-size = <32768>;
81 i-cache-line-size = <64>;
82 i-cache-sets = <128>;
83 d-cache-size = <32768>;
84 d-cache-line-size = <64>;
85 d-cache-sets = <128>;
86 next-level-cache = <&l2_0>;
87 #cooling-cells = <2>;
88 };
89
90 cpu3: cpu@300 {
91 device_type = "cpu";
92 compatible = "arm,cortex-a55";
93 reg = <0x300>;
94 enable-method = "psci";
95 performance-domains = <&performance 0>;
96 clock-frequency = <1701000000>;
97 capacity-dmips-mhz = <308>;
98 cpu-idle-states = <&cpu_off_l &cluster_off_l>;
98 cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
99 i-cache-size = <32768>;
100 i-cache-line-size = <64>;
101 i-cache-sets = <128>;
102 d-cache-size = <32768>;
103 d-cache-line-size = <64>;
104 d-cache-sets = <128>;
105 next-level-cache = <&l2_0>;
106 #cooling-cells = <2>;
107 };
108
109 cpu4: cpu@400 {
110 device_type = "cpu";
111 compatible = "arm,cortex-a78";
112 reg = <0x400>;
113 enable-method = "psci";
114 performance-domains = <&performance 1>;
115 clock-frequency = <2171000000>;
116 capacity-dmips-mhz = <1024>;
99 i-cache-size = <32768>;
100 i-cache-line-size = <64>;
101 i-cache-sets = <128>;
102 d-cache-size = <32768>;
103 d-cache-line-size = <64>;
104 d-cache-sets = <128>;
105 next-level-cache = <&l2_0>;
106 #cooling-cells = <2>;
107 };
108
109 cpu4: cpu@400 {
110 device_type = "cpu";
111 compatible = "arm,cortex-a78";
112 reg = <0x400>;
113 enable-method = "psci";
114 performance-domains = <&performance 1>;
115 clock-frequency = <2171000000>;
116 capacity-dmips-mhz = <1024>;
117 cpu-idle-states = <&cpu_off_b &cluster_off_b>;
117 cpu-idle-states = <&cpu_ret_b &cpu_off_b>;
118 i-cache-size = <65536>;
119 i-cache-line-size = <64>;
120 i-cache-sets = <256>;
121 d-cache-size = <65536>;
122 d-cache-line-size = <64>;
123 d-cache-sets = <256>;
124 next-level-cache = <&l2_1>;
125 #cooling-cells = <2>;
126 };
127
128 cpu5: cpu@500 {
129 device_type = "cpu";
130 compatible = "arm,cortex-a78";
131 reg = <0x500>;
132 enable-method = "psci";
133 performance-domains = <&performance 1>;
134 clock-frequency = <2171000000>;
135 capacity-dmips-mhz = <1024>;
118 i-cache-size = <65536>;
119 i-cache-line-size = <64>;
120 i-cache-sets = <256>;
121 d-cache-size = <65536>;
122 d-cache-line-size = <64>;
123 d-cache-sets = <256>;
124 next-level-cache = <&l2_1>;
125 #cooling-cells = <2>;
126 };
127
128 cpu5: cpu@500 {
129 device_type = "cpu";
130 compatible = "arm,cortex-a78";
131 reg = <0x500>;
132 enable-method = "psci";
133 performance-domains = <&performance 1>;
134 clock-frequency = <2171000000>;
135 capacity-dmips-mhz = <1024>;
136 cpu-idle-states = <&cpu_off_b &cluster_off_b>;
136 cpu-idle-states = <&cpu_ret_b &cpu_off_b>;
137 i-cache-size = <65536>;
138 i-cache-line-size = <64>;
139 i-cache-sets = <256>;
140 d-cache-size = <65536>;
141 d-cache-line-size = <64>;
142 d-cache-sets = <256>;
143 next-level-cache = <&l2_1>;
144 #cooling-cells = <2>;
145 };
146
147 cpu6: cpu@600 {
148 device_type = "cpu";
149 compatible = "arm,cortex-a78";
150 reg = <0x600>;
151 enable-method = "psci";
152 performance-domains = <&performance 1>;
153 clock-frequency = <2171000000>;
154 capacity-dmips-mhz = <1024>;
137 i-cache-size = <65536>;
138 i-cache-line-size = <64>;
139 i-cache-sets = <256>;
140 d-cache-size = <65536>;
141 d-cache-line-size = <64>;
142 d-cache-sets = <256>;
143 next-level-cache = <&l2_1>;
144 #cooling-cells = <2>;
145 };
146
147 cpu6: cpu@600 {
148 device_type = "cpu";
149 compatible = "arm,cortex-a78";
150 reg = <0x600>;
151 enable-method = "psci";
152 performance-domains = <&performance 1>;
153 clock-frequency = <2171000000>;
154 capacity-dmips-mhz = <1024>;
155 cpu-idle-states = <&cpu_off_b &cluster_off_b>;
155 cpu-idle-states = <&cpu_ret_b &cpu_off_b>;
156 i-cache-size = <65536>;
157 i-cache-line-size = <64>;
158 i-cache-sets = <256>;
159 d-cache-size = <65536>;
160 d-cache-line-size = <64>;
161 d-cache-sets = <256>;
162 next-level-cache = <&l2_1>;
163 #cooling-cells = <2>;
164 };
165
166 cpu7: cpu@700 {
167 device_type = "cpu";
168 compatible = "arm,cortex-a78";
169 reg = <0x700>;
170 enable-method = "psci";
171 performance-domains = <&performance 1>;
172 clock-frequency = <2171000000>;
173 capacity-dmips-mhz = <1024>;
156 i-cache-size = <65536>;
157 i-cache-line-size = <64>;
158 i-cache-sets = <256>;
159 d-cache-size = <65536>;
160 d-cache-line-size = <64>;
161 d-cache-sets = <256>;
162 next-level-cache = <&l2_1>;
163 #cooling-cells = <2>;
164 };
165
166 cpu7: cpu@700 {
167 device_type = "cpu";
168 compatible = "arm,cortex-a78";
169 reg = <0x700>;
170 enable-method = "psci";
171 performance-domains = <&performance 1>;
172 clock-frequency = <2171000000>;
173 capacity-dmips-mhz = <1024>;
174 cpu-idle-states = <&cpu_off_b &cluster_off_b>;
174 cpu-idle-states = <&cpu_ret_b &cpu_off_b>;
175 i-cache-size = <65536>;
176 i-cache-line-size = <64>;
177 i-cache-sets = <256>;
178 d-cache-size = <65536>;
179 d-cache-line-size = <64>;
180 d-cache-sets = <256>;
181 next-level-cache = <&l2_1>;
182 #cooling-cells = <2>;

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216 cpu = <&cpu7>;
217 };
218 };
219 };
220
221 idle-states {
222 entry-method = "psci";
223
175 i-cache-size = <65536>;
176 i-cache-line-size = <64>;
177 i-cache-sets = <256>;
178 d-cache-size = <65536>;
179 d-cache-line-size = <64>;
180 d-cache-sets = <256>;
181 next-level-cache = <&l2_1>;
182 #cooling-cells = <2>;

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216 cpu = <&cpu7>;
217 };
218 };
219 };
220
221 idle-states {
222 entry-method = "psci";
223
224 cpu_off_l: cpu-off-l {
224 cpu_ret_l: cpu-retention-l {
225 compatible = "arm,idle-state";
226 arm,psci-suspend-param = <0x00010001>;
227 local-timer-stop;
228 entry-latency-us = <50>;
229 exit-latency-us = <95>;
230 min-residency-us = <580>;
231 };
232
225 compatible = "arm,idle-state";
226 arm,psci-suspend-param = <0x00010001>;
227 local-timer-stop;
228 entry-latency-us = <50>;
229 exit-latency-us = <95>;
230 min-residency-us = <580>;
231 };
232
233 cpu_off_b: cpu-off-b {
233 cpu_ret_b: cpu-retention-b {
234 compatible = "arm,idle-state";
235 arm,psci-suspend-param = <0x00010001>;
236 local-timer-stop;
237 entry-latency-us = <45>;
238 exit-latency-us = <140>;
239 min-residency-us = <740>;
240 };
241
234 compatible = "arm,idle-state";
235 arm,psci-suspend-param = <0x00010001>;
236 local-timer-stop;
237 entry-latency-us = <45>;
238 exit-latency-us = <140>;
239 min-residency-us = <740>;
240 };
241
242 cluster_off_l: cluster-off-l {
242 cpu_off_l: cpu-off-l {
243 compatible = "arm,idle-state";
244 arm,psci-suspend-param = <0x01010002>;
245 local-timer-stop;
246 entry-latency-us = <55>;
247 exit-latency-us = <155>;
248 min-residency-us = <840>;
249 };
250
243 compatible = "arm,idle-state";
244 arm,psci-suspend-param = <0x01010002>;
245 local-timer-stop;
246 entry-latency-us = <55>;
247 exit-latency-us = <155>;
248 min-residency-us = <840>;
249 };
250
251 cluster_off_b: cluster-off-b {
251 cpu_off_b: cpu-off-b {
252 compatible = "arm,idle-state";
253 arm,psci-suspend-param = <0x01010002>;
254 local-timer-stop;
255 entry-latency-us = <50>;
256 exit-latency-us = <200>;
257 min-residency-us = <1000>;
258 };
259 };

--- 2389 unchanged lines hidden --- 		252 compatible = "arm,idle-state";
253 arm,psci-suspend-param = <0x01010002>;
254 local-timer-stop;
255 entry-latency-us = <50>;
256 exit-latency-us = <200>;
257 min-residency-us = <1000>;
258 };
259 };

--- 2389 unchanged lines hidden ---