1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (c) 2021 MediaTek Inc. 4 * Author: Seiya Wang <seiya.wang@mediatek.com> 5 */ 6 7/dts-v1/; 8#include <dt-bindings/clock/mt8195-clk.h> 9#include <dt-bindings/gce/mt8195-gce.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/interrupt-controller/irq.h> 12#include <dt-bindings/memory/mt8195-memory-port.h> 13#include <dt-bindings/phy/phy.h> 14#include <dt-bindings/pinctrl/mt8195-pinfunc.h> 15#include <dt-bindings/power/mt8195-power.h> 16#include <dt-bindings/reset/mt8195-resets.h> 17 18/ { 19 compatible = "mediatek,mt8195"; 20 interrupt-parent = <&gic>; 21 #address-cells = <2>; 22 #size-cells = <2>; 23 24 aliases { 25 gce0 = &gce0; 26 gce1 = &gce1; 27 }; 28 29 cpus { 30 #address-cells = <1>; 31 #size-cells = <0>; 32 33 cpu0: cpu@0 { 34 device_type = "cpu"; 35 compatible = "arm,cortex-a55"; 36 reg = <0x000>; 37 enable-method = "psci"; 38 performance-domains = <&performance 0>; 39 clock-frequency = <1701000000>; 40 capacity-dmips-mhz = <308>; 41 cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 42 i-cache-size = <32768>; 43 i-cache-line-size = <64>; 44 i-cache-sets = <128>; 45 d-cache-size = <32768>; 46 d-cache-line-size = <64>; 47 d-cache-sets = <128>; 48 next-level-cache = <&l2_0>; 49 #cooling-cells = <2>; 50 }; 51 52 cpu1: cpu@100 { 53 device_type = "cpu"; 54 compatible = "arm,cortex-a55"; 55 reg = <0x100>; 56 enable-method = "psci"; 57 performance-domains = <&performance 0>; 58 clock-frequency = <1701000000>; 59 capacity-dmips-mhz = <308>; 60 cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 61 i-cache-size = <32768>; 62 i-cache-line-size = <64>; 63 i-cache-sets = <128>; 64 d-cache-size = <32768>; 65 d-cache-line-size = <64>; 66 d-cache-sets = <128>; 67 next-level-cache = <&l2_0>; 68 #cooling-cells = <2>; 69 }; 70 71 cpu2: cpu@200 { 72 device_type = "cpu"; 73 compatible = "arm,cortex-a55"; 74 reg = <0x200>; 75 enable-method = "psci"; 76 performance-domains = <&performance 0>; 77 clock-frequency = <1701000000>; 78 capacity-dmips-mhz = <308>; 79 cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 80 i-cache-size = <32768>; 81 i-cache-line-size = <64>; 82 i-cache-sets = <128>; 83 d-cache-size = <32768>; 84 d-cache-line-size = <64>; 85 d-cache-sets = <128>; 86 next-level-cache = <&l2_0>; 87 #cooling-cells = <2>; 88 }; 89 90 cpu3: cpu@300 { 91 device_type = "cpu"; 92 compatible = "arm,cortex-a55"; 93 reg = <0x300>; 94 enable-method = "psci"; 95 performance-domains = <&performance 0>; 96 clock-frequency = <1701000000>; 97 capacity-dmips-mhz = <308>; 98 cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 99 i-cache-size = <32768>; 100 i-cache-line-size = <64>; 101 i-cache-sets = <128>; 102 d-cache-size = <32768>; 103 d-cache-line-size = <64>; 104 d-cache-sets = <128>; 105 next-level-cache = <&l2_0>; 106 #cooling-cells = <2>; 107 }; 108 109 cpu4: cpu@400 { 110 device_type = "cpu"; 111 compatible = "arm,cortex-a78"; 112 reg = <0x400>; 113 enable-method = "psci"; 114 performance-domains = <&performance 1>; 115 clock-frequency = <2171000000>; 116 capacity-dmips-mhz = <1024>; 117 cpu-idle-states = <&cpu_ret_b &cpu_off_b>; 118 i-cache-size = <65536>; 119 i-cache-line-size = <64>; 120 i-cache-sets = <256>; 121 d-cache-size = <65536>; 122 d-cache-line-size = <64>; 123 d-cache-sets = <256>; 124 next-level-cache = <&l2_1>; 125 #cooling-cells = <2>; 126 }; 127 128 cpu5: cpu@500 { 129 device_type = "cpu"; 130 compatible = "arm,cortex-a78"; 131 reg = <0x500>; 132 enable-method = "psci"; 133 performance-domains = <&performance 1>; 134 clock-frequency = <2171000000>; 135 capacity-dmips-mhz = <1024>; 136 cpu-idle-states = <&cpu_ret_b &cpu_off_b>; 137 i-cache-size = <65536>; 138 i-cache-line-size = <64>; 139 i-cache-sets = <256>; 140 d-cache-size = <65536>; 141 d-cache-line-size = <64>; 142 d-cache-sets = <256>; 143 next-level-cache = <&l2_1>; 144 #cooling-cells = <2>; 145 }; 146 147 cpu6: cpu@600 { 148 device_type = "cpu"; 149 compatible = "arm,cortex-a78"; 150 reg = <0x600>; 151 enable-method = "psci"; 152 performance-domains = <&performance 1>; 153 clock-frequency = <2171000000>; 154 capacity-dmips-mhz = <1024>; 155 cpu-idle-states = <&cpu_ret_b &cpu_off_b>; 156 i-cache-size = <65536>; 157 i-cache-line-size = <64>; 158 i-cache-sets = <256>; 159 d-cache-size = <65536>; 160 d-cache-line-size = <64>; 161 d-cache-sets = <256>; 162 next-level-cache = <&l2_1>; 163 #cooling-cells = <2>; 164 }; 165 166 cpu7: cpu@700 { 167 device_type = "cpu"; 168 compatible = "arm,cortex-a78"; 169 reg = <0x700>; 170 enable-method = "psci"; 171 performance-domains = <&performance 1>; 172 clock-frequency = <2171000000>; 173 capacity-dmips-mhz = <1024>; 174 cpu-idle-states = <&cpu_ret_b &cpu_off_b>; 175 i-cache-size = <65536>; 176 i-cache-line-size = <64>; 177 i-cache-sets = <256>; 178 d-cache-size = <65536>; 179 d-cache-line-size = <64>; 180 d-cache-sets = <256>; 181 next-level-cache = <&l2_1>; 182 #cooling-cells = <2>; 183 }; 184 185 cpu-map { 186 cluster0 { 187 core0 { 188 cpu = <&cpu0>; 189 }; 190 191 core1 { 192 cpu = <&cpu1>; 193 }; 194 195 core2 { 196 cpu = <&cpu2>; 197 }; 198 199 core3 { 200 cpu = <&cpu3>; 201 }; 202 203 core4 { 204 cpu = <&cpu4>; 205 }; 206 207 core5 { 208 cpu = <&cpu5>; 209 }; 210 211 core6 { 212 cpu = <&cpu6>; 213 }; 214 215 core7 { 216 cpu = <&cpu7>; 217 }; 218 }; 219 }; 220 221 idle-states { 222 entry-method = "psci"; 223 224 cpu_ret_l: cpu-retention-l { 225 compatible = "arm,idle-state"; 226 arm,psci-suspend-param = <0x00010001>; 227 local-timer-stop; 228 entry-latency-us = <50>; 229 exit-latency-us = <95>; 230 min-residency-us = <580>; 231 }; 232 233 cpu_ret_b: cpu-retention-b { 234 compatible = "arm,idle-state"; 235 arm,psci-suspend-param = <0x00010001>; 236 local-timer-stop; 237 entry-latency-us = <45>; 238 exit-latency-us = <140>; 239 min-residency-us = <740>; 240 }; 241 242 cpu_off_l: cpu-off-l { 243 compatible = "arm,idle-state"; 244 arm,psci-suspend-param = <0x01010002>; 245 local-timer-stop; 246 entry-latency-us = <55>; 247 exit-latency-us = <155>; 248 min-residency-us = <840>; 249 }; 250 251 cpu_off_b: cpu-off-b { 252 compatible = "arm,idle-state"; 253 arm,psci-suspend-param = <0x01010002>; 254 local-timer-stop; 255 entry-latency-us = <50>; 256 exit-latency-us = <200>; 257 min-residency-us = <1000>; 258 }; 259 }; 260 261 l2_0: l2-cache0 { 262 compatible = "cache"; 263 cache-level = <2>; 264 cache-size = <131072>; 265 cache-line-size = <64>; 266 cache-sets = <512>; 267 next-level-cache = <&l3_0>; 268 }; 269 270 l2_1: l2-cache1 { 271 compatible = "cache"; 272 cache-level = <2>; 273 cache-size = <262144>; 274 cache-line-size = <64>; 275 cache-sets = <512>; 276 next-level-cache = <&l3_0>; 277 }; 278 279 l3_0: l3-cache { 280 compatible = "cache"; 281 cache-level = <3>; 282 cache-size = <2097152>; 283 cache-line-size = <64>; 284 cache-sets = <2048>; 285 cache-unified; 286 }; 287 }; 288 289 dsu-pmu { 290 compatible = "arm,dsu-pmu"; 291 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>; 292 cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>, 293 <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>; 294 }; 295 296 dmic_codec: dmic-codec { 297 compatible = "dmic-codec"; 298 num-channels = <2>; 299 wakeup-delay-ms = <50>; 300 }; 301 302 sound: mt8195-sound { 303 mediatek,platform = <&afe>; 304 status = "disabled"; 305 }; 306 307 clk13m: fixed-factor-clock-13m { 308 compatible = "fixed-factor-clock"; 309 #clock-cells = <0>; 310 clocks = <&clk26m>; 311 clock-div = <2>; 312 clock-mult = <1>; 313 clock-output-names = "clk13m"; 314 }; 315 316 clk26m: oscillator-26m { 317 compatible = "fixed-clock"; 318 #clock-cells = <0>; 319 clock-frequency = <26000000>; 320 clock-output-names = "clk26m"; 321 }; 322 323 clk32k: oscillator-32k { 324 compatible = "fixed-clock"; 325 #clock-cells = <0>; 326 clock-frequency = <32768>; 327 clock-output-names = "clk32k"; 328 }; 329 330 performance: performance-controller@11bc10 { 331 compatible = "mediatek,cpufreq-hw"; 332 reg = <0 0x0011bc10 0 0x120>, <0 0x0011bd30 0 0x120>; 333 #performance-domain-cells = <1>; 334 }; 335 336 pmu-a55 { 337 compatible = "arm,cortex-a55-pmu"; 338 interrupt-parent = <&gic>; 339 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>; 340 }; 341 342 pmu-a78 { 343 compatible = "arm,cortex-a78-pmu"; 344 interrupt-parent = <&gic>; 345 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>; 346 }; 347 348 psci { 349 compatible = "arm,psci-1.0"; 350 method = "smc"; 351 }; 352 353 timer: timer { 354 compatible = "arm,armv8-timer"; 355 interrupt-parent = <&gic>; 356 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>, 357 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>, 358 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>, 359 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>; 360 }; 361 362 soc { 363 #address-cells = <2>; 364 #size-cells = <2>; 365 compatible = "simple-bus"; 366 ranges; 367 368 gic: interrupt-controller@c000000 { 369 compatible = "arm,gic-v3"; 370 #interrupt-cells = <4>; 371 #redistributor-regions = <1>; 372 interrupt-parent = <&gic>; 373 interrupt-controller; 374 reg = <0 0x0c000000 0 0x40000>, 375 <0 0x0c040000 0 0x200000>; 376 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 377 378 ppi-partitions { 379 ppi_cluster0: interrupt-partition-0 { 380 affinity = <&cpu0 &cpu1 &cpu2 &cpu3>; 381 }; 382 383 ppi_cluster1: interrupt-partition-1 { 384 affinity = <&cpu4 &cpu5 &cpu6 &cpu7>; 385 }; 386 }; 387 }; 388 389 topckgen: syscon@10000000 { 390 compatible = "mediatek,mt8195-topckgen", "syscon"; 391 reg = <0 0x10000000 0 0x1000>; 392 #clock-cells = <1>; 393 }; 394 395 infracfg_ao: syscon@10001000 { 396 compatible = "mediatek,mt8195-infracfg_ao", "syscon", "simple-mfd"; 397 reg = <0 0x10001000 0 0x1000>; 398 #clock-cells = <1>; 399 #reset-cells = <1>; 400 }; 401 402 pericfg: syscon@10003000 { 403 compatible = "mediatek,mt8195-pericfg", "syscon"; 404 reg = <0 0x10003000 0 0x1000>; 405 #clock-cells = <1>; 406 }; 407 408 pio: pinctrl@10005000 { 409 compatible = "mediatek,mt8195-pinctrl"; 410 reg = <0 0x10005000 0 0x1000>, 411 <0 0x11d10000 0 0x1000>, 412 <0 0x11d30000 0 0x1000>, 413 <0 0x11d40000 0 0x1000>, 414 <0 0x11e20000 0 0x1000>, 415 <0 0x11eb0000 0 0x1000>, 416 <0 0x11f40000 0 0x1000>, 417 <0 0x1000b000 0 0x1000>; 418 reg-names = "iocfg0", "iocfg_bm", "iocfg_bl", 419 "iocfg_br", "iocfg_lm", "iocfg_rb", 420 "iocfg_tl", "eint"; 421 gpio-controller; 422 #gpio-cells = <2>; 423 gpio-ranges = <&pio 0 0 144>; 424 interrupt-controller; 425 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH 0>; 426 #interrupt-cells = <2>; 427 }; 428 429 scpsys: syscon@10006000 { 430 compatible = "mediatek,mt8195-scpsys", "syscon", "simple-mfd"; 431 reg = <0 0x10006000 0 0x1000>; 432 433 /* System Power Manager */ 434 spm: power-controller { 435 compatible = "mediatek,mt8195-power-controller"; 436 #address-cells = <1>; 437 #size-cells = <0>; 438 #power-domain-cells = <1>; 439 440 /* power domain of the SoC */ 441 mfg0: power-domain@MT8195_POWER_DOMAIN_MFG0 { 442 reg = <MT8195_POWER_DOMAIN_MFG0>; 443 #address-cells = <1>; 444 #size-cells = <0>; 445 #power-domain-cells = <1>; 446 447 power-domain@MT8195_POWER_DOMAIN_MFG1 { 448 reg = <MT8195_POWER_DOMAIN_MFG1>; 449 clocks = <&apmixedsys CLK_APMIXED_MFGPLL>; 450 clock-names = "mfg"; 451 mediatek,infracfg = <&infracfg_ao>; 452 #address-cells = <1>; 453 #size-cells = <0>; 454 #power-domain-cells = <1>; 455 456 power-domain@MT8195_POWER_DOMAIN_MFG2 { 457 reg = <MT8195_POWER_DOMAIN_MFG2>; 458 #power-domain-cells = <0>; 459 }; 460 461 power-domain@MT8195_POWER_DOMAIN_MFG3 { 462 reg = <MT8195_POWER_DOMAIN_MFG3>; 463 #power-domain-cells = <0>; 464 }; 465 466 power-domain@MT8195_POWER_DOMAIN_MFG4 { 467 reg = <MT8195_POWER_DOMAIN_MFG4>; 468 #power-domain-cells = <0>; 469 }; 470 471 power-domain@MT8195_POWER_DOMAIN_MFG5 { 472 reg = <MT8195_POWER_DOMAIN_MFG5>; 473 #power-domain-cells = <0>; 474 }; 475 476 power-domain@MT8195_POWER_DOMAIN_MFG6 { 477 reg = <MT8195_POWER_DOMAIN_MFG6>; 478 #power-domain-cells = <0>; 479 }; 480 }; 481 }; 482 483 power-domain@MT8195_POWER_DOMAIN_VPPSYS0 { 484 reg = <MT8195_POWER_DOMAIN_VPPSYS0>; 485 clocks = <&topckgen CLK_TOP_VPP>, 486 <&topckgen CLK_TOP_CAM>, 487 <&topckgen CLK_TOP_CCU>, 488 <&topckgen CLK_TOP_IMG>, 489 <&topckgen CLK_TOP_VENC>, 490 <&topckgen CLK_TOP_VDEC>, 491 <&topckgen CLK_TOP_WPE_VPP>, 492 <&topckgen CLK_TOP_CFG_VPP0>, 493 <&vppsys0 CLK_VPP0_SMI_COMMON>, 494 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB0>, 495 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB1>, 496 <&vppsys0 CLK_VPP0_GALS_VENCSYS>, 497 <&vppsys0 CLK_VPP0_GALS_VENCSYS_CORE1>, 498 <&vppsys0 CLK_VPP0_GALS_INFRA>, 499 <&vppsys0 CLK_VPP0_GALS_CAMSYS>, 500 <&vppsys0 CLK_VPP0_GALS_VPP1_LARB5>, 501 <&vppsys0 CLK_VPP0_GALS_VPP1_LARB6>, 502 <&vppsys0 CLK_VPP0_SMI_REORDER>, 503 <&vppsys0 CLK_VPP0_SMI_IOMMU>, 504 <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>, 505 <&vppsys0 CLK_VPP0_GALS_EMI0_EMI1>, 506 <&vppsys0 CLK_VPP0_SMI_SUB_COMMON_REORDER>, 507 <&vppsys0 CLK_VPP0_SMI_RSI>, 508 <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>, 509 <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>, 510 <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>, 511 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>; 512 clock-names = "vppsys", "vppsys1", "vppsys2", "vppsys3", 513 "vppsys4", "vppsys5", "vppsys6", "vppsys7", 514 "vppsys0-0", "vppsys0-1", "vppsys0-2", "vppsys0-3", 515 "vppsys0-4", "vppsys0-5", "vppsys0-6", "vppsys0-7", 516 "vppsys0-8", "vppsys0-9", "vppsys0-10", "vppsys0-11", 517 "vppsys0-12", "vppsys0-13", "vppsys0-14", 518 "vppsys0-15", "vppsys0-16", "vppsys0-17", 519 "vppsys0-18"; 520 mediatek,infracfg = <&infracfg_ao>; 521 #address-cells = <1>; 522 #size-cells = <0>; 523 #power-domain-cells = <1>; 524 525 power-domain@MT8195_POWER_DOMAIN_VDEC1 { 526 reg = <MT8195_POWER_DOMAIN_VDEC1>; 527 clocks = <&vdecsys CLK_VDEC_LARB1>; 528 clock-names = "vdec1-0"; 529 mediatek,infracfg = <&infracfg_ao>; 530 #power-domain-cells = <0>; 531 }; 532 533 power-domain@MT8195_POWER_DOMAIN_VENC_CORE1 { 534 reg = <MT8195_POWER_DOMAIN_VENC_CORE1>; 535 mediatek,infracfg = <&infracfg_ao>; 536 #power-domain-cells = <0>; 537 }; 538 539 power-domain@MT8195_POWER_DOMAIN_VDOSYS0 { 540 reg = <MT8195_POWER_DOMAIN_VDOSYS0>; 541 clocks = <&topckgen CLK_TOP_CFG_VDO0>, 542 <&vdosys0 CLK_VDO0_SMI_GALS>, 543 <&vdosys0 CLK_VDO0_SMI_COMMON>, 544 <&vdosys0 CLK_VDO0_SMI_EMI>, 545 <&vdosys0 CLK_VDO0_SMI_IOMMU>, 546 <&vdosys0 CLK_VDO0_SMI_LARB>, 547 <&vdosys0 CLK_VDO0_SMI_RSI>; 548 clock-names = "vdosys0", "vdosys0-0", "vdosys0-1", 549 "vdosys0-2", "vdosys0-3", 550 "vdosys0-4", "vdosys0-5"; 551 mediatek,infracfg = <&infracfg_ao>; 552 #address-cells = <1>; 553 #size-cells = <0>; 554 #power-domain-cells = <1>; 555 556 power-domain@MT8195_POWER_DOMAIN_VPPSYS1 { 557 reg = <MT8195_POWER_DOMAIN_VPPSYS1>; 558 clocks = <&topckgen CLK_TOP_CFG_VPP1>, 559 <&vppsys1 CLK_VPP1_VPPSYS1_GALS>, 560 <&vppsys1 CLK_VPP1_VPPSYS1_LARB>; 561 clock-names = "vppsys1", "vppsys1-0", 562 "vppsys1-1"; 563 mediatek,infracfg = <&infracfg_ao>; 564 #power-domain-cells = <0>; 565 }; 566 567 power-domain@MT8195_POWER_DOMAIN_WPESYS { 568 reg = <MT8195_POWER_DOMAIN_WPESYS>; 569 clocks = <&wpesys CLK_WPE_SMI_LARB7>, 570 <&wpesys CLK_WPE_SMI_LARB8>, 571 <&wpesys CLK_WPE_SMI_LARB7_P>, 572 <&wpesys CLK_WPE_SMI_LARB8_P>; 573 clock-names = "wepsys-0", "wepsys-1", "wepsys-2", 574 "wepsys-3"; 575 mediatek,infracfg = <&infracfg_ao>; 576 #power-domain-cells = <0>; 577 }; 578 579 power-domain@MT8195_POWER_DOMAIN_VDEC0 { 580 reg = <MT8195_POWER_DOMAIN_VDEC0>; 581 clocks = <&vdecsys_soc CLK_VDEC_SOC_LARB1>; 582 clock-names = "vdec0-0"; 583 mediatek,infracfg = <&infracfg_ao>; 584 #power-domain-cells = <0>; 585 }; 586 587 power-domain@MT8195_POWER_DOMAIN_VDEC2 { 588 reg = <MT8195_POWER_DOMAIN_VDEC2>; 589 clocks = <&vdecsys_core1 CLK_VDEC_CORE1_LARB1>; 590 clock-names = "vdec2-0"; 591 mediatek,infracfg = <&infracfg_ao>; 592 #power-domain-cells = <0>; 593 }; 594 595 power-domain@MT8195_POWER_DOMAIN_VENC { 596 reg = <MT8195_POWER_DOMAIN_VENC>; 597 mediatek,infracfg = <&infracfg_ao>; 598 #power-domain-cells = <0>; 599 }; 600 601 power-domain@MT8195_POWER_DOMAIN_VDOSYS1 { 602 reg = <MT8195_POWER_DOMAIN_VDOSYS1>; 603 clocks = <&topckgen CLK_TOP_CFG_VDO1>, 604 <&vdosys1 CLK_VDO1_SMI_LARB2>, 605 <&vdosys1 CLK_VDO1_SMI_LARB3>, 606 <&vdosys1 CLK_VDO1_GALS>; 607 clock-names = "vdosys1", "vdosys1-0", 608 "vdosys1-1", "vdosys1-2"; 609 mediatek,infracfg = <&infracfg_ao>; 610 #address-cells = <1>; 611 #size-cells = <0>; 612 #power-domain-cells = <1>; 613 614 power-domain@MT8195_POWER_DOMAIN_DP_TX { 615 reg = <MT8195_POWER_DOMAIN_DP_TX>; 616 mediatek,infracfg = <&infracfg_ao>; 617 #power-domain-cells = <0>; 618 }; 619 620 power-domain@MT8195_POWER_DOMAIN_EPD_TX { 621 reg = <MT8195_POWER_DOMAIN_EPD_TX>; 622 mediatek,infracfg = <&infracfg_ao>; 623 #power-domain-cells = <0>; 624 }; 625 626 power-domain@MT8195_POWER_DOMAIN_HDMI_TX { 627 reg = <MT8195_POWER_DOMAIN_HDMI_TX>; 628 clocks = <&topckgen CLK_TOP_HDMI_APB>; 629 clock-names = "hdmi_tx"; 630 #power-domain-cells = <0>; 631 }; 632 }; 633 634 power-domain@MT8195_POWER_DOMAIN_IMG { 635 reg = <MT8195_POWER_DOMAIN_IMG>; 636 clocks = <&imgsys CLK_IMG_LARB9>, 637 <&imgsys CLK_IMG_GALS>; 638 clock-names = "img-0", "img-1"; 639 mediatek,infracfg = <&infracfg_ao>; 640 #address-cells = <1>; 641 #size-cells = <0>; 642 #power-domain-cells = <1>; 643 644 power-domain@MT8195_POWER_DOMAIN_DIP { 645 reg = <MT8195_POWER_DOMAIN_DIP>; 646 #power-domain-cells = <0>; 647 }; 648 649 power-domain@MT8195_POWER_DOMAIN_IPE { 650 reg = <MT8195_POWER_DOMAIN_IPE>; 651 clocks = <&topckgen CLK_TOP_IPE>, 652 <&imgsys CLK_IMG_IPE>, 653 <&ipesys CLK_IPE_SMI_LARB12>; 654 clock-names = "ipe", "ipe-0", "ipe-1"; 655 mediatek,infracfg = <&infracfg_ao>; 656 #power-domain-cells = <0>; 657 }; 658 }; 659 660 power-domain@MT8195_POWER_DOMAIN_CAM { 661 reg = <MT8195_POWER_DOMAIN_CAM>; 662 clocks = <&camsys CLK_CAM_LARB13>, 663 <&camsys CLK_CAM_LARB14>, 664 <&camsys CLK_CAM_CAM2MM0_GALS>, 665 <&camsys CLK_CAM_CAM2MM1_GALS>, 666 <&camsys CLK_CAM_CAM2SYS_GALS>; 667 clock-names = "cam-0", "cam-1", "cam-2", "cam-3", 668 "cam-4"; 669 mediatek,infracfg = <&infracfg_ao>; 670 #address-cells = <1>; 671 #size-cells = <0>; 672 #power-domain-cells = <1>; 673 674 power-domain@MT8195_POWER_DOMAIN_CAM_RAWA { 675 reg = <MT8195_POWER_DOMAIN_CAM_RAWA>; 676 #power-domain-cells = <0>; 677 }; 678 679 power-domain@MT8195_POWER_DOMAIN_CAM_RAWB { 680 reg = <MT8195_POWER_DOMAIN_CAM_RAWB>; 681 #power-domain-cells = <0>; 682 }; 683 684 power-domain@MT8195_POWER_DOMAIN_CAM_MRAW { 685 reg = <MT8195_POWER_DOMAIN_CAM_MRAW>; 686 #power-domain-cells = <0>; 687 }; 688 }; 689 }; 690 }; 691 692 power-domain@MT8195_POWER_DOMAIN_PCIE_MAC_P0 { 693 reg = <MT8195_POWER_DOMAIN_PCIE_MAC_P0>; 694 mediatek,infracfg = <&infracfg_ao>; 695 #power-domain-cells = <0>; 696 }; 697 698 power-domain@MT8195_POWER_DOMAIN_PCIE_MAC_P1 { 699 reg = <MT8195_POWER_DOMAIN_PCIE_MAC_P1>; 700 mediatek,infracfg = <&infracfg_ao>; 701 #power-domain-cells = <0>; 702 }; 703 704 power-domain@MT8195_POWER_DOMAIN_PCIE_PHY { 705 reg = <MT8195_POWER_DOMAIN_PCIE_PHY>; 706 #power-domain-cells = <0>; 707 }; 708 709 power-domain@MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY { 710 reg = <MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY>; 711 #power-domain-cells = <0>; 712 }; 713 714 power-domain@MT8195_POWER_DOMAIN_CSI_RX_TOP { 715 reg = <MT8195_POWER_DOMAIN_CSI_RX_TOP>; 716 clocks = <&topckgen CLK_TOP_SENINF>, 717 <&topckgen CLK_TOP_SENINF2>; 718 clock-names = "csi_rx_top", "csi_rx_top1"; 719 #power-domain-cells = <0>; 720 }; 721 722 power-domain@MT8195_POWER_DOMAIN_ETHER { 723 reg = <MT8195_POWER_DOMAIN_ETHER>; 724 clocks = <&pericfg_ao CLK_PERI_AO_ETHERNET_MAC>; 725 clock-names = "ether"; 726 #power-domain-cells = <0>; 727 }; 728 729 power-domain@MT8195_POWER_DOMAIN_ADSP { 730 reg = <MT8195_POWER_DOMAIN_ADSP>; 731 clocks = <&topckgen CLK_TOP_ADSP>, 732 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>; 733 clock-names = "adsp", "adsp1"; 734 #address-cells = <1>; 735 #size-cells = <0>; 736 mediatek,infracfg = <&infracfg_ao>; 737 #power-domain-cells = <1>; 738 739 power-domain@MT8195_POWER_DOMAIN_AUDIO { 740 reg = <MT8195_POWER_DOMAIN_AUDIO>; 741 clocks = <&topckgen CLK_TOP_A1SYS_HP>, 742 <&topckgen CLK_TOP_AUD_INTBUS>, 743 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>, 744 <&infracfg_ao CLK_INFRA_AO_AUDIO_26M_B>; 745 clock-names = "audio", "audio1", "audio2", 746 "audio3"; 747 mediatek,infracfg = <&infracfg_ao>; 748 #power-domain-cells = <0>; 749 }; 750 }; 751 }; 752 }; 753 754 watchdog: watchdog@10007000 { 755 compatible = "mediatek,mt8195-wdt", 756 "mediatek,mt6589-wdt"; 757 mediatek,disable-extrst; 758 reg = <0 0x10007000 0 0x100>; 759 #reset-cells = <1>; 760 }; 761 762 apmixedsys: syscon@1000c000 { 763 compatible = "mediatek,mt8195-apmixedsys", "syscon"; 764 reg = <0 0x1000c000 0 0x1000>; 765 #clock-cells = <1>; 766 }; 767 768 systimer: timer@10017000 { 769 compatible = "mediatek,mt8195-timer", 770 "mediatek,mt6765-timer"; 771 reg = <0 0x10017000 0 0x1000>; 772 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>; 773 clocks = <&clk13m>; 774 }; 775 776 pwrap: pwrap@10024000 { 777 compatible = "mediatek,mt8195-pwrap", "syscon"; 778 reg = <0 0x10024000 0 0x1000>; 779 reg-names = "pwrap"; 780 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH 0>; 781 clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>, 782 <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>; 783 clock-names = "spi", "wrap"; 784 assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC>; 785 assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>; 786 }; 787 788 spmi: spmi@10027000 { 789 compatible = "mediatek,mt8195-spmi"; 790 reg = <0 0x10027000 0 0x000e00>, 791 <0 0x10029000 0 0x000100>; 792 reg-names = "pmif", "spmimst"; 793 clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>, 794 <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>, 795 <&topckgen CLK_TOP_SPMI_M_MST>; 796 clock-names = "pmif_sys_ck", 797 "pmif_tmr_ck", 798 "spmimst_clk_mux"; 799 assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC>; 800 assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>; 801 }; 802 803 iommu_infra: infra-iommu@10315000 { 804 compatible = "mediatek,mt8195-iommu-infra"; 805 reg = <0 0x10315000 0 0x5000>; 806 interrupts = <GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH 0>, 807 <GIC_SPI 796 IRQ_TYPE_LEVEL_HIGH 0>, 808 <GIC_SPI 797 IRQ_TYPE_LEVEL_HIGH 0>, 809 <GIC_SPI 798 IRQ_TYPE_LEVEL_HIGH 0>, 810 <GIC_SPI 799 IRQ_TYPE_LEVEL_HIGH 0>; 811 #iommu-cells = <1>; 812 }; 813 814 gce0: mailbox@10320000 { 815 compatible = "mediatek,mt8195-gce"; 816 reg = <0 0x10320000 0 0x4000>; 817 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH 0>; 818 #mbox-cells = <2>; 819 clocks = <&infracfg_ao CLK_INFRA_AO_GCE>; 820 }; 821 822 gce1: mailbox@10330000 { 823 compatible = "mediatek,mt8195-gce"; 824 reg = <0 0x10330000 0 0x4000>; 825 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH 0>; 826 #mbox-cells = <2>; 827 clocks = <&infracfg_ao CLK_INFRA_AO_GCE2>; 828 }; 829 830 scp: scp@10500000 { 831 compatible = "mediatek,mt8195-scp"; 832 reg = <0 0x10500000 0 0x100000>, 833 <0 0x10720000 0 0xe0000>, 834 <0 0x10700000 0 0x8000>; 835 reg-names = "sram", "cfg", "l1tcm"; 836 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH 0>; 837 status = "disabled"; 838 }; 839 840 scp_adsp: clock-controller@10720000 { 841 compatible = "mediatek,mt8195-scp_adsp"; 842 reg = <0 0x10720000 0 0x1000>; 843 #clock-cells = <1>; 844 }; 845 846 adsp: dsp@10803000 { 847 compatible = "mediatek,mt8195-dsp"; 848 reg = <0 0x10803000 0 0x1000>, 849 <0 0x10840000 0 0x40000>; 850 reg-names = "cfg", "sram"; 851 clocks = <&topckgen CLK_TOP_ADSP>, 852 <&clk26m>, 853 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>, 854 <&topckgen CLK_TOP_MAINPLL_D7_D2>, 855 <&scp_adsp CLK_SCP_ADSP_AUDIODSP>, 856 <&topckgen CLK_TOP_AUDIO_H>; 857 clock-names = "adsp_sel", 858 "clk26m_ck", 859 "audio_local_bus", 860 "mainpll_d7_d2", 861 "scp_adsp_audiodsp", 862 "audio_h"; 863 power-domains = <&spm MT8195_POWER_DOMAIN_ADSP>; 864 mbox-names = "rx", "tx"; 865 mboxes = <&adsp_mailbox0>, <&adsp_mailbox1>; 866 status = "disabled"; 867 }; 868 869 adsp_mailbox0: mailbox@10816000 { 870 compatible = "mediatek,mt8195-adsp-mbox"; 871 #mbox-cells = <0>; 872 reg = <0 0x10816000 0 0x1000>; 873 interrupts = <GIC_SPI 702 IRQ_TYPE_LEVEL_HIGH 0>; 874 }; 875 876 adsp_mailbox1: mailbox@10817000 { 877 compatible = "mediatek,mt8195-adsp-mbox"; 878 #mbox-cells = <0>; 879 reg = <0 0x10817000 0 0x1000>; 880 interrupts = <GIC_SPI 703 IRQ_TYPE_LEVEL_HIGH 0>; 881 }; 882 883 afe: mt8195-afe-pcm@10890000 { 884 compatible = "mediatek,mt8195-audio"; 885 reg = <0 0x10890000 0 0x10000>; 886 mediatek,topckgen = <&topckgen>; 887 power-domains = <&spm MT8195_POWER_DOMAIN_AUDIO>; 888 interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH 0>; 889 resets = <&watchdog 14>; 890 reset-names = "audiosys"; 891 clocks = <&clk26m>, 892 <&apmixedsys CLK_APMIXED_APLL1>, 893 <&apmixedsys CLK_APMIXED_APLL2>, 894 <&topckgen CLK_TOP_APLL12_DIV0>, 895 <&topckgen CLK_TOP_APLL12_DIV1>, 896 <&topckgen CLK_TOP_APLL12_DIV2>, 897 <&topckgen CLK_TOP_APLL12_DIV3>, 898 <&topckgen CLK_TOP_APLL12_DIV9>, 899 <&topckgen CLK_TOP_A1SYS_HP>, 900 <&topckgen CLK_TOP_AUD_INTBUS>, 901 <&topckgen CLK_TOP_AUDIO_H>, 902 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>, 903 <&topckgen CLK_TOP_DPTX_MCK>, 904 <&topckgen CLK_TOP_I2SO1_MCK>, 905 <&topckgen CLK_TOP_I2SO2_MCK>, 906 <&topckgen CLK_TOP_I2SI1_MCK>, 907 <&topckgen CLK_TOP_I2SI2_MCK>, 908 <&infracfg_ao CLK_INFRA_AO_AUDIO_26M_B>, 909 <&scp_adsp CLK_SCP_ADSP_AUDIODSP>; 910 clock-names = "clk26m", 911 "apll1_ck", 912 "apll2_ck", 913 "apll12_div0", 914 "apll12_div1", 915 "apll12_div2", 916 "apll12_div3", 917 "apll12_div9", 918 "a1sys_hp_sel", 919 "aud_intbus_sel", 920 "audio_h_sel", 921 "audio_local_bus_sel", 922 "dptx_m_sel", 923 "i2so1_m_sel", 924 "i2so2_m_sel", 925 "i2si1_m_sel", 926 "i2si2_m_sel", 927 "infra_ao_audio_26m_b", 928 "scp_adsp_audiodsp"; 929 status = "disabled"; 930 }; 931 932 uart0: serial@11001100 { 933 compatible = "mediatek,mt8195-uart", 934 "mediatek,mt6577-uart"; 935 reg = <0 0x11001100 0 0x100>; 936 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH 0>; 937 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART0>; 938 clock-names = "baud", "bus"; 939 status = "disabled"; 940 }; 941 942 uart1: serial@11001200 { 943 compatible = "mediatek,mt8195-uart", 944 "mediatek,mt6577-uart"; 945 reg = <0 0x11001200 0 0x100>; 946 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH 0>; 947 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART1>; 948 clock-names = "baud", "bus"; 949 status = "disabled"; 950 }; 951 952 uart2: serial@11001300 { 953 compatible = "mediatek,mt8195-uart", 954 "mediatek,mt6577-uart"; 955 reg = <0 0x11001300 0 0x100>; 956 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH 0>; 957 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART2>; 958 clock-names = "baud", "bus"; 959 status = "disabled"; 960 }; 961 962 uart3: serial@11001400 { 963 compatible = "mediatek,mt8195-uart", 964 "mediatek,mt6577-uart"; 965 reg = <0 0x11001400 0 0x100>; 966 interrupts = <GIC_SPI 723 IRQ_TYPE_LEVEL_HIGH 0>; 967 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART3>; 968 clock-names = "baud", "bus"; 969 status = "disabled"; 970 }; 971 972 uart4: serial@11001500 { 973 compatible = "mediatek,mt8195-uart", 974 "mediatek,mt6577-uart"; 975 reg = <0 0x11001500 0 0x100>; 976 interrupts = <GIC_SPI 724 IRQ_TYPE_LEVEL_HIGH 0>; 977 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART4>; 978 clock-names = "baud", "bus"; 979 status = "disabled"; 980 }; 981 982 uart5: serial@11001600 { 983 compatible = "mediatek,mt8195-uart", 984 "mediatek,mt6577-uart"; 985 reg = <0 0x11001600 0 0x100>; 986 interrupts = <GIC_SPI 725 IRQ_TYPE_LEVEL_HIGH 0>; 987 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART5>; 988 clock-names = "baud", "bus"; 989 status = "disabled"; 990 }; 991 992 auxadc: auxadc@11002000 { 993 compatible = "mediatek,mt8195-auxadc", 994 "mediatek,mt8173-auxadc"; 995 reg = <0 0x11002000 0 0x1000>; 996 clocks = <&infracfg_ao CLK_INFRA_AO_AUXADC>; 997 clock-names = "main"; 998 #io-channel-cells = <1>; 999 status = "disabled"; 1000 }; 1001 1002 pericfg_ao: syscon@11003000 { 1003 compatible = "mediatek,mt8195-pericfg_ao", "syscon"; 1004 reg = <0 0x11003000 0 0x1000>; 1005 #clock-cells = <1>; 1006 }; 1007 1008 spi0: spi@1100a000 { 1009 compatible = "mediatek,mt8195-spi", 1010 "mediatek,mt6765-spi"; 1011 #address-cells = <1>; 1012 #size-cells = <0>; 1013 reg = <0 0x1100a000 0 0x1000>; 1014 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH 0>; 1015 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 1016 <&topckgen CLK_TOP_SPI>, 1017 <&infracfg_ao CLK_INFRA_AO_SPI0>; 1018 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1019 status = "disabled"; 1020 }; 1021 1022 spi1: spi@11010000 { 1023 compatible = "mediatek,mt8195-spi", 1024 "mediatek,mt6765-spi"; 1025 #address-cells = <1>; 1026 #size-cells = <0>; 1027 reg = <0 0x11010000 0 0x1000>; 1028 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH 0>; 1029 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 1030 <&topckgen CLK_TOP_SPI>, 1031 <&infracfg_ao CLK_INFRA_AO_SPI1>; 1032 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1033 status = "disabled"; 1034 }; 1035 1036 spi2: spi@11012000 { 1037 compatible = "mediatek,mt8195-spi", 1038 "mediatek,mt6765-spi"; 1039 #address-cells = <1>; 1040 #size-cells = <0>; 1041 reg = <0 0x11012000 0 0x1000>; 1042 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH 0>; 1043 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 1044 <&topckgen CLK_TOP_SPI>, 1045 <&infracfg_ao CLK_INFRA_AO_SPI2>; 1046 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1047 status = "disabled"; 1048 }; 1049 1050 spi3: spi@11013000 { 1051 compatible = "mediatek,mt8195-spi", 1052 "mediatek,mt6765-spi"; 1053 #address-cells = <1>; 1054 #size-cells = <0>; 1055 reg = <0 0x11013000 0 0x1000>; 1056 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH 0>; 1057 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 1058 <&topckgen CLK_TOP_SPI>, 1059 <&infracfg_ao CLK_INFRA_AO_SPI3>; 1060 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1061 status = "disabled"; 1062 }; 1063 1064 spi4: spi@11018000 { 1065 compatible = "mediatek,mt8195-spi", 1066 "mediatek,mt6765-spi"; 1067 #address-cells = <1>; 1068 #size-cells = <0>; 1069 reg = <0 0x11018000 0 0x1000>; 1070 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH 0>; 1071 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 1072 <&topckgen CLK_TOP_SPI>, 1073 <&infracfg_ao CLK_INFRA_AO_SPI4>; 1074 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1075 status = "disabled"; 1076 }; 1077 1078 spi5: spi@11019000 { 1079 compatible = "mediatek,mt8195-spi", 1080 "mediatek,mt6765-spi"; 1081 #address-cells = <1>; 1082 #size-cells = <0>; 1083 reg = <0 0x11019000 0 0x1000>; 1084 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH 0>; 1085 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 1086 <&topckgen CLK_TOP_SPI>, 1087 <&infracfg_ao CLK_INFRA_AO_SPI5>; 1088 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1089 status = "disabled"; 1090 }; 1091 1092 spis0: spi@1101d000 { 1093 compatible = "mediatek,mt8195-spi-slave"; 1094 reg = <0 0x1101d000 0 0x1000>; 1095 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH 0>; 1096 clocks = <&infracfg_ao CLK_INFRA_AO_SPIS0>; 1097 clock-names = "spi"; 1098 assigned-clocks = <&topckgen CLK_TOP_SPIS>; 1099 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>; 1100 status = "disabled"; 1101 }; 1102 1103 spis1: spi@1101e000 { 1104 compatible = "mediatek,mt8195-spi-slave"; 1105 reg = <0 0x1101e000 0 0x1000>; 1106 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH 0>; 1107 clocks = <&infracfg_ao CLK_INFRA_AO_SPIS1>; 1108 clock-names = "spi"; 1109 assigned-clocks = <&topckgen CLK_TOP_SPIS>; 1110 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>; 1111 status = "disabled"; 1112 }; 1113 1114 eth: ethernet@11021000 { 1115 compatible = "mediatek,mt8195-gmac", "snps,dwmac-5.10a"; 1116 reg = <0 0x11021000 0 0x4000>; 1117 interrupts = <GIC_SPI 716 IRQ_TYPE_LEVEL_HIGH 0>; 1118 interrupt-names = "macirq"; 1119 clock-names = "axi", 1120 "apb", 1121 "mac_main", 1122 "ptp_ref", 1123 "rmii_internal", 1124 "mac_cg"; 1125 clocks = <&pericfg_ao CLK_PERI_AO_ETHERNET>, 1126 <&pericfg_ao CLK_PERI_AO_ETHERNET_BUS>, 1127 <&topckgen CLK_TOP_SNPS_ETH_250M>, 1128 <&topckgen CLK_TOP_SNPS_ETH_62P4M_PTP>, 1129 <&topckgen CLK_TOP_SNPS_ETH_50M_RMII>, 1130 <&pericfg_ao CLK_PERI_AO_ETHERNET_MAC>; 1131 assigned-clocks = <&topckgen CLK_TOP_SNPS_ETH_250M>, 1132 <&topckgen CLK_TOP_SNPS_ETH_62P4M_PTP>, 1133 <&topckgen CLK_TOP_SNPS_ETH_50M_RMII>; 1134 assigned-clock-parents = <&topckgen CLK_TOP_ETHPLL_D2>, 1135 <&topckgen CLK_TOP_ETHPLL_D8>, 1136 <&topckgen CLK_TOP_ETHPLL_D10>; 1137 power-domains = <&spm MT8195_POWER_DOMAIN_ETHER>; 1138 mediatek,pericfg = <&infracfg_ao>; 1139 snps,axi-config = <&stmmac_axi_setup>; 1140 snps,mtl-rx-config = <&mtl_rx_setup>; 1141 snps,mtl-tx-config = <&mtl_tx_setup>; 1142 snps,txpbl = <16>; 1143 snps,rxpbl = <16>; 1144 snps,clk-csr = <0>; 1145 status = "disabled"; 1146 1147 mdio { 1148 compatible = "snps,dwmac-mdio"; 1149 #address-cells = <1>; 1150 #size-cells = <0>; 1151 }; 1152 1153 stmmac_axi_setup: stmmac-axi-config { 1154 snps,wr_osr_lmt = <0x7>; 1155 snps,rd_osr_lmt = <0x7>; 1156 snps,blen = <0 0 0 0 16 8 4>; 1157 }; 1158 1159 mtl_rx_setup: rx-queues-config { 1160 snps,rx-queues-to-use = <4>; 1161 snps,rx-sched-sp; 1162 queue0 { 1163 snps,dcb-algorithm; 1164 snps,map-to-dma-channel = <0x0>; 1165 }; 1166 queue1 { 1167 snps,dcb-algorithm; 1168 snps,map-to-dma-channel = <0x0>; 1169 }; 1170 queue2 { 1171 snps,dcb-algorithm; 1172 snps,map-to-dma-channel = <0x0>; 1173 }; 1174 queue3 { 1175 snps,dcb-algorithm; 1176 snps,map-to-dma-channel = <0x0>; 1177 }; 1178 }; 1179 1180 mtl_tx_setup: tx-queues-config { 1181 snps,tx-queues-to-use = <4>; 1182 snps,tx-sched-wrr; 1183 queue0 { 1184 snps,weight = <0x10>; 1185 snps,dcb-algorithm; 1186 snps,priority = <0x0>; 1187 }; 1188 queue1 { 1189 snps,weight = <0x11>; 1190 snps,dcb-algorithm; 1191 snps,priority = <0x1>; 1192 }; 1193 queue2 { 1194 snps,weight = <0x12>; 1195 snps,dcb-algorithm; 1196 snps,priority = <0x2>; 1197 }; 1198 queue3 { 1199 snps,weight = <0x13>; 1200 snps,dcb-algorithm; 1201 snps,priority = <0x3>; 1202 }; 1203 }; 1204 }; 1205 1206 xhci0: usb@11200000 { 1207 compatible = "mediatek,mt8195-xhci", 1208 "mediatek,mtk-xhci"; 1209 reg = <0 0x11200000 0 0x1000>, 1210 <0 0x11203e00 0 0x0100>; 1211 reg-names = "mac", "ippc"; 1212 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH 0>; 1213 phys = <&u2port0 PHY_TYPE_USB2>, 1214 <&u3port0 PHY_TYPE_USB3>; 1215 assigned-clocks = <&topckgen CLK_TOP_USB_TOP>, 1216 <&topckgen CLK_TOP_SSUSB_XHCI>; 1217 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, 1218 <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 1219 clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB>, 1220 <&topckgen CLK_TOP_SSUSB_REF>, 1221 <&apmixedsys CLK_APMIXED_USB1PLL>, 1222 <&clk26m>, 1223 <&infracfg_ao CLK_INFRA_AO_SSUSB_XHCI>; 1224 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", 1225 "xhci_ck"; 1226 mediatek,syscon-wakeup = <&pericfg 0x400 103>; 1227 wakeup-source; 1228 status = "disabled"; 1229 }; 1230 1231 mmc0: mmc@11230000 { 1232 compatible = "mediatek,mt8195-mmc", 1233 "mediatek,mt8183-mmc"; 1234 reg = <0 0x11230000 0 0x10000>, 1235 <0 0x11f50000 0 0x1000>; 1236 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>; 1237 clocks = <&topckgen CLK_TOP_MSDC50_0>, 1238 <&infracfg_ao CLK_INFRA_AO_MSDC0>, 1239 <&infracfg_ao CLK_INFRA_AO_MSDC0_SRC>; 1240 clock-names = "source", "hclk", "source_cg"; 1241 status = "disabled"; 1242 }; 1243 1244 mmc1: mmc@11240000 { 1245 compatible = "mediatek,mt8195-mmc", 1246 "mediatek,mt8183-mmc"; 1247 reg = <0 0x11240000 0 0x1000>, 1248 <0 0x11c70000 0 0x1000>; 1249 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH 0>; 1250 clocks = <&topckgen CLK_TOP_MSDC30_1>, 1251 <&infracfg_ao CLK_INFRA_AO_MSDC1>, 1252 <&infracfg_ao CLK_INFRA_AO_MSDC1_SRC>; 1253 clock-names = "source", "hclk", "source_cg"; 1254 assigned-clocks = <&topckgen CLK_TOP_MSDC30_1>; 1255 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>; 1256 status = "disabled"; 1257 }; 1258 1259 mmc2: mmc@11250000 { 1260 compatible = "mediatek,mt8195-mmc", 1261 "mediatek,mt8183-mmc"; 1262 reg = <0 0x11250000 0 0x1000>, 1263 <0 0x11e60000 0 0x1000>; 1264 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH 0>; 1265 clocks = <&topckgen CLK_TOP_MSDC30_2>, 1266 <&infracfg_ao CLK_INFRA_AO_CG1_MSDC2>, 1267 <&infracfg_ao CLK_INFRA_AO_CG3_MSDC2>; 1268 clock-names = "source", "hclk", "source_cg"; 1269 assigned-clocks = <&topckgen CLK_TOP_MSDC30_2>; 1270 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>; 1271 status = "disabled"; 1272 }; 1273 1274 xhci1: usb@11290000 { 1275 compatible = "mediatek,mt8195-xhci", 1276 "mediatek,mtk-xhci"; 1277 reg = <0 0x11290000 0 0x1000>, 1278 <0 0x11293e00 0 0x0100>; 1279 reg-names = "mac", "ippc"; 1280 interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH 0>; 1281 phys = <&u2port1 PHY_TYPE_USB2>; 1282 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_1P>, 1283 <&topckgen CLK_TOP_SSUSB_XHCI_1P>; 1284 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, 1285 <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 1286 clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_1P_BUS>, 1287 <&topckgen CLK_TOP_SSUSB_P1_REF>, 1288 <&apmixedsys CLK_APMIXED_USB1PLL>, 1289 <&clk26m>, 1290 <&pericfg_ao CLK_PERI_AO_SSUSB_1P_XHCI>; 1291 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", 1292 "xhci_ck"; 1293 mediatek,syscon-wakeup = <&pericfg 0x400 104>; 1294 wakeup-source; 1295 status = "disabled"; 1296 }; 1297 1298 xhci2: usb@112a0000 { 1299 compatible = "mediatek,mt8195-xhci", 1300 "mediatek,mtk-xhci"; 1301 reg = <0 0x112a0000 0 0x1000>, 1302 <0 0x112a3e00 0 0x0100>; 1303 reg-names = "mac", "ippc"; 1304 interrupts = <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH 0>; 1305 phys = <&u2port2 PHY_TYPE_USB2>; 1306 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_2P>, 1307 <&topckgen CLK_TOP_SSUSB_XHCI_2P>; 1308 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, 1309 <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 1310 clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_2P_BUS>, 1311 <&topckgen CLK_TOP_SSUSB_P2_REF>, 1312 <&clk26m>, 1313 <&clk26m>, 1314 <&pericfg_ao CLK_PERI_AO_SSUSB_2P_XHCI>; 1315 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", 1316 "xhci_ck"; 1317 mediatek,syscon-wakeup = <&pericfg 0x400 105>; 1318 wakeup-source; 1319 status = "disabled"; 1320 }; 1321 1322 xhci3: usb@112b0000 { 1323 compatible = "mediatek,mt8195-xhci", 1324 "mediatek,mtk-xhci"; 1325 reg = <0 0x112b0000 0 0x1000>, 1326 <0 0x112b3e00 0 0x0100>; 1327 reg-names = "mac", "ippc"; 1328 interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH 0>; 1329 phys = <&u2port3 PHY_TYPE_USB2>; 1330 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_3P>, 1331 <&topckgen CLK_TOP_SSUSB_XHCI_3P>; 1332 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, 1333 <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 1334 clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_3P_BUS>, 1335 <&topckgen CLK_TOP_SSUSB_P3_REF>, 1336 <&clk26m>, 1337 <&clk26m>, 1338 <&pericfg_ao CLK_PERI_AO_SSUSB_3P_XHCI>; 1339 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", 1340 "xhci_ck"; 1341 mediatek,syscon-wakeup = <&pericfg 0x400 106>; 1342 wakeup-source; 1343 status = "disabled"; 1344 }; 1345 1346 pcie0: pcie@112f0000 { 1347 compatible = "mediatek,mt8195-pcie", 1348 "mediatek,mt8192-pcie"; 1349 device_type = "pci"; 1350 #address-cells = <3>; 1351 #size-cells = <2>; 1352 reg = <0 0x112f0000 0 0x4000>; 1353 reg-names = "pcie-mac"; 1354 interrupts = <GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH 0>; 1355 bus-range = <0x00 0xff>; 1356 ranges = <0x81000000 0 0x20000000 1357 0x0 0x20000000 0 0x200000>, 1358 <0x82000000 0 0x20200000 1359 0x0 0x20200000 0 0x3e00000>; 1360 1361 iommu-map = <0 &iommu_infra IOMMU_PORT_INFRA_PCIE0 0x2>; 1362 iommu-map-mask = <0x0>; 1363 1364 clocks = <&infracfg_ao CLK_INFRA_AO_PCIE_PL_P_250M_P0>, 1365 <&infracfg_ao CLK_INFRA_AO_PCIE_TL_26M>, 1366 <&infracfg_ao CLK_INFRA_AO_PCIE_TL_96M>, 1367 <&infracfg_ao CLK_INFRA_AO_PCIE_TL_32K>, 1368 <&infracfg_ao CLK_INFRA_AO_PCIE_PERI_26M>, 1369 <&pericfg_ao CLK_PERI_AO_PCIE_P0_MEM>; 1370 clock-names = "pl_250m", "tl_26m", "tl_96m", 1371 "tl_32k", "peri_26m", "peri_mem"; 1372 assigned-clocks = <&topckgen CLK_TOP_TL>; 1373 assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4_D4>; 1374 1375 phys = <&pciephy>; 1376 phy-names = "pcie-phy"; 1377 1378 power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_MAC_P0>; 1379 1380 resets = <&infracfg_ao MT8195_INFRA_RST2_PCIE_P0_SWRST>; 1381 reset-names = "mac"; 1382 1383 #interrupt-cells = <1>; 1384 interrupt-map-mask = <0 0 0 7>; 1385 interrupt-map = <0 0 0 1 &pcie_intc0 0>, 1386 <0 0 0 2 &pcie_intc0 1>, 1387 <0 0 0 3 &pcie_intc0 2>, 1388 <0 0 0 4 &pcie_intc0 3>; 1389 status = "disabled"; 1390 1391 pcie_intc0: interrupt-controller { 1392 interrupt-controller; 1393 #address-cells = <0>; 1394 #interrupt-cells = <1>; 1395 }; 1396 }; 1397 1398 pcie1: pcie@112f8000 { 1399 compatible = "mediatek,mt8195-pcie", 1400 "mediatek,mt8192-pcie"; 1401 device_type = "pci"; 1402 #address-cells = <3>; 1403 #size-cells = <2>; 1404 reg = <0 0x112f8000 0 0x4000>; 1405 reg-names = "pcie-mac"; 1406 interrupts = <GIC_SPI 792 IRQ_TYPE_LEVEL_HIGH 0>; 1407 bus-range = <0x00 0xff>; 1408 ranges = <0x81000000 0 0x24000000 1409 0x0 0x24000000 0 0x200000>, 1410 <0x82000000 0 0x24200000 1411 0x0 0x24200000 0 0x3e00000>; 1412 1413 iommu-map = <0 &iommu_infra IOMMU_PORT_INFRA_PCIE1 0x2>; 1414 iommu-map-mask = <0x0>; 1415 1416 clocks = <&infracfg_ao CLK_INFRA_AO_PCIE_PL_P_250M_P1>, 1417 <&clk26m>, 1418 <&infracfg_ao CLK_INFRA_AO_PCIE_P1_TL_96M>, 1419 <&clk26m>, 1420 <&infracfg_ao CLK_INFRA_AO_PCIE_P1_PERI_26M>, 1421 /* Designer has connect pcie1 with peri_mem_p0 clock */ 1422 <&pericfg_ao CLK_PERI_AO_PCIE_P0_MEM>; 1423 clock-names = "pl_250m", "tl_26m", "tl_96m", 1424 "tl_32k", "peri_26m", "peri_mem"; 1425 assigned-clocks = <&topckgen CLK_TOP_TL_P1>; 1426 assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4_D4>; 1427 1428 phys = <&u3port1 PHY_TYPE_PCIE>; 1429 phy-names = "pcie-phy"; 1430 power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_MAC_P1>; 1431 1432 resets = <&infracfg_ao MT8195_INFRA_RST2_PCIE_P1_SWRST>; 1433 reset-names = "mac"; 1434 1435 #interrupt-cells = <1>; 1436 interrupt-map-mask = <0 0 0 7>; 1437 interrupt-map = <0 0 0 1 &pcie_intc1 0>, 1438 <0 0 0 2 &pcie_intc1 1>, 1439 <0 0 0 3 &pcie_intc1 2>, 1440 <0 0 0 4 &pcie_intc1 3>; 1441 status = "disabled"; 1442 1443 pcie_intc1: interrupt-controller { 1444 interrupt-controller; 1445 #address-cells = <0>; 1446 #interrupt-cells = <1>; 1447 }; 1448 }; 1449 1450 nor_flash: spi@1132c000 { 1451 compatible = "mediatek,mt8195-nor", 1452 "mediatek,mt8173-nor"; 1453 reg = <0 0x1132c000 0 0x1000>; 1454 interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH 0>; 1455 clocks = <&topckgen CLK_TOP_SPINOR>, 1456 <&pericfg_ao CLK_PERI_AO_FLASHIF_FLASH>, 1457 <&pericfg_ao CLK_PERI_AO_FLASHIF_BUS>; 1458 clock-names = "spi", "sf", "axi"; 1459 #address-cells = <1>; 1460 #size-cells = <0>; 1461 status = "disabled"; 1462 }; 1463 1464 efuse: efuse@11c10000 { 1465 compatible = "mediatek,mt8195-efuse", "mediatek,efuse"; 1466 reg = <0 0x11c10000 0 0x1000>; 1467 #address-cells = <1>; 1468 #size-cells = <1>; 1469 u3_tx_imp_p0: usb3-tx-imp@184,1 { 1470 reg = <0x184 0x1>; 1471 bits = <0 5>; 1472 }; 1473 u3_rx_imp_p0: usb3-rx-imp@184,2 { 1474 reg = <0x184 0x2>; 1475 bits = <5 5>; 1476 }; 1477 u3_intr_p0: usb3-intr@185 { 1478 reg = <0x185 0x1>; 1479 bits = <2 6>; 1480 }; 1481 comb_tx_imp_p1: usb3-tx-imp@186,1 { 1482 reg = <0x186 0x1>; 1483 bits = <0 5>; 1484 }; 1485 comb_rx_imp_p1: usb3-rx-imp@186,2 { 1486 reg = <0x186 0x2>; 1487 bits = <5 5>; 1488 }; 1489 comb_intr_p1: usb3-intr@187 { 1490 reg = <0x187 0x1>; 1491 bits = <2 6>; 1492 }; 1493 u2_intr_p0: usb2-intr-p0@188,1 { 1494 reg = <0x188 0x1>; 1495 bits = <0 5>; 1496 }; 1497 u2_intr_p1: usb2-intr-p1@188,2 { 1498 reg = <0x188 0x2>; 1499 bits = <5 5>; 1500 }; 1501 u2_intr_p2: usb2-intr-p2@189,1 { 1502 reg = <0x189 0x1>; 1503 bits = <2 5>; 1504 }; 1505 u2_intr_p3: usb2-intr-p3@189,2 { 1506 reg = <0x189 0x2>; 1507 bits = <7 5>; 1508 }; 1509 pciephy_rx_ln1: pciephy-rx-ln1@190,1 { 1510 reg = <0x190 0x1>; 1511 bits = <0 4>; 1512 }; 1513 pciephy_tx_ln1_nmos: pciephy-tx-ln1-nmos@190,2 { 1514 reg = <0x190 0x1>; 1515 bits = <4 4>; 1516 }; 1517 pciephy_tx_ln1_pmos: pciephy-tx-ln1-pmos@191,1 { 1518 reg = <0x191 0x1>; 1519 bits = <0 4>; 1520 }; 1521 pciephy_rx_ln0: pciephy-rx-ln0@191,2 { 1522 reg = <0x191 0x1>; 1523 bits = <4 4>; 1524 }; 1525 pciephy_tx_ln0_nmos: pciephy-tx-ln0-nmos@192,1 { 1526 reg = <0x192 0x1>; 1527 bits = <0 4>; 1528 }; 1529 pciephy_tx_ln0_pmos: pciephy-tx-ln0-pmos@192,2 { 1530 reg = <0x192 0x1>; 1531 bits = <4 4>; 1532 }; 1533 pciephy_glb_intr: pciephy-glb-intr@193 { 1534 reg = <0x193 0x1>; 1535 bits = <0 4>; 1536 }; 1537 dp_calibration: dp-data@1ac { 1538 reg = <0x1ac 0x10>; 1539 }; 1540 lvts_efuse_data1: lvts1-calib@1bc { 1541 reg = <0x1bc 0x14>; 1542 }; 1543 lvts_efuse_data2: lvts2-calib@1d0 { 1544 reg = <0x1d0 0x38>; 1545 }; 1546 }; 1547 1548 u3phy2: t-phy@11c40000 { 1549 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3"; 1550 #address-cells = <1>; 1551 #size-cells = <1>; 1552 ranges = <0 0 0x11c40000 0x700>; 1553 status = "disabled"; 1554 1555 u2port2: usb-phy@0 { 1556 reg = <0x0 0x700>; 1557 clocks = <&topckgen CLK_TOP_SSUSB_PHY_P2_REF>; 1558 clock-names = "ref"; 1559 #phy-cells = <1>; 1560 }; 1561 }; 1562 1563 u3phy3: t-phy@11c50000 { 1564 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3"; 1565 #address-cells = <1>; 1566 #size-cells = <1>; 1567 ranges = <0 0 0x11c50000 0x700>; 1568 status = "disabled"; 1569 1570 u2port3: usb-phy@0 { 1571 reg = <0x0 0x700>; 1572 clocks = <&topckgen CLK_TOP_SSUSB_PHY_P3_REF>; 1573 clock-names = "ref"; 1574 #phy-cells = <1>; 1575 }; 1576 }; 1577 1578 i2c5: i2c@11d00000 { 1579 compatible = "mediatek,mt8195-i2c", 1580 "mediatek,mt8192-i2c"; 1581 reg = <0 0x11d00000 0 0x1000>, 1582 <0 0x10220580 0 0x80>; 1583 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH 0>; 1584 clock-div = <1>; 1585 clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C5>, 1586 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1587 clock-names = "main", "dma"; 1588 #address-cells = <1>; 1589 #size-cells = <0>; 1590 status = "disabled"; 1591 }; 1592 1593 i2c6: i2c@11d01000 { 1594 compatible = "mediatek,mt8195-i2c", 1595 "mediatek,mt8192-i2c"; 1596 reg = <0 0x11d01000 0 0x1000>, 1597 <0 0x10220600 0 0x80>; 1598 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH 0>; 1599 clock-div = <1>; 1600 clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C6>, 1601 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1602 clock-names = "main", "dma"; 1603 #address-cells = <1>; 1604 #size-cells = <0>; 1605 status = "disabled"; 1606 }; 1607 1608 i2c7: i2c@11d02000 { 1609 compatible = "mediatek,mt8195-i2c", 1610 "mediatek,mt8192-i2c"; 1611 reg = <0 0x11d02000 0 0x1000>, 1612 <0 0x10220680 0 0x80>; 1613 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>; 1614 clock-div = <1>; 1615 clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C7>, 1616 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1617 clock-names = "main", "dma"; 1618 #address-cells = <1>; 1619 #size-cells = <0>; 1620 status = "disabled"; 1621 }; 1622 1623 imp_iic_wrap_s: clock-controller@11d03000 { 1624 compatible = "mediatek,mt8195-imp_iic_wrap_s"; 1625 reg = <0 0x11d03000 0 0x1000>; 1626 #clock-cells = <1>; 1627 }; 1628 1629 i2c0: i2c@11e00000 { 1630 compatible = "mediatek,mt8195-i2c", 1631 "mediatek,mt8192-i2c"; 1632 reg = <0 0x11e00000 0 0x1000>, 1633 <0 0x10220080 0 0x80>; 1634 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH 0>; 1635 clock-div = <1>; 1636 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C0>, 1637 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1638 clock-names = "main", "dma"; 1639 #address-cells = <1>; 1640 #size-cells = <0>; 1641 status = "disabled"; 1642 }; 1643 1644 i2c1: i2c@11e01000 { 1645 compatible = "mediatek,mt8195-i2c", 1646 "mediatek,mt8192-i2c"; 1647 reg = <0 0x11e01000 0 0x1000>, 1648 <0 0x10220200 0 0x80>; 1649 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH 0>; 1650 clock-div = <1>; 1651 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C1>, 1652 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1653 clock-names = "main", "dma"; 1654 #address-cells = <1>; 1655 #size-cells = <0>; 1656 status = "disabled"; 1657 }; 1658 1659 i2c2: i2c@11e02000 { 1660 compatible = "mediatek,mt8195-i2c", 1661 "mediatek,mt8192-i2c"; 1662 reg = <0 0x11e02000 0 0x1000>, 1663 <0 0x10220380 0 0x80>; 1664 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH 0>; 1665 clock-div = <1>; 1666 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C2>, 1667 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1668 clock-names = "main", "dma"; 1669 #address-cells = <1>; 1670 #size-cells = <0>; 1671 status = "disabled"; 1672 }; 1673 1674 i2c3: i2c@11e03000 { 1675 compatible = "mediatek,mt8195-i2c", 1676 "mediatek,mt8192-i2c"; 1677 reg = <0 0x11e03000 0 0x1000>, 1678 <0 0x10220480 0 0x80>; 1679 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH 0>; 1680 clock-div = <1>; 1681 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C3>, 1682 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1683 clock-names = "main", "dma"; 1684 #address-cells = <1>; 1685 #size-cells = <0>; 1686 status = "disabled"; 1687 }; 1688 1689 i2c4: i2c@11e04000 { 1690 compatible = "mediatek,mt8195-i2c", 1691 "mediatek,mt8192-i2c"; 1692 reg = <0 0x11e04000 0 0x1000>, 1693 <0 0x10220500 0 0x80>; 1694 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH 0>; 1695 clock-div = <1>; 1696 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C4>, 1697 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1698 clock-names = "main", "dma"; 1699 #address-cells = <1>; 1700 #size-cells = <0>; 1701 status = "disabled"; 1702 }; 1703 1704 imp_iic_wrap_w: clock-controller@11e05000 { 1705 compatible = "mediatek,mt8195-imp_iic_wrap_w"; 1706 reg = <0 0x11e05000 0 0x1000>; 1707 #clock-cells = <1>; 1708 }; 1709 1710 u3phy1: t-phy@11e30000 { 1711 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3"; 1712 #address-cells = <1>; 1713 #size-cells = <1>; 1714 ranges = <0 0 0x11e30000 0xe00>; 1715 power-domains = <&spm MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY>; 1716 status = "disabled"; 1717 1718 u2port1: usb-phy@0 { 1719 reg = <0x0 0x700>; 1720 clocks = <&topckgen CLK_TOP_SSUSB_PHY_P1_REF>, 1721 <&clk26m>; 1722 clock-names = "ref", "da_ref"; 1723 #phy-cells = <1>; 1724 }; 1725 1726 u3port1: usb-phy@700 { 1727 reg = <0x700 0x700>; 1728 clocks = <&apmixedsys CLK_APMIXED_PLL_SSUSB26M>, 1729 <&topckgen CLK_TOP_SSUSB_PHY_P1_REF>; 1730 clock-names = "ref", "da_ref"; 1731 nvmem-cells = <&comb_intr_p1>, 1732 <&comb_rx_imp_p1>, 1733 <&comb_tx_imp_p1>; 1734 nvmem-cell-names = "intr", "rx_imp", "tx_imp"; 1735 #phy-cells = <1>; 1736 }; 1737 }; 1738 1739 u3phy0: t-phy@11e40000 { 1740 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3"; 1741 #address-cells = <1>; 1742 #size-cells = <1>; 1743 ranges = <0 0 0x11e40000 0xe00>; 1744 status = "disabled"; 1745 1746 u2port0: usb-phy@0 { 1747 reg = <0x0 0x700>; 1748 clocks = <&topckgen CLK_TOP_SSUSB_PHY_REF>, 1749 <&clk26m>; 1750 clock-names = "ref", "da_ref"; 1751 #phy-cells = <1>; 1752 }; 1753 1754 u3port0: usb-phy@700 { 1755 reg = <0x700 0x700>; 1756 clocks = <&apmixedsys CLK_APMIXED_PLL_SSUSB26M>, 1757 <&topckgen CLK_TOP_SSUSB_PHY_REF>; 1758 clock-names = "ref", "da_ref"; 1759 nvmem-cells = <&u3_intr_p0>, 1760 <&u3_rx_imp_p0>, 1761 <&u3_tx_imp_p0>; 1762 nvmem-cell-names = "intr", "rx_imp", "tx_imp"; 1763 #phy-cells = <1>; 1764 }; 1765 }; 1766 1767 pciephy: phy@11e80000 { 1768 compatible = "mediatek,mt8195-pcie-phy"; 1769 reg = <0 0x11e80000 0 0x10000>; 1770 reg-names = "sif"; 1771 nvmem-cells = <&pciephy_glb_intr>, <&pciephy_tx_ln0_pmos>, 1772 <&pciephy_tx_ln0_nmos>, <&pciephy_rx_ln0>, 1773 <&pciephy_tx_ln1_pmos>, <&pciephy_tx_ln1_nmos>, 1774 <&pciephy_rx_ln1>; 1775 nvmem-cell-names = "glb_intr", "tx_ln0_pmos", 1776 "tx_ln0_nmos", "rx_ln0", 1777 "tx_ln1_pmos", "tx_ln1_nmos", 1778 "rx_ln1"; 1779 power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_PHY>; 1780 #phy-cells = <0>; 1781 status = "disabled"; 1782 }; 1783 1784 ufsphy: ufs-phy@11fa0000 { 1785 compatible = "mediatek,mt8195-ufsphy", "mediatek,mt8183-ufsphy"; 1786 reg = <0 0x11fa0000 0 0xc000>; 1787 clocks = <&clk26m>, <&clk26m>; 1788 clock-names = "unipro", "mp"; 1789 #phy-cells = <0>; 1790 status = "disabled"; 1791 }; 1792 1793 mfgcfg: clock-controller@13fbf000 { 1794 compatible = "mediatek,mt8195-mfgcfg"; 1795 reg = <0 0x13fbf000 0 0x1000>; 1796 #clock-cells = <1>; 1797 }; 1798 1799 vppsys0: clock-controller@14000000 { 1800 compatible = "mediatek,mt8195-vppsys0"; 1801 reg = <0 0x14000000 0 0x1000>; 1802 #clock-cells = <1>; 1803 }; 1804 1805 smi_sub_common_vpp0_vpp1_2x1: smi@14010000 { 1806 compatible = "mediatek,mt8195-smi-sub-common"; 1807 reg = <0 0x14010000 0 0x1000>; 1808 clocks = <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>, 1809 <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>, 1810 <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>; 1811 clock-names = "apb", "smi", "gals0"; 1812 mediatek,smi = <&smi_common_vpp>; 1813 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; 1814 }; 1815 1816 smi_sub_common_vdec_vpp0_2x1: smi@14011000 { 1817 compatible = "mediatek,mt8195-smi-sub-common"; 1818 reg = <0 0x14011000 0 0x1000>; 1819 clocks = <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>, 1820 <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>, 1821 <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>; 1822 clock-names = "apb", "smi", "gals0"; 1823 mediatek,smi = <&smi_common_vpp>; 1824 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; 1825 }; 1826 1827 smi_common_vpp: smi@14012000 { 1828 compatible = "mediatek,mt8195-smi-common-vpp"; 1829 reg = <0 0x14012000 0 0x1000>; 1830 clocks = <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>, 1831 <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>, 1832 <&vppsys0 CLK_VPP0_SMI_RSI>, 1833 <&vppsys0 CLK_VPP0_SMI_RSI>; 1834 clock-names = "apb", "smi", "gals0", "gals1"; 1835 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; 1836 }; 1837 1838 larb4: larb@14013000 { 1839 compatible = "mediatek,mt8195-smi-larb"; 1840 reg = <0 0x14013000 0 0x1000>; 1841 mediatek,larb-id = <4>; 1842 mediatek,smi = <&smi_sub_common_vpp0_vpp1_2x1>; 1843 clocks = <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>, 1844 <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>; 1845 clock-names = "apb", "smi"; 1846 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; 1847 }; 1848 1849 iommu_vpp: iommu@14018000 { 1850 compatible = "mediatek,mt8195-iommu-vpp"; 1851 reg = <0 0x14018000 0 0x1000>; 1852 mediatek,larbs = <&larb1 &larb3 &larb4 &larb6 &larb8 1853 &larb12 &larb14 &larb16 &larb18 1854 &larb20 &larb22 &larb23 &larb26 1855 &larb27>; 1856 interrupts = <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH 0>; 1857 clocks = <&vppsys0 CLK_VPP0_SMI_IOMMU>; 1858 clock-names = "bclk"; 1859 #iommu-cells = <1>; 1860 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; 1861 }; 1862 1863 wpesys: clock-controller@14e00000 { 1864 compatible = "mediatek,mt8195-wpesys"; 1865 reg = <0 0x14e00000 0 0x1000>; 1866 #clock-cells = <1>; 1867 }; 1868 1869 wpesys_vpp0: clock-controller@14e02000 { 1870 compatible = "mediatek,mt8195-wpesys_vpp0"; 1871 reg = <0 0x14e02000 0 0x1000>; 1872 #clock-cells = <1>; 1873 }; 1874 1875 wpesys_vpp1: clock-controller@14e03000 { 1876 compatible = "mediatek,mt8195-wpesys_vpp1"; 1877 reg = <0 0x14e03000 0 0x1000>; 1878 #clock-cells = <1>; 1879 }; 1880 1881 larb7: larb@14e04000 { 1882 compatible = "mediatek,mt8195-smi-larb"; 1883 reg = <0 0x14e04000 0 0x1000>; 1884 mediatek,larb-id = <7>; 1885 mediatek,smi = <&smi_common_vdo>; 1886 clocks = <&wpesys CLK_WPE_SMI_LARB7>, 1887 <&wpesys CLK_WPE_SMI_LARB7>; 1888 clock-names = "apb", "smi"; 1889 power-domains = <&spm MT8195_POWER_DOMAIN_WPESYS>; 1890 }; 1891 1892 larb8: larb@14e05000 { 1893 compatible = "mediatek,mt8195-smi-larb"; 1894 reg = <0 0x14e05000 0 0x1000>; 1895 mediatek,larb-id = <8>; 1896 mediatek,smi = <&smi_common_vpp>; 1897 clocks = <&wpesys CLK_WPE_SMI_LARB8>, 1898 <&wpesys CLK_WPE_SMI_LARB8>, 1899 <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>; 1900 clock-names = "apb", "smi", "gals"; 1901 power-domains = <&spm MT8195_POWER_DOMAIN_WPESYS>; 1902 }; 1903 1904 vppsys1: clock-controller@14f00000 { 1905 compatible = "mediatek,mt8195-vppsys1"; 1906 reg = <0 0x14f00000 0 0x1000>; 1907 #clock-cells = <1>; 1908 }; 1909 1910 larb5: larb@14f02000 { 1911 compatible = "mediatek,mt8195-smi-larb"; 1912 reg = <0 0x14f02000 0 0x1000>; 1913 mediatek,larb-id = <5>; 1914 mediatek,smi = <&smi_common_vdo>; 1915 clocks = <&vppsys1 CLK_VPP1_VPPSYS1_LARB>, 1916 <&vppsys1 CLK_VPP1_VPPSYS1_GALS>, 1917 <&vppsys0 CLK_VPP0_GALS_VPP1_LARB5>; 1918 clock-names = "apb", "smi", "gals"; 1919 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 1920 }; 1921 1922 larb6: larb@14f03000 { 1923 compatible = "mediatek,mt8195-smi-larb"; 1924 reg = <0 0x14f03000 0 0x1000>; 1925 mediatek,larb-id = <6>; 1926 mediatek,smi = <&smi_sub_common_vpp0_vpp1_2x1>; 1927 clocks = <&vppsys1 CLK_VPP1_VPPSYS1_LARB>, 1928 <&vppsys1 CLK_VPP1_VPPSYS1_GALS>, 1929 <&vppsys0 CLK_VPP0_GALS_VPP1_LARB6>; 1930 clock-names = "apb", "smi", "gals"; 1931 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 1932 }; 1933 1934 imgsys: clock-controller@15000000 { 1935 compatible = "mediatek,mt8195-imgsys"; 1936 reg = <0 0x15000000 0 0x1000>; 1937 #clock-cells = <1>; 1938 }; 1939 1940 larb9: larb@15001000 { 1941 compatible = "mediatek,mt8195-smi-larb"; 1942 reg = <0 0x15001000 0 0x1000>; 1943 mediatek,larb-id = <9>; 1944 mediatek,smi = <&smi_sub_common_img1_3x1>; 1945 clocks = <&imgsys CLK_IMG_LARB9>, 1946 <&imgsys CLK_IMG_LARB9>, 1947 <&imgsys CLK_IMG_GALS>; 1948 clock-names = "apb", "smi", "gals"; 1949 power-domains = <&spm MT8195_POWER_DOMAIN_IMG>; 1950 }; 1951 1952 smi_sub_common_img0_3x1: smi@15002000 { 1953 compatible = "mediatek,mt8195-smi-sub-common"; 1954 reg = <0 0x15002000 0 0x1000>; 1955 clocks = <&imgsys CLK_IMG_IPE>, 1956 <&imgsys CLK_IMG_IPE>, 1957 <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>; 1958 clock-names = "apb", "smi", "gals0"; 1959 mediatek,smi = <&smi_common_vpp>; 1960 power-domains = <&spm MT8195_POWER_DOMAIN_IMG>; 1961 }; 1962 1963 smi_sub_common_img1_3x1: smi@15003000 { 1964 compatible = "mediatek,mt8195-smi-sub-common"; 1965 reg = <0 0x15003000 0 0x1000>; 1966 clocks = <&imgsys CLK_IMG_LARB9>, 1967 <&imgsys CLK_IMG_LARB9>, 1968 <&imgsys CLK_IMG_GALS>; 1969 clock-names = "apb", "smi", "gals0"; 1970 mediatek,smi = <&smi_common_vdo>; 1971 power-domains = <&spm MT8195_POWER_DOMAIN_IMG>; 1972 }; 1973 1974 imgsys1_dip_top: clock-controller@15110000 { 1975 compatible = "mediatek,mt8195-imgsys1_dip_top"; 1976 reg = <0 0x15110000 0 0x1000>; 1977 #clock-cells = <1>; 1978 }; 1979 1980 larb10: larb@15120000 { 1981 compatible = "mediatek,mt8195-smi-larb"; 1982 reg = <0 0x15120000 0 0x1000>; 1983 mediatek,larb-id = <10>; 1984 mediatek,smi = <&smi_sub_common_img1_3x1>; 1985 clocks = <&imgsys CLK_IMG_DIP0>, 1986 <&imgsys1_dip_top CLK_IMG1_DIP_TOP_LARB10>; 1987 clock-names = "apb", "smi"; 1988 power-domains = <&spm MT8195_POWER_DOMAIN_DIP>; 1989 }; 1990 1991 imgsys1_dip_nr: clock-controller@15130000 { 1992 compatible = "mediatek,mt8195-imgsys1_dip_nr"; 1993 reg = <0 0x15130000 0 0x1000>; 1994 #clock-cells = <1>; 1995 }; 1996 1997 imgsys1_wpe: clock-controller@15220000 { 1998 compatible = "mediatek,mt8195-imgsys1_wpe"; 1999 reg = <0 0x15220000 0 0x1000>; 2000 #clock-cells = <1>; 2001 }; 2002 2003 larb11: larb@15230000 { 2004 compatible = "mediatek,mt8195-smi-larb"; 2005 reg = <0 0x15230000 0 0x1000>; 2006 mediatek,larb-id = <11>; 2007 mediatek,smi = <&smi_sub_common_img1_3x1>; 2008 clocks = <&imgsys CLK_IMG_WPE0>, 2009 <&imgsys1_wpe CLK_IMG1_WPE_LARB11>; 2010 clock-names = "apb", "smi"; 2011 power-domains = <&spm MT8195_POWER_DOMAIN_DIP>; 2012 }; 2013 2014 ipesys: clock-controller@15330000 { 2015 compatible = "mediatek,mt8195-ipesys"; 2016 reg = <0 0x15330000 0 0x1000>; 2017 #clock-cells = <1>; 2018 }; 2019 2020 larb12: larb@15340000 { 2021 compatible = "mediatek,mt8195-smi-larb"; 2022 reg = <0 0x15340000 0 0x1000>; 2023 mediatek,larb-id = <12>; 2024 mediatek,smi = <&smi_sub_common_img0_3x1>; 2025 clocks = <&ipesys CLK_IPE_SMI_LARB12>, 2026 <&ipesys CLK_IPE_SMI_LARB12>; 2027 clock-names = "apb", "smi"; 2028 power-domains = <&spm MT8195_POWER_DOMAIN_IPE>; 2029 }; 2030 2031 camsys: clock-controller@16000000 { 2032 compatible = "mediatek,mt8195-camsys"; 2033 reg = <0 0x16000000 0 0x1000>; 2034 #clock-cells = <1>; 2035 }; 2036 2037 larb13: larb@16001000 { 2038 compatible = "mediatek,mt8195-smi-larb"; 2039 reg = <0 0x16001000 0 0x1000>; 2040 mediatek,larb-id = <13>; 2041 mediatek,smi = <&smi_sub_common_cam_4x1>; 2042 clocks = <&camsys CLK_CAM_LARB13>, 2043 <&camsys CLK_CAM_LARB13>, 2044 <&camsys CLK_CAM_CAM2MM0_GALS>; 2045 clock-names = "apb", "smi", "gals"; 2046 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>; 2047 }; 2048 2049 larb14: larb@16002000 { 2050 compatible = "mediatek,mt8195-smi-larb"; 2051 reg = <0 0x16002000 0 0x1000>; 2052 mediatek,larb-id = <14>; 2053 mediatek,smi = <&smi_sub_common_cam_7x1>; 2054 clocks = <&camsys CLK_CAM_LARB14>, 2055 <&camsys CLK_CAM_LARB14>; 2056 clock-names = "apb", "smi"; 2057 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>; 2058 }; 2059 2060 smi_sub_common_cam_4x1: smi@16004000 { 2061 compatible = "mediatek,mt8195-smi-sub-common"; 2062 reg = <0 0x16004000 0 0x1000>; 2063 clocks = <&camsys CLK_CAM_LARB13>, 2064 <&camsys CLK_CAM_LARB13>, 2065 <&camsys CLK_CAM_CAM2MM0_GALS>; 2066 clock-names = "apb", "smi", "gals0"; 2067 mediatek,smi = <&smi_common_vdo>; 2068 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>; 2069 }; 2070 2071 smi_sub_common_cam_7x1: smi@16005000 { 2072 compatible = "mediatek,mt8195-smi-sub-common"; 2073 reg = <0 0x16005000 0 0x1000>; 2074 clocks = <&camsys CLK_CAM_LARB14>, 2075 <&camsys CLK_CAM_CAM2MM1_GALS>, 2076 <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>; 2077 clock-names = "apb", "smi", "gals0"; 2078 mediatek,smi = <&smi_common_vpp>; 2079 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>; 2080 }; 2081 2082 larb16: larb@16012000 { 2083 compatible = "mediatek,mt8195-smi-larb"; 2084 reg = <0 0x16012000 0 0x1000>; 2085 mediatek,larb-id = <16>; 2086 mediatek,smi = <&smi_sub_common_cam_7x1>; 2087 clocks = <&camsys_rawa CLK_CAM_RAWA_LARBX>, 2088 <&camsys_rawa CLK_CAM_RAWA_LARBX>; 2089 clock-names = "apb", "smi"; 2090 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWA>; 2091 }; 2092 2093 larb17: larb@16013000 { 2094 compatible = "mediatek,mt8195-smi-larb"; 2095 reg = <0 0x16013000 0 0x1000>; 2096 mediatek,larb-id = <17>; 2097 mediatek,smi = <&smi_sub_common_cam_4x1>; 2098 clocks = <&camsys_yuva CLK_CAM_YUVA_LARBX>, 2099 <&camsys_yuva CLK_CAM_YUVA_LARBX>; 2100 clock-names = "apb", "smi"; 2101 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWA>; 2102 }; 2103 2104 larb27: larb@16014000 { 2105 compatible = "mediatek,mt8195-smi-larb"; 2106 reg = <0 0x16014000 0 0x1000>; 2107 mediatek,larb-id = <27>; 2108 mediatek,smi = <&smi_sub_common_cam_7x1>; 2109 clocks = <&camsys_rawb CLK_CAM_RAWB_LARBX>, 2110 <&camsys_rawb CLK_CAM_RAWB_LARBX>; 2111 clock-names = "apb", "smi"; 2112 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWB>; 2113 }; 2114 2115 larb28: larb@16015000 { 2116 compatible = "mediatek,mt8195-smi-larb"; 2117 reg = <0 0x16015000 0 0x1000>; 2118 mediatek,larb-id = <28>; 2119 mediatek,smi = <&smi_sub_common_cam_4x1>; 2120 clocks = <&camsys_yuvb CLK_CAM_YUVB_LARBX>, 2121 <&camsys_yuvb CLK_CAM_YUVB_LARBX>; 2122 clock-names = "apb", "smi"; 2123 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWB>; 2124 }; 2125 2126 camsys_rawa: clock-controller@1604f000 { 2127 compatible = "mediatek,mt8195-camsys_rawa"; 2128 reg = <0 0x1604f000 0 0x1000>; 2129 #clock-cells = <1>; 2130 }; 2131 2132 camsys_yuva: clock-controller@1606f000 { 2133 compatible = "mediatek,mt8195-camsys_yuva"; 2134 reg = <0 0x1606f000 0 0x1000>; 2135 #clock-cells = <1>; 2136 }; 2137 2138 camsys_rawb: clock-controller@1608f000 { 2139 compatible = "mediatek,mt8195-camsys_rawb"; 2140 reg = <0 0x1608f000 0 0x1000>; 2141 #clock-cells = <1>; 2142 }; 2143 2144 camsys_yuvb: clock-controller@160af000 { 2145 compatible = "mediatek,mt8195-camsys_yuvb"; 2146 reg = <0 0x160af000 0 0x1000>; 2147 #clock-cells = <1>; 2148 }; 2149 2150 camsys_mraw: clock-controller@16140000 { 2151 compatible = "mediatek,mt8195-camsys_mraw"; 2152 reg = <0 0x16140000 0 0x1000>; 2153 #clock-cells = <1>; 2154 }; 2155 2156 larb25: larb@16141000 { 2157 compatible = "mediatek,mt8195-smi-larb"; 2158 reg = <0 0x16141000 0 0x1000>; 2159 mediatek,larb-id = <25>; 2160 mediatek,smi = <&smi_sub_common_cam_4x1>; 2161 clocks = <&camsys CLK_CAM_LARB13>, 2162 <&camsys_mraw CLK_CAM_MRAW_LARBX>, 2163 <&camsys CLK_CAM_CAM2MM0_GALS>; 2164 clock-names = "apb", "smi", "gals"; 2165 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_MRAW>; 2166 }; 2167 2168 larb26: larb@16142000 { 2169 compatible = "mediatek,mt8195-smi-larb"; 2170 reg = <0 0x16142000 0 0x1000>; 2171 mediatek,larb-id = <26>; 2172 mediatek,smi = <&smi_sub_common_cam_7x1>; 2173 clocks = <&camsys_mraw CLK_CAM_MRAW_LARBX>, 2174 <&camsys_mraw CLK_CAM_MRAW_LARBX>; 2175 clock-names = "apb", "smi"; 2176 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_MRAW>; 2177 2178 }; 2179 2180 ccusys: clock-controller@17200000 { 2181 compatible = "mediatek,mt8195-ccusys"; 2182 reg = <0 0x17200000 0 0x1000>; 2183 #clock-cells = <1>; 2184 }; 2185 2186 larb18: larb@17201000 { 2187 compatible = "mediatek,mt8195-smi-larb"; 2188 reg = <0 0x17201000 0 0x1000>; 2189 mediatek,larb-id = <18>; 2190 mediatek,smi = <&smi_sub_common_cam_7x1>; 2191 clocks = <&ccusys CLK_CCU_LARB18>, 2192 <&ccusys CLK_CCU_LARB18>; 2193 clock-names = "apb", "smi"; 2194 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>; 2195 }; 2196 2197 larb24: larb@1800d000 { 2198 compatible = "mediatek,mt8195-smi-larb"; 2199 reg = <0 0x1800d000 0 0x1000>; 2200 mediatek,larb-id = <24>; 2201 mediatek,smi = <&smi_common_vdo>; 2202 clocks = <&vdecsys_soc CLK_VDEC_SOC_LARB1>, 2203 <&vdecsys_soc CLK_VDEC_SOC_LARB1>; 2204 clock-names = "apb", "smi"; 2205 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>; 2206 }; 2207 2208 larb23: larb@1800e000 { 2209 compatible = "mediatek,mt8195-smi-larb"; 2210 reg = <0 0x1800e000 0 0x1000>; 2211 mediatek,larb-id = <23>; 2212 mediatek,smi = <&smi_sub_common_vdec_vpp0_2x1>; 2213 clocks = <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>, 2214 <&vdecsys_soc CLK_VDEC_SOC_LARB1>; 2215 clock-names = "apb", "smi"; 2216 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>; 2217 }; 2218 2219 vdecsys_soc: clock-controller@1800f000 { 2220 compatible = "mediatek,mt8195-vdecsys_soc"; 2221 reg = <0 0x1800f000 0 0x1000>; 2222 #clock-cells = <1>; 2223 }; 2224 2225 larb21: larb@1802e000 { 2226 compatible = "mediatek,mt8195-smi-larb"; 2227 reg = <0 0x1802e000 0 0x1000>; 2228 mediatek,larb-id = <21>; 2229 mediatek,smi = <&smi_common_vdo>; 2230 clocks = <&vdecsys CLK_VDEC_LARB1>, 2231 <&vdecsys CLK_VDEC_LARB1>; 2232 clock-names = "apb", "smi"; 2233 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>; 2234 }; 2235 2236 vdecsys: clock-controller@1802f000 { 2237 compatible = "mediatek,mt8195-vdecsys"; 2238 reg = <0 0x1802f000 0 0x1000>; 2239 #clock-cells = <1>; 2240 }; 2241 2242 larb22: larb@1803e000 { 2243 compatible = "mediatek,mt8195-smi-larb"; 2244 reg = <0 0x1803e000 0 0x1000>; 2245 mediatek,larb-id = <22>; 2246 mediatek,smi = <&smi_sub_common_vdec_vpp0_2x1>; 2247 clocks = <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>, 2248 <&vdecsys_core1 CLK_VDEC_CORE1_LARB1>; 2249 clock-names = "apb", "smi"; 2250 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC2>; 2251 }; 2252 2253 vdecsys_core1: clock-controller@1803f000 { 2254 compatible = "mediatek,mt8195-vdecsys_core1"; 2255 reg = <0 0x1803f000 0 0x1000>; 2256 #clock-cells = <1>; 2257 }; 2258 2259 apusys_pll: clock-controller@190f3000 { 2260 compatible = "mediatek,mt8195-apusys_pll"; 2261 reg = <0 0x190f3000 0 0x1000>; 2262 #clock-cells = <1>; 2263 }; 2264 2265 vencsys: clock-controller@1a000000 { 2266 compatible = "mediatek,mt8195-vencsys"; 2267 reg = <0 0x1a000000 0 0x1000>; 2268 #clock-cells = <1>; 2269 }; 2270 2271 larb19: larb@1a010000 { 2272 compatible = "mediatek,mt8195-smi-larb"; 2273 reg = <0 0x1a010000 0 0x1000>; 2274 mediatek,larb-id = <19>; 2275 mediatek,smi = <&smi_common_vdo>; 2276 clocks = <&vencsys CLK_VENC_VENC>, 2277 <&vencsys CLK_VENC_GALS>; 2278 clock-names = "apb", "smi"; 2279 power-domains = <&spm MT8195_POWER_DOMAIN_VENC>; 2280 }; 2281 2282 venc: video-codec@1a020000 { 2283 compatible = "mediatek,mt8195-vcodec-enc"; 2284 reg = <0 0x1a020000 0 0x10000>; 2285 iommus = <&iommu_vdo M4U_PORT_L19_VENC_RCPU>, 2286 <&iommu_vdo M4U_PORT_L19_VENC_REC>, 2287 <&iommu_vdo M4U_PORT_L19_VENC_BSDMA>, 2288 <&iommu_vdo M4U_PORT_L19_VENC_SV_COMV>, 2289 <&iommu_vdo M4U_PORT_L19_VENC_RD_COMV>, 2290 <&iommu_vdo M4U_PORT_L19_VENC_CUR_LUMA>, 2291 <&iommu_vdo M4U_PORT_L19_VENC_CUR_CHROMA>, 2292 <&iommu_vdo M4U_PORT_L19_VENC_REF_LUMA>, 2293 <&iommu_vdo M4U_PORT_L19_VENC_REF_CHROMA>; 2294 interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH 0>; 2295 mediatek,scp = <&scp>; 2296 clocks = <&vencsys CLK_VENC_VENC>; 2297 clock-names = "venc_sel"; 2298 assigned-clocks = <&topckgen CLK_TOP_VENC>; 2299 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>; 2300 power-domains = <&spm MT8195_POWER_DOMAIN_VENC>; 2301 #address-cells = <2>; 2302 #size-cells = <2>; 2303 dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>; 2304 }; 2305 2306 jpgdec-master { 2307 compatible = "mediatek,mt8195-jpgdec"; 2308 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>; 2309 iommus = <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA0>, 2310 <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA0>, 2311 <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA1>, 2312 <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA1>, 2313 <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>, 2314 <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>; 2315 dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>; 2316 #address-cells = <2>; 2317 #size-cells = <2>; 2318 ranges; 2319 2320 jpgdec@1a040000 { 2321 compatible = "mediatek,mt8195-jpgdec-hw"; 2322 reg = <0 0x1a040000 0 0x10000>;/* JPGDEC_C0 */ 2323 iommus = <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA0>, 2324 <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA0>, 2325 <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA1>, 2326 <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA1>, 2327 <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>, 2328 <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>; 2329 interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH 0>; 2330 clocks = <&vencsys CLK_VENC_JPGDEC>; 2331 clock-names = "jpgdec"; 2332 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>; 2333 }; 2334 2335 jpgdec@1a050000 { 2336 compatible = "mediatek,mt8195-jpgdec-hw"; 2337 reg = <0 0x1a050000 0 0x10000>;/* JPGDEC_C1 */ 2338 iommus = <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA0>, 2339 <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA0>, 2340 <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA1>, 2341 <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA1>, 2342 <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>, 2343 <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>; 2344 interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH 0>; 2345 clocks = <&vencsys CLK_VENC_JPGDEC_C1>; 2346 clock-names = "jpgdec"; 2347 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>; 2348 }; 2349 2350 jpgdec@1b040000 { 2351 compatible = "mediatek,mt8195-jpgdec-hw"; 2352 reg = <0 0x1b040000 0 0x10000>;/* JPGDEC_C2 */ 2353 iommus = <&iommu_vpp M4U_PORT_L20_JPGDEC_WDMA0>, 2354 <&iommu_vpp M4U_PORT_L20_JPGDEC_BSDMA0>, 2355 <&iommu_vpp M4U_PORT_L20_JPGDEC_WDMA1>, 2356 <&iommu_vpp M4U_PORT_L20_JPGDEC_BSDMA1>, 2357 <&iommu_vpp M4U_PORT_L20_JPGDEC_BUFF_OFFSET1>, 2358 <&iommu_vpp M4U_PORT_L20_JPGDEC_BUFF_OFFSET0>; 2359 interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH 0>; 2360 clocks = <&vencsys_core1 CLK_VENC_CORE1_JPGDEC>; 2361 clock-names = "jpgdec"; 2362 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC2>; 2363 }; 2364 }; 2365 2366 vencsys_core1: clock-controller@1b000000 { 2367 compatible = "mediatek,mt8195-vencsys_core1"; 2368 reg = <0 0x1b000000 0 0x1000>; 2369 #clock-cells = <1>; 2370 }; 2371 2372 vdosys0: syscon@1c01a000 { 2373 compatible = "mediatek,mt8195-mmsys", "syscon"; 2374 reg = <0 0x1c01a000 0 0x1000>; 2375 mboxes = <&gce0 0 CMDQ_THR_PRIO_4>; 2376 #clock-cells = <1>; 2377 }; 2378 2379 2380 jpgenc-master { 2381 compatible = "mediatek,mt8195-jpgenc"; 2382 power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>; 2383 iommus = <&iommu_vpp M4U_PORT_L20_JPGENC_Y_RDMA>, 2384 <&iommu_vpp M4U_PORT_L20_JPGENC_C_RDMA>, 2385 <&iommu_vpp M4U_PORT_L20_JPGENC_Q_TABLE>, 2386 <&iommu_vpp M4U_PORT_L20_JPGENC_BSDMA>; 2387 dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>; 2388 #address-cells = <2>; 2389 #size-cells = <2>; 2390 ranges; 2391 2392 jpgenc@1a030000 { 2393 compatible = "mediatek,mt8195-jpgenc-hw"; 2394 reg = <0 0x1a030000 0 0x10000>; 2395 iommus = <&iommu_vdo M4U_PORT_L19_JPGENC_Y_RDMA>, 2396 <&iommu_vdo M4U_PORT_L19_JPGENC_C_RDMA>, 2397 <&iommu_vdo M4U_PORT_L19_JPGENC_Q_TABLE>, 2398 <&iommu_vdo M4U_PORT_L19_JPGENC_BSDMA>; 2399 interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH 0>; 2400 clocks = <&vencsys CLK_VENC_JPGENC>; 2401 clock-names = "jpgenc"; 2402 power-domains = <&spm MT8195_POWER_DOMAIN_VENC>; 2403 }; 2404 2405 jpgenc@1b030000 { 2406 compatible = "mediatek,mt8195-jpgenc-hw"; 2407 reg = <0 0x1b030000 0 0x10000>; 2408 iommus = <&iommu_vpp M4U_PORT_L20_JPGENC_Y_RDMA>, 2409 <&iommu_vpp M4U_PORT_L20_JPGENC_C_RDMA>, 2410 <&iommu_vpp M4U_PORT_L20_JPGENC_Q_TABLE>, 2411 <&iommu_vpp M4U_PORT_L20_JPGENC_BSDMA>; 2412 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH 0>; 2413 clocks = <&vencsys_core1 CLK_VENC_CORE1_JPGENC>; 2414 clock-names = "jpgenc"; 2415 power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>; 2416 }; 2417 }; 2418 2419 larb20: larb@1b010000 { 2420 compatible = "mediatek,mt8195-smi-larb"; 2421 reg = <0 0x1b010000 0 0x1000>; 2422 mediatek,larb-id = <20>; 2423 mediatek,smi = <&smi_common_vpp>; 2424 clocks = <&vencsys_core1 CLK_VENC_CORE1_LARB>, 2425 <&vencsys_core1 CLK_VENC_CORE1_GALS>, 2426 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>; 2427 clock-names = "apb", "smi", "gals"; 2428 power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>; 2429 }; 2430 2431 ovl0: ovl@1c000000 { 2432 compatible = "mediatek,mt8195-disp-ovl", "mediatek,mt8183-disp-ovl"; 2433 reg = <0 0x1c000000 0 0x1000>; 2434 interrupts = <GIC_SPI 636 IRQ_TYPE_LEVEL_HIGH 0>; 2435 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2436 clocks = <&vdosys0 CLK_VDO0_DISP_OVL0>; 2437 iommus = <&iommu_vdo M4U_PORT_L0_DISP_OVL0_RDMA0>; 2438 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x0000 0x1000>; 2439 }; 2440 2441 rdma0: rdma@1c002000 { 2442 compatible = "mediatek,mt8195-disp-rdma"; 2443 reg = <0 0x1c002000 0 0x1000>; 2444 interrupts = <GIC_SPI 638 IRQ_TYPE_LEVEL_HIGH 0>; 2445 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2446 clocks = <&vdosys0 CLK_VDO0_DISP_RDMA0>; 2447 iommus = <&iommu_vdo M4U_PORT_L0_DISP_RDMA0>; 2448 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x2000 0x1000>; 2449 }; 2450 2451 color0: color@1c003000 { 2452 compatible = "mediatek,mt8195-disp-color", "mediatek,mt8173-disp-color"; 2453 reg = <0 0x1c003000 0 0x1000>; 2454 interrupts = <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH 0>; 2455 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2456 clocks = <&vdosys0 CLK_VDO0_DISP_COLOR0>; 2457 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x3000 0x1000>; 2458 }; 2459 2460 ccorr0: ccorr@1c004000 { 2461 compatible = "mediatek,mt8195-disp-ccorr", "mediatek,mt8192-disp-ccorr"; 2462 reg = <0 0x1c004000 0 0x1000>; 2463 interrupts = <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH 0>; 2464 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2465 clocks = <&vdosys0 CLK_VDO0_DISP_CCORR0>; 2466 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x4000 0x1000>; 2467 }; 2468 2469 aal0: aal@1c005000 { 2470 compatible = "mediatek,mt8195-disp-aal", "mediatek,mt8183-disp-aal"; 2471 reg = <0 0x1c005000 0 0x1000>; 2472 interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH 0>; 2473 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2474 clocks = <&vdosys0 CLK_VDO0_DISP_AAL0>; 2475 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x5000 0x1000>; 2476 }; 2477 2478 gamma0: gamma@1c006000 { 2479 compatible = "mediatek,mt8195-disp-gamma", "mediatek,mt8183-disp-gamma"; 2480 reg = <0 0x1c006000 0 0x1000>; 2481 interrupts = <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH 0>; 2482 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2483 clocks = <&vdosys0 CLK_VDO0_DISP_GAMMA0>; 2484 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x6000 0x1000>; 2485 }; 2486 2487 dither0: dither@1c007000 { 2488 compatible = "mediatek,mt8195-disp-dither", "mediatek,mt8183-disp-dither"; 2489 reg = <0 0x1c007000 0 0x1000>; 2490 interrupts = <GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH 0>; 2491 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2492 clocks = <&vdosys0 CLK_VDO0_DISP_DITHER0>; 2493 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x7000 0x1000>; 2494 }; 2495 2496 dsc0: dsc@1c009000 { 2497 compatible = "mediatek,mt8195-disp-dsc"; 2498 reg = <0 0x1c009000 0 0x1000>; 2499 interrupts = <GIC_SPI 645 IRQ_TYPE_LEVEL_HIGH 0>; 2500 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2501 clocks = <&vdosys0 CLK_VDO0_DSC_WRAP0>; 2502 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x9000 0x1000>; 2503 }; 2504 2505 merge0: merge@1c014000 { 2506 compatible = "mediatek,mt8195-disp-merge"; 2507 reg = <0 0x1c014000 0 0x1000>; 2508 interrupts = <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH 0>; 2509 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2510 clocks = <&vdosys0 CLK_VDO0_VPP_MERGE0>; 2511 mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0x4000 0x1000>; 2512 }; 2513 2514 dp_intf0: dp-intf@1c015000 { 2515 compatible = "mediatek,mt8195-dp-intf"; 2516 reg = <0 0x1c015000 0 0x1000>; 2517 interrupts = <GIC_SPI 657 IRQ_TYPE_LEVEL_HIGH 0>; 2518 clocks = <&vdosys0 CLK_VDO0_DP_INTF0>, 2519 <&vdosys0 CLK_VDO0_DP_INTF0_DP_INTF>, 2520 <&apmixedsys CLK_APMIXED_TVDPLL1>; 2521 clock-names = "engine", "pixel", "pll"; 2522 status = "disabled"; 2523 }; 2524 2525 mutex: mutex@1c016000 { 2526 compatible = "mediatek,mt8195-disp-mutex"; 2527 reg = <0 0x1c016000 0 0x1000>; 2528 interrupts = <GIC_SPI 658 IRQ_TYPE_LEVEL_HIGH 0>; 2529 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2530 clocks = <&vdosys0 CLK_VDO0_DISP_MUTEX0>; 2531 mediatek,gce-events = <CMDQ_EVENT_VDO0_DISP_STREAM_DONE_0>; 2532 }; 2533 2534 larb0: larb@1c018000 { 2535 compatible = "mediatek,mt8195-smi-larb"; 2536 reg = <0 0x1c018000 0 0x1000>; 2537 mediatek,larb-id = <0>; 2538 mediatek,smi = <&smi_common_vdo>; 2539 clocks = <&vdosys0 CLK_VDO0_SMI_LARB>, 2540 <&vdosys0 CLK_VDO0_SMI_LARB>, 2541 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB0>; 2542 clock-names = "apb", "smi", "gals"; 2543 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2544 }; 2545 2546 larb1: larb@1c019000 { 2547 compatible = "mediatek,mt8195-smi-larb"; 2548 reg = <0 0x1c019000 0 0x1000>; 2549 mediatek,larb-id = <1>; 2550 mediatek,smi = <&smi_common_vpp>; 2551 clocks = <&vdosys0 CLK_VDO0_SMI_LARB>, 2552 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>, 2553 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB1>; 2554 clock-names = "apb", "smi", "gals"; 2555 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2556 }; 2557 2558 vdosys1: syscon@1c100000 { 2559 compatible = "mediatek,mt8195-mmsys", "syscon"; 2560 reg = <0 0x1c100000 0 0x1000>; 2561 #clock-cells = <1>; 2562 }; 2563 2564 smi_common_vdo: smi@1c01b000 { 2565 compatible = "mediatek,mt8195-smi-common-vdo"; 2566 reg = <0 0x1c01b000 0 0x1000>; 2567 clocks = <&vdosys0 CLK_VDO0_SMI_COMMON>, 2568 <&vdosys0 CLK_VDO0_SMI_EMI>, 2569 <&vdosys0 CLK_VDO0_SMI_RSI>, 2570 <&vdosys0 CLK_VDO0_SMI_GALS>; 2571 clock-names = "apb", "smi", "gals0", "gals1"; 2572 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2573 2574 }; 2575 2576 iommu_vdo: iommu@1c01f000 { 2577 compatible = "mediatek,mt8195-iommu-vdo"; 2578 reg = <0 0x1c01f000 0 0x1000>; 2579 mediatek,larbs = <&larb0 &larb2 &larb5 &larb7 &larb9 2580 &larb10 &larb11 &larb13 &larb17 2581 &larb19 &larb21 &larb24 &larb25 2582 &larb28>; 2583 interrupts = <GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH 0>; 2584 #iommu-cells = <1>; 2585 clocks = <&vdosys0 CLK_VDO0_SMI_IOMMU>; 2586 clock-names = "bclk"; 2587 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2588 }; 2589 2590 larb2: larb@1c102000 { 2591 compatible = "mediatek,mt8195-smi-larb"; 2592 reg = <0 0x1c102000 0 0x1000>; 2593 mediatek,larb-id = <2>; 2594 mediatek,smi = <&smi_common_vdo>; 2595 clocks = <&vdosys1 CLK_VDO1_SMI_LARB2>, 2596 <&vdosys1 CLK_VDO1_SMI_LARB2>, 2597 <&vdosys1 CLK_VDO1_GALS>; 2598 clock-names = "apb", "smi", "gals"; 2599 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 2600 }; 2601 2602 larb3: larb@1c103000 { 2603 compatible = "mediatek,mt8195-smi-larb"; 2604 reg = <0 0x1c103000 0 0x1000>; 2605 mediatek,larb-id = <3>; 2606 mediatek,smi = <&smi_common_vpp>; 2607 clocks = <&vdosys1 CLK_VDO1_SMI_LARB3>, 2608 <&vdosys1 CLK_VDO1_GALS>, 2609 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>; 2610 clock-names = "apb", "smi", "gals"; 2611 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 2612 }; 2613 2614 dp_intf1: dp-intf@1c113000 { 2615 compatible = "mediatek,mt8195-dp-intf"; 2616 reg = <0 0x1c113000 0 0x1000>; 2617 interrupts = <GIC_SPI 513 IRQ_TYPE_LEVEL_HIGH 0>; 2618 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 2619 clocks = <&vdosys1 CLK_VDO1_DP_INTF0_MM>, 2620 <&vdosys1 CLK_VDO1_DPINTF>, 2621 <&apmixedsys CLK_APMIXED_TVDPLL2>; 2622 clock-names = "engine", "pixel", "pll"; 2623 status = "disabled"; 2624 }; 2625 2626 edp_tx: edp-tx@1c500000 { 2627 compatible = "mediatek,mt8195-edp-tx"; 2628 reg = <0 0x1c500000 0 0x8000>; 2629 nvmem-cells = <&dp_calibration>; 2630 nvmem-cell-names = "dp_calibration_data"; 2631 power-domains = <&spm MT8195_POWER_DOMAIN_EPD_TX>; 2632 interrupts = <GIC_SPI 676 IRQ_TYPE_LEVEL_HIGH 0>; 2633 max-linkrate-mhz = <8100>; 2634 status = "disabled"; 2635 }; 2636 2637 dp_tx: dp-tx@1c600000 { 2638 compatible = "mediatek,mt8195-dp-tx"; 2639 reg = <0 0x1c600000 0 0x8000>; 2640 nvmem-cells = <&dp_calibration>; 2641 nvmem-cell-names = "dp_calibration_data"; 2642 power-domains = <&spm MT8195_POWER_DOMAIN_DP_TX>; 2643 interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH 0>; 2644 max-linkrate-mhz = <8100>; 2645 status = "disabled"; 2646 }; 2647 }; 2648}; 2649