mt8195.dtsi (a93f071a753a2f3fb7ff0acff588ade7679c92aa) mt8195.dtsi (e39e72cffea3288d3b1f27e0e05ce6c2d18b8735)
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (c) 2021 MediaTek Inc.
4 * Author: Seiya Wang <seiya.wang@mediatek.com>
5 */
6
7/dts-v1/;
8#include <dt-bindings/clock/mt8195-clk.h>

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21 #address-cells = <1>;
22 #size-cells = <0>;
23
24 cpu0: cpu@0 {
25 device_type = "cpu";
26 compatible = "arm,cortex-a55";
27 reg = <0x000>;
28 enable-method = "psci";
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (c) 2021 MediaTek Inc.
4 * Author: Seiya Wang <seiya.wang@mediatek.com>
5 */
6
7/dts-v1/;
8#include <dt-bindings/clock/mt8195-clk.h>

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21 #address-cells = <1>;
22 #size-cells = <0>;
23
24 cpu0: cpu@0 {
25 device_type = "cpu";
26 compatible = "arm,cortex-a55";
27 reg = <0x000>;
28 enable-method = "psci";
29 performance-domains = <&performance 0>;
29 clock-frequency = <1701000000>;
30 capacity-dmips-mhz = <578>;
31 cpu-idle-states = <&cpu_off_l &cluster_off_l>;
32 next-level-cache = <&l2_0>;
33 #cooling-cells = <2>;
34 };
35
36 cpu1: cpu@100 {
37 device_type = "cpu";
38 compatible = "arm,cortex-a55";
39 reg = <0x100>;
40 enable-method = "psci";
30 clock-frequency = <1701000000>;
31 capacity-dmips-mhz = <578>;
32 cpu-idle-states = <&cpu_off_l &cluster_off_l>;
33 next-level-cache = <&l2_0>;
34 #cooling-cells = <2>;
35 };
36
37 cpu1: cpu@100 {
38 device_type = "cpu";
39 compatible = "arm,cortex-a55";
40 reg = <0x100>;
41 enable-method = "psci";
42 performance-domains = <&performance 0>;
41 clock-frequency = <1701000000>;
42 capacity-dmips-mhz = <578>;
43 cpu-idle-states = <&cpu_off_l &cluster_off_l>;
44 next-level-cache = <&l2_0>;
45 #cooling-cells = <2>;
46 };
47
48 cpu2: cpu@200 {
49 device_type = "cpu";
50 compatible = "arm,cortex-a55";
51 reg = <0x200>;
52 enable-method = "psci";
43 clock-frequency = <1701000000>;
44 capacity-dmips-mhz = <578>;
45 cpu-idle-states = <&cpu_off_l &cluster_off_l>;
46 next-level-cache = <&l2_0>;
47 #cooling-cells = <2>;
48 };
49
50 cpu2: cpu@200 {
51 device_type = "cpu";
52 compatible = "arm,cortex-a55";
53 reg = <0x200>;
54 enable-method = "psci";
55 performance-domains = <&performance 0>;
53 clock-frequency = <1701000000>;
54 capacity-dmips-mhz = <578>;
55 cpu-idle-states = <&cpu_off_l &cluster_off_l>;
56 next-level-cache = <&l2_0>;
57 #cooling-cells = <2>;
58 };
59
60 cpu3: cpu@300 {
61 device_type = "cpu";
62 compatible = "arm,cortex-a55";
63 reg = <0x300>;
64 enable-method = "psci";
56 clock-frequency = <1701000000>;
57 capacity-dmips-mhz = <578>;
58 cpu-idle-states = <&cpu_off_l &cluster_off_l>;
59 next-level-cache = <&l2_0>;
60 #cooling-cells = <2>;
61 };
62
63 cpu3: cpu@300 {
64 device_type = "cpu";
65 compatible = "arm,cortex-a55";
66 reg = <0x300>;
67 enable-method = "psci";
68 performance-domains = <&performance 0>;
65 clock-frequency = <1701000000>;
66 capacity-dmips-mhz = <578>;
67 cpu-idle-states = <&cpu_off_l &cluster_off_l>;
68 next-level-cache = <&l2_0>;
69 #cooling-cells = <2>;
70 };
71
72 cpu4: cpu@400 {
73 device_type = "cpu";
74 compatible = "arm,cortex-a78";
75 reg = <0x400>;
76 enable-method = "psci";
69 clock-frequency = <1701000000>;
70 capacity-dmips-mhz = <578>;
71 cpu-idle-states = <&cpu_off_l &cluster_off_l>;
72 next-level-cache = <&l2_0>;
73 #cooling-cells = <2>;
74 };
75
76 cpu4: cpu@400 {
77 device_type = "cpu";
78 compatible = "arm,cortex-a78";
79 reg = <0x400>;
80 enable-method = "psci";
81 performance-domains = <&performance 1>;
77 clock-frequency = <2171000000>;
78 capacity-dmips-mhz = <1024>;
79 cpu-idle-states = <&cpu_off_b &cluster_off_b>;
80 next-level-cache = <&l2_1>;
81 #cooling-cells = <2>;
82 };
83
84 cpu5: cpu@500 {
85 device_type = "cpu";
86 compatible = "arm,cortex-a78";
87 reg = <0x500>;
88 enable-method = "psci";
82 clock-frequency = <2171000000>;
83 capacity-dmips-mhz = <1024>;
84 cpu-idle-states = <&cpu_off_b &cluster_off_b>;
85 next-level-cache = <&l2_1>;
86 #cooling-cells = <2>;
87 };
88
89 cpu5: cpu@500 {
90 device_type = "cpu";
91 compatible = "arm,cortex-a78";
92 reg = <0x500>;
93 enable-method = "psci";
94 performance-domains = <&performance 1>;
89 clock-frequency = <2171000000>;
90 capacity-dmips-mhz = <1024>;
91 cpu-idle-states = <&cpu_off_b &cluster_off_b>;
92 next-level-cache = <&l2_1>;
93 #cooling-cells = <2>;
94 };
95
96 cpu6: cpu@600 {
97 device_type = "cpu";
98 compatible = "arm,cortex-a78";
99 reg = <0x600>;
100 enable-method = "psci";
95 clock-frequency = <2171000000>;
96 capacity-dmips-mhz = <1024>;
97 cpu-idle-states = <&cpu_off_b &cluster_off_b>;
98 next-level-cache = <&l2_1>;
99 #cooling-cells = <2>;
100 };
101
102 cpu6: cpu@600 {
103 device_type = "cpu";
104 compatible = "arm,cortex-a78";
105 reg = <0x600>;
106 enable-method = "psci";
107 performance-domains = <&performance 1>;
101 clock-frequency = <2171000000>;
102 capacity-dmips-mhz = <1024>;
103 cpu-idle-states = <&cpu_off_b &cluster_off_b>;
104 next-level-cache = <&l2_1>;
105 #cooling-cells = <2>;
106 };
107
108 cpu7: cpu@700 {
109 device_type = "cpu";
110 compatible = "arm,cortex-a78";
111 reg = <0x700>;
112 enable-method = "psci";
108 clock-frequency = <2171000000>;
109 capacity-dmips-mhz = <1024>;
110 cpu-idle-states = <&cpu_off_b &cluster_off_b>;
111 next-level-cache = <&l2_1>;
112 #cooling-cells = <2>;
113 };
114
115 cpu7: cpu@700 {
116 device_type = "cpu";
117 compatible = "arm,cortex-a78";
118 reg = <0x700>;
119 enable-method = "psci";
120 performance-domains = <&performance 1>;
113 clock-frequency = <2171000000>;
114 capacity-dmips-mhz = <1024>;
115 cpu-idle-states = <&cpu_off_b &cluster_off_b>;
116 next-level-cache = <&l2_1>;
117 #cooling-cells = <2>;
118 };
119
120 cpu-map {

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226
227 clk32k: oscillator-32k {
228 compatible = "fixed-clock";
229 #clock-cells = <0>;
230 clock-frequency = <32768>;
231 clock-output-names = "clk32k";
232 };
233
121 clock-frequency = <2171000000>;
122 capacity-dmips-mhz = <1024>;
123 cpu-idle-states = <&cpu_off_b &cluster_off_b>;
124 next-level-cache = <&l2_1>;
125 #cooling-cells = <2>;
126 };
127
128 cpu-map {

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234
235 clk32k: oscillator-32k {
236 compatible = "fixed-clock";
237 #clock-cells = <0>;
238 clock-frequency = <32768>;
239 clock-output-names = "clk32k";
240 };
241
242 performance: performance-controller@11bc10 {
243 compatible = "mediatek,cpufreq-hw";
244 reg = <0 0x0011bc10 0 0x120>, <0 0x0011bd30 0 0x120>;
245 #performance-domain-cells = <1>;
246 };
247
234 pmu-a55 {
235 compatible = "arm,cortex-a55-pmu";
236 interrupt-parent = <&gic>;
237 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>;
238 };
239
240 pmu-a78 {
241 compatible = "arm,cortex-a78-pmu";

--- 857 unchanged lines hidden --- 		248 pmu-a55 {
249 compatible = "arm,cortex-a55-pmu";
250 interrupt-parent = <&gic>;
251 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>;
252 };
253
254 pmu-a78 {
255 compatible = "arm,cortex-a78-pmu";

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