1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (c) 2021 MediaTek Inc. 4 * Author: Seiya Wang <seiya.wang@mediatek.com> 5 */ 6 7/dts-v1/; 8#include <dt-bindings/clock/mt8195-clk.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/phy/phy.h> 12#include <dt-bindings/pinctrl/mt8195-pinfunc.h> 13 14/ { 15 compatible = "mediatek,mt8195"; 16 interrupt-parent = <&gic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 cpus { 21 #address-cells = <1>; 22 #size-cells = <0>; 23 24 cpu0: cpu@0 { 25 device_type = "cpu"; 26 compatible = "arm,cortex-a55"; 27 reg = <0x000>; 28 enable-method = "psci"; 29 clock-frequency = <1701000000>; 30 capacity-dmips-mhz = <578>; 31 cpu-idle-states = <&cpu_off_l &cluster_off_l>; 32 next-level-cache = <&l2_0>; 33 #cooling-cells = <2>; 34 }; 35 36 cpu1: cpu@100 { 37 device_type = "cpu"; 38 compatible = "arm,cortex-a55"; 39 reg = <0x100>; 40 enable-method = "psci"; 41 clock-frequency = <1701000000>; 42 capacity-dmips-mhz = <578>; 43 cpu-idle-states = <&cpu_off_l &cluster_off_l>; 44 next-level-cache = <&l2_0>; 45 #cooling-cells = <2>; 46 }; 47 48 cpu2: cpu@200 { 49 device_type = "cpu"; 50 compatible = "arm,cortex-a55"; 51 reg = <0x200>; 52 enable-method = "psci"; 53 clock-frequency = <1701000000>; 54 capacity-dmips-mhz = <578>; 55 cpu-idle-states = <&cpu_off_l &cluster_off_l>; 56 next-level-cache = <&l2_0>; 57 #cooling-cells = <2>; 58 }; 59 60 cpu3: cpu@300 { 61 device_type = "cpu"; 62 compatible = "arm,cortex-a55"; 63 reg = <0x300>; 64 enable-method = "psci"; 65 clock-frequency = <1701000000>; 66 capacity-dmips-mhz = <578>; 67 cpu-idle-states = <&cpu_off_l &cluster_off_l>; 68 next-level-cache = <&l2_0>; 69 #cooling-cells = <2>; 70 }; 71 72 cpu4: cpu@400 { 73 device_type = "cpu"; 74 compatible = "arm,cortex-a78"; 75 reg = <0x400>; 76 enable-method = "psci"; 77 clock-frequency = <2171000000>; 78 capacity-dmips-mhz = <1024>; 79 cpu-idle-states = <&cpu_off_b &cluster_off_b>; 80 next-level-cache = <&l2_1>; 81 #cooling-cells = <2>; 82 }; 83 84 cpu5: cpu@500 { 85 device_type = "cpu"; 86 compatible = "arm,cortex-a78"; 87 reg = <0x500>; 88 enable-method = "psci"; 89 clock-frequency = <2171000000>; 90 capacity-dmips-mhz = <1024>; 91 cpu-idle-states = <&cpu_off_b &cluster_off_b>; 92 next-level-cache = <&l2_1>; 93 #cooling-cells = <2>; 94 }; 95 96 cpu6: cpu@600 { 97 device_type = "cpu"; 98 compatible = "arm,cortex-a78"; 99 reg = <0x600>; 100 enable-method = "psci"; 101 clock-frequency = <2171000000>; 102 capacity-dmips-mhz = <1024>; 103 cpu-idle-states = <&cpu_off_b &cluster_off_b>; 104 next-level-cache = <&l2_1>; 105 #cooling-cells = <2>; 106 }; 107 108 cpu7: cpu@700 { 109 device_type = "cpu"; 110 compatible = "arm,cortex-a78"; 111 reg = <0x700>; 112 enable-method = "psci"; 113 clock-frequency = <2171000000>; 114 capacity-dmips-mhz = <1024>; 115 cpu-idle-states = <&cpu_off_b &cluster_off_b>; 116 next-level-cache = <&l2_1>; 117 #cooling-cells = <2>; 118 }; 119 120 cpu-map { 121 cluster0 { 122 core0 { 123 cpu = <&cpu0>; 124 }; 125 126 core1 { 127 cpu = <&cpu1>; 128 }; 129 130 core2 { 131 cpu = <&cpu2>; 132 }; 133 134 core3 { 135 cpu = <&cpu3>; 136 }; 137 }; 138 139 cluster1 { 140 core0 { 141 cpu = <&cpu4>; 142 }; 143 144 core1 { 145 cpu = <&cpu5>; 146 }; 147 148 core2 { 149 cpu = <&cpu6>; 150 }; 151 152 core3 { 153 cpu = <&cpu7>; 154 }; 155 }; 156 }; 157 158 idle-states { 159 entry-method = "psci"; 160 161 cpu_off_l: cpu-off-l { 162 compatible = "arm,idle-state"; 163 arm,psci-suspend-param = <0x00010001>; 164 local-timer-stop; 165 entry-latency-us = <50>; 166 exit-latency-us = <95>; 167 min-residency-us = <580>; 168 }; 169 170 cpu_off_b: cpu-off-b { 171 compatible = "arm,idle-state"; 172 arm,psci-suspend-param = <0x00010001>; 173 local-timer-stop; 174 entry-latency-us = <45>; 175 exit-latency-us = <140>; 176 min-residency-us = <740>; 177 }; 178 179 cluster_off_l: cluster-off-l { 180 compatible = "arm,idle-state"; 181 arm,psci-suspend-param = <0x01010002>; 182 local-timer-stop; 183 entry-latency-us = <55>; 184 exit-latency-us = <155>; 185 min-residency-us = <840>; 186 }; 187 188 cluster_off_b: cluster-off-b { 189 compatible = "arm,idle-state"; 190 arm,psci-suspend-param = <0x01010002>; 191 local-timer-stop; 192 entry-latency-us = <50>; 193 exit-latency-us = <200>; 194 min-residency-us = <1000>; 195 }; 196 }; 197 198 l2_0: l2-cache0 { 199 compatible = "cache"; 200 next-level-cache = <&l3_0>; 201 }; 202 203 l2_1: l2-cache1 { 204 compatible = "cache"; 205 next-level-cache = <&l3_0>; 206 }; 207 208 l3_0: l3-cache { 209 compatible = "cache"; 210 }; 211 }; 212 213 dsu-pmu { 214 compatible = "arm,dsu-pmu"; 215 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>; 216 cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>, 217 <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>; 218 }; 219 220 clk26m: oscillator-26m { 221 compatible = "fixed-clock"; 222 #clock-cells = <0>; 223 clock-frequency = <26000000>; 224 clock-output-names = "clk26m"; 225 }; 226 227 clk32k: oscillator-32k { 228 compatible = "fixed-clock"; 229 #clock-cells = <0>; 230 clock-frequency = <32768>; 231 clock-output-names = "clk32k"; 232 }; 233 234 pmu-a55 { 235 compatible = "arm,cortex-a55-pmu"; 236 interrupt-parent = <&gic>; 237 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>; 238 }; 239 240 pmu-a78 { 241 compatible = "arm,cortex-a78-pmu"; 242 interrupt-parent = <&gic>; 243 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>; 244 }; 245 246 psci { 247 compatible = "arm,psci-1.0"; 248 method = "smc"; 249 }; 250 251 timer: timer { 252 compatible = "arm,armv8-timer"; 253 interrupt-parent = <&gic>; 254 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>, 255 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>, 256 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>, 257 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>; 258 }; 259 260 soc { 261 #address-cells = <2>; 262 #size-cells = <2>; 263 compatible = "simple-bus"; 264 ranges; 265 266 gic: interrupt-controller@c000000 { 267 compatible = "arm,gic-v3"; 268 #interrupt-cells = <4>; 269 #redistributor-regions = <1>; 270 interrupt-parent = <&gic>; 271 interrupt-controller; 272 reg = <0 0x0c000000 0 0x40000>, 273 <0 0x0c040000 0 0x200000>; 274 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 275 276 ppi-partitions { 277 ppi_cluster0: interrupt-partition-0 { 278 affinity = <&cpu0 &cpu1 &cpu2 &cpu3>; 279 }; 280 281 ppi_cluster1: interrupt-partition-1 { 282 affinity = <&cpu4 &cpu5 &cpu6 &cpu7>; 283 }; 284 }; 285 }; 286 287 topckgen: syscon@10000000 { 288 compatible = "mediatek,mt8195-topckgen", "syscon"; 289 reg = <0 0x10000000 0 0x1000>; 290 #clock-cells = <1>; 291 }; 292 293 infracfg_ao: syscon@10001000 { 294 compatible = "mediatek,mt8195-infracfg_ao", "syscon", "simple-mfd"; 295 reg = <0 0x10001000 0 0x1000>; 296 #clock-cells = <1>; 297 #reset-cells = <1>; 298 }; 299 300 pericfg: syscon@10003000 { 301 compatible = "mediatek,mt8195-pericfg", "syscon"; 302 reg = <0 0x10003000 0 0x1000>; 303 #clock-cells = <1>; 304 }; 305 306 pio: pinctrl@10005000 { 307 compatible = "mediatek,mt8195-pinctrl"; 308 reg = <0 0x10005000 0 0x1000>, 309 <0 0x11d10000 0 0x1000>, 310 <0 0x11d30000 0 0x1000>, 311 <0 0x11d40000 0 0x1000>, 312 <0 0x11e20000 0 0x1000>, 313 <0 0x11eb0000 0 0x1000>, 314 <0 0x11f40000 0 0x1000>, 315 <0 0x1000b000 0 0x1000>; 316 reg-names = "iocfg0", "iocfg_bm", "iocfg_bl", 317 "iocfg_br", "iocfg_lm", "iocfg_rb", 318 "iocfg_tl", "eint"; 319 gpio-controller; 320 #gpio-cells = <2>; 321 gpio-ranges = <&pio 0 0 144>; 322 interrupt-controller; 323 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH 0>; 324 #interrupt-cells = <2>; 325 }; 326 327 watchdog: watchdog@10007000 { 328 compatible = "mediatek,mt8195-wdt", 329 "mediatek,mt6589-wdt"; 330 mediatek,disable-extrst; 331 reg = <0 0x10007000 0 0x100>; 332 }; 333 334 apmixedsys: syscon@1000c000 { 335 compatible = "mediatek,mt8195-apmixedsys", "syscon"; 336 reg = <0 0x1000c000 0 0x1000>; 337 #clock-cells = <1>; 338 }; 339 340 systimer: timer@10017000 { 341 compatible = "mediatek,mt8195-timer", 342 "mediatek,mt6765-timer"; 343 reg = <0 0x10017000 0 0x1000>; 344 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>; 345 clocks = <&topckgen CLK_TOP_CLK26M_D2>; 346 }; 347 348 pwrap: pwrap@10024000 { 349 compatible = "mediatek,mt8195-pwrap", "syscon"; 350 reg = <0 0x10024000 0 0x1000>; 351 reg-names = "pwrap"; 352 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH 0>; 353 clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>, 354 <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>; 355 clock-names = "spi", "wrap"; 356 assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC>; 357 assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>; 358 }; 359 360 scp_adsp: clock-controller@10720000 { 361 compatible = "mediatek,mt8195-scp_adsp"; 362 reg = <0 0x10720000 0 0x1000>; 363 #clock-cells = <1>; 364 }; 365 366 uart0: serial@11001100 { 367 compatible = "mediatek,mt8195-uart", 368 "mediatek,mt6577-uart"; 369 reg = <0 0x11001100 0 0x100>; 370 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH 0>; 371 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART0>; 372 clock-names = "baud", "bus"; 373 status = "disabled"; 374 }; 375 376 uart1: serial@11001200 { 377 compatible = "mediatek,mt8195-uart", 378 "mediatek,mt6577-uart"; 379 reg = <0 0x11001200 0 0x100>; 380 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH 0>; 381 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART1>; 382 clock-names = "baud", "bus"; 383 status = "disabled"; 384 }; 385 386 uart2: serial@11001300 { 387 compatible = "mediatek,mt8195-uart", 388 "mediatek,mt6577-uart"; 389 reg = <0 0x11001300 0 0x100>; 390 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH 0>; 391 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART2>; 392 clock-names = "baud", "bus"; 393 status = "disabled"; 394 }; 395 396 uart3: serial@11001400 { 397 compatible = "mediatek,mt8195-uart", 398 "mediatek,mt6577-uart"; 399 reg = <0 0x11001400 0 0x100>; 400 interrupts = <GIC_SPI 723 IRQ_TYPE_LEVEL_HIGH 0>; 401 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART3>; 402 clock-names = "baud", "bus"; 403 status = "disabled"; 404 }; 405 406 uart4: serial@11001500 { 407 compatible = "mediatek,mt8195-uart", 408 "mediatek,mt6577-uart"; 409 reg = <0 0x11001500 0 0x100>; 410 interrupts = <GIC_SPI 724 IRQ_TYPE_LEVEL_HIGH 0>; 411 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART4>; 412 clock-names = "baud", "bus"; 413 status = "disabled"; 414 }; 415 416 uart5: serial@11001600 { 417 compatible = "mediatek,mt8195-uart", 418 "mediatek,mt6577-uart"; 419 reg = <0 0x11001600 0 0x100>; 420 interrupts = <GIC_SPI 725 IRQ_TYPE_LEVEL_HIGH 0>; 421 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART5>; 422 clock-names = "baud", "bus"; 423 status = "disabled"; 424 }; 425 426 auxadc: auxadc@11002000 { 427 compatible = "mediatek,mt8195-auxadc", 428 "mediatek,mt8173-auxadc"; 429 reg = <0 0x11002000 0 0x1000>; 430 clocks = <&infracfg_ao CLK_INFRA_AO_AUXADC>; 431 clock-names = "main"; 432 #io-channel-cells = <1>; 433 status = "disabled"; 434 }; 435 436 pericfg_ao: syscon@11003000 { 437 compatible = "mediatek,mt8195-pericfg_ao", "syscon"; 438 reg = <0 0x11003000 0 0x1000>; 439 #clock-cells = <1>; 440 }; 441 442 spi0: spi@1100a000 { 443 compatible = "mediatek,mt8195-spi", 444 "mediatek,mt6765-spi"; 445 #address-cells = <1>; 446 #size-cells = <0>; 447 reg = <0 0x1100a000 0 0x1000>; 448 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH 0>; 449 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 450 <&topckgen CLK_TOP_SPI>, 451 <&infracfg_ao CLK_INFRA_AO_SPI0>; 452 clock-names = "parent-clk", "sel-clk", "spi-clk"; 453 status = "disabled"; 454 }; 455 456 spi1: spi@11010000 { 457 compatible = "mediatek,mt8195-spi", 458 "mediatek,mt6765-spi"; 459 #address-cells = <1>; 460 #size-cells = <0>; 461 reg = <0 0x11010000 0 0x1000>; 462 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH 0>; 463 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 464 <&topckgen CLK_TOP_SPI>, 465 <&infracfg_ao CLK_INFRA_AO_SPI1>; 466 clock-names = "parent-clk", "sel-clk", "spi-clk"; 467 status = "disabled"; 468 }; 469 470 spi2: spi@11012000 { 471 compatible = "mediatek,mt8195-spi", 472 "mediatek,mt6765-spi"; 473 #address-cells = <1>; 474 #size-cells = <0>; 475 reg = <0 0x11012000 0 0x1000>; 476 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH 0>; 477 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 478 <&topckgen CLK_TOP_SPI>, 479 <&infracfg_ao CLK_INFRA_AO_SPI2>; 480 clock-names = "parent-clk", "sel-clk", "spi-clk"; 481 status = "disabled"; 482 }; 483 484 spi3: spi@11013000 { 485 compatible = "mediatek,mt8195-spi", 486 "mediatek,mt6765-spi"; 487 #address-cells = <1>; 488 #size-cells = <0>; 489 reg = <0 0x11013000 0 0x1000>; 490 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH 0>; 491 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 492 <&topckgen CLK_TOP_SPI>, 493 <&infracfg_ao CLK_INFRA_AO_SPI3>; 494 clock-names = "parent-clk", "sel-clk", "spi-clk"; 495 status = "disabled"; 496 }; 497 498 spi4: spi@11018000 { 499 compatible = "mediatek,mt8195-spi", 500 "mediatek,mt6765-spi"; 501 #address-cells = <1>; 502 #size-cells = <0>; 503 reg = <0 0x11018000 0 0x1000>; 504 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH 0>; 505 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 506 <&topckgen CLK_TOP_SPI>, 507 <&infracfg_ao CLK_INFRA_AO_SPI4>; 508 clock-names = "parent-clk", "sel-clk", "spi-clk"; 509 status = "disabled"; 510 }; 511 512 spi5: spi@11019000 { 513 compatible = "mediatek,mt8195-spi", 514 "mediatek,mt6765-spi"; 515 #address-cells = <1>; 516 #size-cells = <0>; 517 reg = <0 0x11019000 0 0x1000>; 518 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH 0>; 519 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 520 <&topckgen CLK_TOP_SPI>, 521 <&infracfg_ao CLK_INFRA_AO_SPI5>; 522 clock-names = "parent-clk", "sel-clk", "spi-clk"; 523 status = "disabled"; 524 }; 525 526 spis0: spi@1101d000 { 527 compatible = "mediatek,mt8195-spi-slave"; 528 reg = <0 0x1101d000 0 0x1000>; 529 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH 0>; 530 clocks = <&infracfg_ao CLK_INFRA_AO_SPIS0>; 531 clock-names = "spi"; 532 assigned-clocks = <&topckgen CLK_TOP_SPIS>; 533 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>; 534 status = "disabled"; 535 }; 536 537 spis1: spi@1101e000 { 538 compatible = "mediatek,mt8195-spi-slave"; 539 reg = <0 0x1101e000 0 0x1000>; 540 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH 0>; 541 clocks = <&infracfg_ao CLK_INFRA_AO_SPIS1>; 542 clock-names = "spi"; 543 assigned-clocks = <&topckgen CLK_TOP_SPIS>; 544 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>; 545 status = "disabled"; 546 }; 547 548 xhci0: usb@11200000 { 549 compatible = "mediatek,mt8195-xhci", 550 "mediatek,mtk-xhci"; 551 reg = <0 0x11200000 0 0x1000>, 552 <0 0x11203e00 0 0x0100>; 553 reg-names = "mac", "ippc"; 554 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH 0>; 555 phys = <&u2port0 PHY_TYPE_USB2>, 556 <&u3port0 PHY_TYPE_USB3>; 557 assigned-clocks = <&topckgen CLK_TOP_USB_TOP>, 558 <&topckgen CLK_TOP_SSUSB_XHCI>; 559 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, 560 <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 561 clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB>, 562 <&topckgen CLK_TOP_SSUSB_REF>, 563 <&apmixedsys CLK_APMIXED_USB1PLL>, 564 <&infracfg_ao CLK_INFRA_AO_SSUSB_XHCI>; 565 clock-names = "sys_ck", "ref_ck", "mcu_ck", "xhci_ck"; 566 mediatek,syscon-wakeup = <&pericfg 0x400 103>; 567 wakeup-source; 568 status = "disabled"; 569 }; 570 571 mmc0: mmc@11230000 { 572 compatible = "mediatek,mt8195-mmc", 573 "mediatek,mt8183-mmc"; 574 reg = <0 0x11230000 0 0x10000>, 575 <0 0x11f50000 0 0x1000>; 576 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>; 577 clocks = <&topckgen CLK_TOP_MSDC50_0>, 578 <&infracfg_ao CLK_INFRA_AO_MSDC0>, 579 <&infracfg_ao CLK_INFRA_AO_MSDC0_SRC>; 580 clock-names = "source", "hclk", "source_cg"; 581 status = "disabled"; 582 }; 583 584 mmc1: mmc@11240000 { 585 compatible = "mediatek,mt8195-mmc", 586 "mediatek,mt8183-mmc"; 587 reg = <0 0x11240000 0 0x1000>, 588 <0 0x11c70000 0 0x1000>; 589 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH 0>; 590 clocks = <&topckgen CLK_TOP_MSDC30_1>, 591 <&infracfg_ao CLK_INFRA_AO_MSDC1>, 592 <&infracfg_ao CLK_INFRA_AO_MSDC1_SRC>; 593 clock-names = "source", "hclk", "source_cg"; 594 assigned-clocks = <&topckgen CLK_TOP_MSDC30_1>; 595 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>; 596 status = "disabled"; 597 }; 598 599 mmc2: mmc@11250000 { 600 compatible = "mediatek,mt8195-mmc", 601 "mediatek,mt8183-mmc"; 602 reg = <0 0x11250000 0 0x1000>, 603 <0 0x11e60000 0 0x1000>; 604 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH 0>; 605 clocks = <&topckgen CLK_TOP_MSDC30_2>, 606 <&infracfg_ao CLK_INFRA_AO_CG1_MSDC2>, 607 <&infracfg_ao CLK_INFRA_AO_CG3_MSDC2>; 608 clock-names = "source", "hclk", "source_cg"; 609 assigned-clocks = <&topckgen CLK_TOP_MSDC30_2>; 610 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>; 611 status = "disabled"; 612 }; 613 614 xhci1: usb@11290000 { 615 compatible = "mediatek,mt8195-xhci", 616 "mediatek,mtk-xhci"; 617 reg = <0 0x11290000 0 0x1000>, 618 <0 0x11293e00 0 0x0100>; 619 reg-names = "mac", "ippc"; 620 interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH 0>; 621 phys = <&u2port1 PHY_TYPE_USB2>; 622 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_1P>, 623 <&topckgen CLK_TOP_SSUSB_XHCI_1P>; 624 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, 625 <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 626 clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_1P_BUS>, 627 <&topckgen CLK_TOP_SSUSB_P1_REF>, 628 <&apmixedsys CLK_APMIXED_USB1PLL>, 629 <&pericfg_ao CLK_PERI_AO_SSUSB_1P_XHCI>; 630 clock-names = "sys_ck", "ref_ck", "mcu_ck","xhci_ck"; 631 mediatek,syscon-wakeup = <&pericfg 0x400 104>; 632 wakeup-source; 633 status = "disabled"; 634 }; 635 636 xhci2: usb@112a0000 { 637 compatible = "mediatek,mt8195-xhci", 638 "mediatek,mtk-xhci"; 639 reg = <0 0x112a0000 0 0x1000>, 640 <0 0x112a3e00 0 0x0100>; 641 reg-names = "mac", "ippc"; 642 interrupts = <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH 0>; 643 phys = <&u2port2 PHY_TYPE_USB2>; 644 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_2P>, 645 <&topckgen CLK_TOP_SSUSB_XHCI_2P>; 646 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, 647 <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 648 clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_2P_BUS>, 649 <&topckgen CLK_TOP_SSUSB_P2_REF>, 650 <&pericfg_ao CLK_PERI_AO_SSUSB_2P_XHCI>; 651 clock-names = "sys_ck", "ref_ck", "xhci_ck"; 652 mediatek,syscon-wakeup = <&pericfg 0x400 105>; 653 wakeup-source; 654 status = "disabled"; 655 }; 656 657 xhci3: usb@112b0000 { 658 compatible = "mediatek,mt8195-xhci", 659 "mediatek,mtk-xhci"; 660 reg = <0 0x112b0000 0 0x1000>, 661 <0 0x112b3e00 0 0x0100>; 662 reg-names = "mac", "ippc"; 663 interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH 0>; 664 phys = <&u2port3 PHY_TYPE_USB2>; 665 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_3P>, 666 <&topckgen CLK_TOP_SSUSB_XHCI_3P>; 667 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, 668 <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 669 clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_3P_BUS>, 670 <&topckgen CLK_TOP_SSUSB_P3_REF>, 671 <&pericfg_ao CLK_PERI_AO_SSUSB_3P_XHCI>; 672 clock-names = "sys_ck", "ref_ck", "xhci_ck"; 673 mediatek,syscon-wakeup = <&pericfg 0x400 106>; 674 wakeup-source; 675 status = "disabled"; 676 }; 677 678 nor_flash: spi@1132c000 { 679 compatible = "mediatek,mt8195-nor", 680 "mediatek,mt8173-nor"; 681 reg = <0 0x1132c000 0 0x1000>; 682 interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH 0>; 683 clocks = <&topckgen CLK_TOP_SPINOR>, 684 <&pericfg_ao CLK_PERI_AO_FLASHIF_FLASH>, 685 <&pericfg_ao CLK_PERI_AO_FLASHIF_BUS>; 686 clock-names = "spi", "sf", "axi"; 687 #address-cells = <1>; 688 #size-cells = <0>; 689 status = "disabled"; 690 }; 691 692 efuse: efuse@11c10000 { 693 compatible = "mediatek,mt8195-efuse", "mediatek,efuse"; 694 reg = <0 0x11c10000 0 0x1000>; 695 #address-cells = <1>; 696 #size-cells = <1>; 697 u3_tx_imp_p0: usb3-tx-imp@184,1 { 698 reg = <0x184 0x1>; 699 bits = <0 5>; 700 }; 701 u3_rx_imp_p0: usb3-rx-imp@184,2 { 702 reg = <0x184 0x2>; 703 bits = <5 5>; 704 }; 705 u3_intr_p0: usb3-intr@185 { 706 reg = <0x185 0x1>; 707 bits = <2 6>; 708 }; 709 comb_tx_imp_p1: usb3-tx-imp@186,1 { 710 reg = <0x186 0x1>; 711 bits = <0 5>; 712 }; 713 comb_rx_imp_p1: usb3-rx-imp@186,2 { 714 reg = <0x186 0x2>; 715 bits = <5 5>; 716 }; 717 comb_intr_p1: usb3-intr@187 { 718 reg = <0x187 0x1>; 719 bits = <2 6>; 720 }; 721 u2_intr_p0: usb2-intr-p0@188,1 { 722 reg = <0x188 0x1>; 723 bits = <0 5>; 724 }; 725 u2_intr_p1: usb2-intr-p1@188,2 { 726 reg = <0x188 0x2>; 727 bits = <5 5>; 728 }; 729 u2_intr_p2: usb2-intr-p2@189,1 { 730 reg = <0x189 0x1>; 731 bits = <2 5>; 732 }; 733 u2_intr_p3: usb2-intr-p3@189,2 { 734 reg = <0x189 0x2>; 735 bits = <7 5>; 736 }; 737 }; 738 739 u3phy2: t-phy@11c40000 { 740 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3"; 741 #address-cells = <1>; 742 #size-cells = <1>; 743 ranges = <0 0 0x11c40000 0x700>; 744 status = "disabled"; 745 746 u2port2: usb-phy@0 { 747 reg = <0x0 0x700>; 748 clocks = <&topckgen CLK_TOP_SSUSB_PHY_P2_REF>; 749 clock-names = "ref"; 750 #phy-cells = <1>; 751 }; 752 }; 753 754 u3phy3: t-phy@11c50000 { 755 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3"; 756 #address-cells = <1>; 757 #size-cells = <1>; 758 ranges = <0 0 0x11c50000 0x700>; 759 status = "disabled"; 760 761 u2port3: usb-phy@0 { 762 reg = <0x0 0x700>; 763 clocks = <&topckgen CLK_TOP_SSUSB_PHY_P3_REF>; 764 clock-names = "ref"; 765 #phy-cells = <1>; 766 }; 767 }; 768 769 i2c5: i2c@11d00000 { 770 compatible = "mediatek,mt8195-i2c", 771 "mediatek,mt8192-i2c"; 772 reg = <0 0x11d00000 0 0x1000>, 773 <0 0x10220580 0 0x80>; 774 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH 0>; 775 clock-div = <1>; 776 clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C5>, 777 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 778 clock-names = "main", "dma"; 779 #address-cells = <1>; 780 #size-cells = <0>; 781 status = "disabled"; 782 }; 783 784 i2c6: i2c@11d01000 { 785 compatible = "mediatek,mt8195-i2c", 786 "mediatek,mt8192-i2c"; 787 reg = <0 0x11d01000 0 0x1000>, 788 <0 0x10220600 0 0x80>; 789 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH 0>; 790 clock-div = <1>; 791 clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C6>, 792 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 793 clock-names = "main", "dma"; 794 #address-cells = <1>; 795 #size-cells = <0>; 796 status = "disabled"; 797 }; 798 799 i2c7: i2c@11d02000 { 800 compatible = "mediatek,mt8195-i2c", 801 "mediatek,mt8192-i2c"; 802 reg = <0 0x11d02000 0 0x1000>, 803 <0 0x10220680 0 0x80>; 804 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>; 805 clock-div = <1>; 806 clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C7>, 807 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 808 clock-names = "main", "dma"; 809 #address-cells = <1>; 810 #size-cells = <0>; 811 status = "disabled"; 812 }; 813 814 imp_iic_wrap_s: clock-controller@11d03000 { 815 compatible = "mediatek,mt8195-imp_iic_wrap_s"; 816 reg = <0 0x11d03000 0 0x1000>; 817 #clock-cells = <1>; 818 }; 819 820 i2c0: i2c@11e00000 { 821 compatible = "mediatek,mt8195-i2c", 822 "mediatek,mt8192-i2c"; 823 reg = <0 0x11e00000 0 0x1000>, 824 <0 0x10220080 0 0x80>; 825 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH 0>; 826 clock-div = <1>; 827 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C0>, 828 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 829 clock-names = "main", "dma"; 830 #address-cells = <1>; 831 #size-cells = <0>; 832 status = "disabled"; 833 }; 834 835 i2c1: i2c@11e01000 { 836 compatible = "mediatek,mt8195-i2c", 837 "mediatek,mt8192-i2c"; 838 reg = <0 0x11e01000 0 0x1000>, 839 <0 0x10220200 0 0x80>; 840 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH 0>; 841 clock-div = <1>; 842 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C1>, 843 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 844 clock-names = "main", "dma"; 845 #address-cells = <1>; 846 #size-cells = <0>; 847 status = "disabled"; 848 }; 849 850 i2c2: i2c@11e02000 { 851 compatible = "mediatek,mt8195-i2c", 852 "mediatek,mt8192-i2c"; 853 reg = <0 0x11e02000 0 0x1000>, 854 <0 0x10220380 0 0x80>; 855 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH 0>; 856 clock-div = <1>; 857 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C2>, 858 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 859 clock-names = "main", "dma"; 860 #address-cells = <1>; 861 #size-cells = <0>; 862 status = "disabled"; 863 }; 864 865 i2c3: i2c@11e03000 { 866 compatible = "mediatek,mt8195-i2c", 867 "mediatek,mt8192-i2c"; 868 reg = <0 0x11e03000 0 0x1000>, 869 <0 0x10220480 0 0x80>; 870 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH 0>; 871 clock-div = <1>; 872 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C3>, 873 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 874 clock-names = "main", "dma"; 875 #address-cells = <1>; 876 #size-cells = <0>; 877 status = "disabled"; 878 }; 879 880 i2c4: i2c@11e04000 { 881 compatible = "mediatek,mt8195-i2c", 882 "mediatek,mt8192-i2c"; 883 reg = <0 0x11e04000 0 0x1000>, 884 <0 0x10220500 0 0x80>; 885 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH 0>; 886 clock-div = <1>; 887 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C4>, 888 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 889 clock-names = "main", "dma"; 890 #address-cells = <1>; 891 #size-cells = <0>; 892 status = "disabled"; 893 }; 894 895 imp_iic_wrap_w: clock-controller@11e05000 { 896 compatible = "mediatek,mt8195-imp_iic_wrap_w"; 897 reg = <0 0x11e05000 0 0x1000>; 898 #clock-cells = <1>; 899 }; 900 901 u3phy1: t-phy@11e30000 { 902 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3"; 903 #address-cells = <1>; 904 #size-cells = <1>; 905 ranges = <0 0 0x11e30000 0xe00>; 906 status = "disabled"; 907 908 u2port1: usb-phy@0 { 909 reg = <0x0 0x700>; 910 clocks = <&topckgen CLK_TOP_SSUSB_PHY_P1_REF>, 911 <&clk26m>; 912 clock-names = "ref", "da_ref"; 913 #phy-cells = <1>; 914 }; 915 916 u3port1: usb-phy@700 { 917 reg = <0x700 0x700>; 918 clocks = <&apmixedsys CLK_APMIXED_PLL_SSUSB26M>, 919 <&topckgen CLK_TOP_SSUSB_PHY_P1_REF>; 920 clock-names = "ref", "da_ref"; 921 nvmem-cells = <&comb_intr_p1>, 922 <&comb_rx_imp_p1>, 923 <&comb_tx_imp_p1>; 924 nvmem-cell-names = "intr", "rx_imp", "tx_imp"; 925 #phy-cells = <1>; 926 }; 927 }; 928 929 u3phy0: t-phy@11e40000 { 930 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3"; 931 #address-cells = <1>; 932 #size-cells = <1>; 933 ranges = <0 0 0x11e40000 0xe00>; 934 status = "disabled"; 935 936 u2port0: usb-phy@0 { 937 reg = <0x0 0x700>; 938 clocks = <&topckgen CLK_TOP_SSUSB_PHY_REF>, 939 <&clk26m>; 940 clock-names = "ref", "da_ref"; 941 #phy-cells = <1>; 942 }; 943 944 u3port0: usb-phy@700 { 945 reg = <0x700 0x700>; 946 clocks = <&apmixedsys CLK_APMIXED_PLL_SSUSB26M>, 947 <&topckgen CLK_TOP_SSUSB_PHY_REF>; 948 clock-names = "ref", "da_ref"; 949 nvmem-cells = <&u3_intr_p0>, 950 <&u3_rx_imp_p0>, 951 <&u3_tx_imp_p0>; 952 nvmem-cell-names = "intr", "rx_imp", "tx_imp"; 953 #phy-cells = <1>; 954 }; 955 }; 956 957 ufsphy: ufs-phy@11fa0000 { 958 compatible = "mediatek,mt8195-ufsphy", "mediatek,mt8183-ufsphy"; 959 reg = <0 0x11fa0000 0 0xc000>; 960 clocks = <&clk26m>, <&clk26m>; 961 clock-names = "unipro", "mp"; 962 #phy-cells = <0>; 963 status = "disabled"; 964 }; 965 966 mfgcfg: clock-controller@13fbf000 { 967 compatible = "mediatek,mt8195-mfgcfg"; 968 reg = <0 0x13fbf000 0 0x1000>; 969 #clock-cells = <1>; 970 }; 971 972 wpesys: clock-controller@14e00000 { 973 compatible = "mediatek,mt8195-wpesys"; 974 reg = <0 0x14e00000 0 0x1000>; 975 #clock-cells = <1>; 976 }; 977 978 wpesys_vpp0: clock-controller@14e02000 { 979 compatible = "mediatek,mt8195-wpesys_vpp0"; 980 reg = <0 0x14e02000 0 0x1000>; 981 #clock-cells = <1>; 982 }; 983 984 wpesys_vpp1: clock-controller@14e03000 { 985 compatible = "mediatek,mt8195-wpesys_vpp1"; 986 reg = <0 0x14e03000 0 0x1000>; 987 #clock-cells = <1>; 988 }; 989 990 imgsys: clock-controller@15000000 { 991 compatible = "mediatek,mt8195-imgsys"; 992 reg = <0 0x15000000 0 0x1000>; 993 #clock-cells = <1>; 994 }; 995 996 imgsys1_dip_top: clock-controller@15110000 { 997 compatible = "mediatek,mt8195-imgsys1_dip_top"; 998 reg = <0 0x15110000 0 0x1000>; 999 #clock-cells = <1>; 1000 }; 1001 1002 imgsys1_dip_nr: clock-controller@15130000 { 1003 compatible = "mediatek,mt8195-imgsys1_dip_nr"; 1004 reg = <0 0x15130000 0 0x1000>; 1005 #clock-cells = <1>; 1006 }; 1007 1008 imgsys1_wpe: clock-controller@15220000 { 1009 compatible = "mediatek,mt8195-imgsys1_wpe"; 1010 reg = <0 0x15220000 0 0x1000>; 1011 #clock-cells = <1>; 1012 }; 1013 1014 ipesys: clock-controller@15330000 { 1015 compatible = "mediatek,mt8195-ipesys"; 1016 reg = <0 0x15330000 0 0x1000>; 1017 #clock-cells = <1>; 1018 }; 1019 1020 camsys: clock-controller@16000000 { 1021 compatible = "mediatek,mt8195-camsys"; 1022 reg = <0 0x16000000 0 0x1000>; 1023 #clock-cells = <1>; 1024 }; 1025 1026 camsys_rawa: clock-controller@1604f000 { 1027 compatible = "mediatek,mt8195-camsys_rawa"; 1028 reg = <0 0x1604f000 0 0x1000>; 1029 #clock-cells = <1>; 1030 }; 1031 1032 camsys_yuva: clock-controller@1606f000 { 1033 compatible = "mediatek,mt8195-camsys_yuva"; 1034 reg = <0 0x1606f000 0 0x1000>; 1035 #clock-cells = <1>; 1036 }; 1037 1038 camsys_rawb: clock-controller@1608f000 { 1039 compatible = "mediatek,mt8195-camsys_rawb"; 1040 reg = <0 0x1608f000 0 0x1000>; 1041 #clock-cells = <1>; 1042 }; 1043 1044 camsys_yuvb: clock-controller@160af000 { 1045 compatible = "mediatek,mt8195-camsys_yuvb"; 1046 reg = <0 0x160af000 0 0x1000>; 1047 #clock-cells = <1>; 1048 }; 1049 1050 camsys_mraw: clock-controller@16140000 { 1051 compatible = "mediatek,mt8195-camsys_mraw"; 1052 reg = <0 0x16140000 0 0x1000>; 1053 #clock-cells = <1>; 1054 }; 1055 1056 ccusys: clock-controller@17200000 { 1057 compatible = "mediatek,mt8195-ccusys"; 1058 reg = <0 0x17200000 0 0x1000>; 1059 #clock-cells = <1>; 1060 }; 1061 1062 vdecsys_soc: clock-controller@1800f000 { 1063 compatible = "mediatek,mt8195-vdecsys_soc"; 1064 reg = <0 0x1800f000 0 0x1000>; 1065 #clock-cells = <1>; 1066 }; 1067 1068 vdecsys: clock-controller@1802f000 { 1069 compatible = "mediatek,mt8195-vdecsys"; 1070 reg = <0 0x1802f000 0 0x1000>; 1071 #clock-cells = <1>; 1072 }; 1073 1074 vdecsys_core1: clock-controller@1803f000 { 1075 compatible = "mediatek,mt8195-vdecsys_core1"; 1076 reg = <0 0x1803f000 0 0x1000>; 1077 #clock-cells = <1>; 1078 }; 1079 1080 apusys_pll: clock-controller@190f3000 { 1081 compatible = "mediatek,mt8195-apusys_pll"; 1082 reg = <0 0x190f3000 0 0x1000>; 1083 #clock-cells = <1>; 1084 }; 1085 1086 vencsys: clock-controller@1a000000 { 1087 compatible = "mediatek,mt8195-vencsys"; 1088 reg = <0 0x1a000000 0 0x1000>; 1089 #clock-cells = <1>; 1090 }; 1091 1092 vencsys_core1: clock-controller@1b000000 { 1093 compatible = "mediatek,mt8195-vencsys_core1"; 1094 reg = <0 0x1b000000 0 0x1000>; 1095 #clock-cells = <1>; 1096 }; 1097 }; 1098}; 1099