mt8195.dtsi (a376a9a6491431587992e3d4319466d9adba1b58) mt8195.dtsi (a93f071a753a2f3fb7ff0acff588ade7679c92aa)
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (c) 2021 MediaTek Inc.
4 * Author: Seiya Wang <seiya.wang@mediatek.com>
5 */
6
7/dts-v1/;
8#include <dt-bindings/clock/mt8195-clk.h>

--- 815 unchanged lines hidden (view full) ---

824 <0 0x10220080 0 0x80>;
825 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH 0>;
826 clock-div = <1>;
827 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C0>,
828 <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
829 clock-names = "main", "dma";
830 #address-cells = <1>;
831 #size-cells = <0>;
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (c) 2021 MediaTek Inc.
4 * Author: Seiya Wang <seiya.wang@mediatek.com>
5 */
6
7/dts-v1/;
8#include <dt-bindings/clock/mt8195-clk.h>

--- 815 unchanged lines hidden (view full) ---

824 <0 0x10220080 0 0x80>;
825 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH 0>;
826 clock-div = <1>;
827 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C0>,
828 <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
829 clock-names = "main", "dma";
830 #address-cells = <1>;
831 #size-cells = <0>;
832 status = "okay";
832 status = "disabled";
833 };
834
835 i2c1: i2c@11e01000 {
836 compatible = "mediatek,mt8195-i2c",
837 "mediatek,mt8192-i2c";
838 reg = <0 0x11e01000 0 0x1000>,
839 <0 0x10220200 0 0x80>;
840 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH 0>;

--- 258 unchanged lines hidden --- 		833 };
834
835 i2c1: i2c@11e01000 {
836 compatible = "mediatek,mt8195-i2c",
837 "mediatek,mt8192-i2c";
838 reg = <0 0x11e01000 0 0x1000>,
839 <0 0x10220200 0 0x80>;
840 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH 0>;

--- 258 unchanged lines hidden ---