mt8195.dtsi (8903821c8ef9fe89ef20401f2261d2cfcdb0c386) mt8195.dtsi (7dd5bc578974a96025cb120012706bb4bf4e41fc)
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (c) 2021 MediaTek Inc.
4 * Author: Seiya Wang <seiya.wang@mediatek.com>
5 */
6
7/dts-v1/;
8#include <dt-bindings/clock/mt8195-clk.h>

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734 };
735
736 scp_adsp: clock-controller@10720000 {
737 compatible = "mediatek,mt8195-scp_adsp";
738 reg = <0 0x10720000 0 0x1000>;
739 #clock-cells = <1>;
740 };
741
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (c) 2021 MediaTek Inc.
4 * Author: Seiya Wang <seiya.wang@mediatek.com>
5 */
6
7/dts-v1/;
8#include <dt-bindings/clock/mt8195-clk.h>

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734 };
735
736 scp_adsp: clock-controller@10720000 {
737 compatible = "mediatek,mt8195-scp_adsp";
738 reg = <0 0x10720000 0 0x1000>;
739 #clock-cells = <1>;
740 };
741
742 adsp: dsp@10803000 {
743 compatible = "mediatek,mt8195-dsp";
744 reg = <0 0x10803000 0 0x1000>,
745 <0 0x10840000 0 0x40000>;
746 reg-names = "cfg", "sram";
747 clocks = <&topckgen CLK_TOP_ADSP>,
748 <&clk26m>,
749 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>,
750 <&topckgen CLK_TOP_MAINPLL_D7_D2>,
751 <&scp_adsp CLK_SCP_ADSP_AUDIODSP>,
752 <&topckgen CLK_TOP_AUDIO_H>;
753 clock-names = "adsp_sel",
754 "clk26m_ck",
755 "audio_local_bus",
756 "mainpll_d7_d2",
757 "scp_adsp_audiodsp",
758 "audio_h";
759 power-domains = <&spm MT8195_POWER_DOMAIN_ADSP>;
760 mbox-names = "rx", "tx";
761 mboxes = <&adsp_mailbox0>, <&adsp_mailbox1>;
762 status = "disabled";
763 };
764
765 adsp_mailbox0: mailbox@10816000 {
766 compatible = "mediatek,mt8195-adsp-mbox";
767 #mbox-cells = <0>;
768 reg = <0 0x10816000 0 0x1000>;
769 interrupts = <GIC_SPI 702 IRQ_TYPE_LEVEL_HIGH 0>;
770 };
771
772 adsp_mailbox1: mailbox@10817000 {
773 compatible = "mediatek,mt8195-adsp-mbox";
774 #mbox-cells = <0>;
775 reg = <0 0x10817000 0 0x1000>;
776 interrupts = <GIC_SPI 703 IRQ_TYPE_LEVEL_HIGH 0>;
777 };
778
742 afe: mt8195-afe-pcm@10890000 {
743 compatible = "mediatek,mt8195-audio";
744 reg = <0 0x10890000 0 0x10000>;
745 mediatek,topckgen = <&topckgen>;
746 power-domains = <&spm MT8195_POWER_DOMAIN_AUDIO>;
747 interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH 0>;
748 clocks = <&clk26m>,
749 <&apmixedsys CLK_APMIXED_APLL1>,

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780 compatible = "mediatek,mt8195-audio";
781 reg = <0 0x10890000 0 0x10000>;
782 mediatek,topckgen = <&topckgen>;
783 power-domains = <&spm MT8195_POWER_DOMAIN_AUDIO>;
784 interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH 0>;
785 clocks = <&clk26m>,
786 <&apmixedsys CLK_APMIXED_APLL1>,

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