mt8195.dtsi (329239a154bc735a74c33e33c5139b30949efc57) mt8195.dtsi (b852ee68fd722294145d86bb4d383d4ad4ae270f)
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (c) 2021 MediaTek Inc.
4 * Author: Seiya Wang <seiya.wang@mediatek.com>
5 */
6
7/dts-v1/;
8#include <dt-bindings/clock/mt8195-clk.h>

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1953 compatible = "mediatek,mt8195-vencsys_core1";
1954 reg = <0 0x1b000000 0 0x1000>;
1955 #clock-cells = <1>;
1956 };
1957
1958 vdosys0: syscon@1c01a000 {
1959 compatible = "mediatek,mt8195-mmsys", "syscon";
1960 reg = <0 0x1c01a000 0 0x1000>;
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (c) 2021 MediaTek Inc.
4 * Author: Seiya Wang <seiya.wang@mediatek.com>
5 */
6
7/dts-v1/;
8#include <dt-bindings/clock/mt8195-clk.h>

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1953 compatible = "mediatek,mt8195-vencsys_core1";
1954 reg = <0 0x1b000000 0 0x1000>;
1955 #clock-cells = <1>;
1956 };
1957
1958 vdosys0: syscon@1c01a000 {
1959 compatible = "mediatek,mt8195-mmsys", "syscon";
1960 reg = <0 0x1c01a000 0 0x1000>;
1961 mboxes = <&gce0 0 CMDQ_THR_PRIO_4>;
1961 #clock-cells = <1>;
1962 };
1963
1964 larb20: larb@1b010000 {
1965 compatible = "mediatek,mt8195-smi-larb";
1966 reg = <0 0x1b010000 0 0x1000>;
1967 mediatek,larb-id = <20>;
1968 mediatek,smi = <&smi_common_vpp>;
1969 clocks = <&vencsys_core1 CLK_VENC_CORE1_LARB>,
1970 <&vencsys_core1 CLK_VENC_CORE1_GALS>,
1971 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>;
1972 clock-names = "apb", "smi", "gals";
1973 power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>;
1974 };
1975
1962 #clock-cells = <1>;
1963 };
1964
1965 larb20: larb@1b010000 {
1966 compatible = "mediatek,mt8195-smi-larb";
1967 reg = <0 0x1b010000 0 0x1000>;
1968 mediatek,larb-id = <20>;
1969 mediatek,smi = <&smi_common_vpp>;
1970 clocks = <&vencsys_core1 CLK_VENC_CORE1_LARB>,
1971 <&vencsys_core1 CLK_VENC_CORE1_GALS>,
1972 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>;
1973 clock-names = "apb", "smi", "gals";
1974 power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>;
1975 };
1976
1977 ovl0: ovl@1c000000 {
1978 compatible = "mediatek,mt8195-disp-ovl", "mediatek,mt8183-disp-ovl";
1979 reg = <0 0x1c000000 0 0x1000>;
1980 interrupts = <GIC_SPI 636 IRQ_TYPE_LEVEL_HIGH 0>;
1981 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
1982 clocks = <&vdosys0 CLK_VDO0_DISP_OVL0>;
1983 iommus = <&iommu_vdo M4U_PORT_L0_DISP_OVL0_RDMA0>;
1984 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x0000 0x1000>;
1985 };
1986
1987 rdma0: rdma@1c002000 {
1988 compatible = "mediatek,mt8195-disp-rdma";
1989 reg = <0 0x1c002000 0 0x1000>;
1990 interrupts = <GIC_SPI 638 IRQ_TYPE_LEVEL_HIGH 0>;
1991 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
1992 clocks = <&vdosys0 CLK_VDO0_DISP_RDMA0>;
1993 iommus = <&iommu_vdo M4U_PORT_L0_DISP_RDMA0>;
1994 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x2000 0x1000>;
1995 };
1996
1997 color0: color@1c003000 {
1998 compatible = "mediatek,mt8195-disp-color", "mediatek,mt8173-disp-color";
1999 reg = <0 0x1c003000 0 0x1000>;
2000 interrupts = <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH 0>;
2001 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
2002 clocks = <&vdosys0 CLK_VDO0_DISP_COLOR0>;
2003 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x3000 0x1000>;
2004 };
2005
2006 ccorr0: ccorr@1c004000 {
2007 compatible = "mediatek,mt8195-disp-ccorr", "mediatek,mt8192-disp-ccorr";
2008 reg = <0 0x1c004000 0 0x1000>;
2009 interrupts = <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH 0>;
2010 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
2011 clocks = <&vdosys0 CLK_VDO0_DISP_CCORR0>;
2012 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x4000 0x1000>;
2013 };
2014
2015 aal0: aal@1c005000 {
2016 compatible = "mediatek,mt8195-disp-aal", "mediatek,mt8183-disp-aal";
2017 reg = <0 0x1c005000 0 0x1000>;
2018 interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH 0>;
2019 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
2020 clocks = <&vdosys0 CLK_VDO0_DISP_AAL0>;
2021 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x5000 0x1000>;
2022 };
2023
2024 gamma0: gamma@1c006000 {
2025 compatible = "mediatek,mt8195-disp-gamma", "mediatek,mt8183-disp-gamma";
2026 reg = <0 0x1c006000 0 0x1000>;
2027 interrupts = <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH 0>;
2028 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
2029 clocks = <&vdosys0 CLK_VDO0_DISP_GAMMA0>;
2030 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x6000 0x1000>;
2031 };
2032
2033 dither0: dither@1c007000 {
2034 compatible = "mediatek,mt8195-disp-dither", "mediatek,mt8183-disp-dither";
2035 reg = <0 0x1c007000 0 0x1000>;
2036 interrupts = <GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH 0>;
2037 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
2038 clocks = <&vdosys0 CLK_VDO0_DISP_DITHER0>;
2039 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x7000 0x1000>;
2040 };
2041
2042 dsc0: dsc@1c009000 {
2043 compatible = "mediatek,mt8195-disp-dsc";
2044 reg = <0 0x1c009000 0 0x1000>;
2045 interrupts = <GIC_SPI 645 IRQ_TYPE_LEVEL_HIGH 0>;
2046 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
2047 clocks = <&vdosys0 CLK_VDO0_DSC_WRAP0>;
2048 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x9000 0x1000>;
2049 };
2050
2051 merge0: merge@1c014000 {
2052 compatible = "mediatek,mt8195-disp-merge";
2053 reg = <0 0x1c014000 0 0x1000>;
2054 interrupts = <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH 0>;
2055 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
2056 clocks = <&vdosys0 CLK_VDO0_VPP_MERGE0>;
2057 mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0x4000 0x1000>;
2058 };
2059
2060 mutex: mutex@1c016000 {
2061 compatible = "mediatek,mt8195-disp-mutex";
2062 reg = <0 0x1c016000 0 0x1000>;
2063 interrupts = <GIC_SPI 658 IRQ_TYPE_LEVEL_HIGH 0>;
2064 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
2065 clocks = <&vdosys0 CLK_VDO0_DISP_MUTEX0>;
2066 mediatek,gce-events = <CMDQ_EVENT_VDO0_DISP_STREAM_DONE_0>;
2067 };
2068
1976 larb0: larb@1c018000 {
1977 compatible = "mediatek,mt8195-smi-larb";
1978 reg = <0 0x1c018000 0 0x1000>;
1979 mediatek,larb-id = <0>;
1980 mediatek,smi = <&smi_common_vdo>;
1981 clocks = <&vdosys0 CLK_VDO0_SMI_LARB>,
1982 <&vdosys0 CLK_VDO0_SMI_LARB>,
1983 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB0>;

--- 73 unchanged lines hidden --- 		2069 larb0: larb@1c018000 {
2070 compatible = "mediatek,mt8195-smi-larb";
2071 reg = <0 0x1c018000 0 0x1000>;
2072 mediatek,larb-id = <0>;
2073 mediatek,smi = <&smi_common_vdo>;
2074 clocks = <&vdosys0 CLK_VDO0_SMI_LARB>,
2075 <&vdosys0 CLK_VDO0_SMI_LARB>,
2076 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB0>;

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