mt8195.dtsi (2b515194bf0cb8f380586e96d2530a51b1878e6a) mt8195.dtsi (385e0eedb7ab8069894c59455892dd916acb4456)
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (c) 2021 MediaTek Inc.
4 * Author: Seiya Wang <seiya.wang@mediatek.com>
5 */
6
7/dts-v1/;
8#include <dt-bindings/clock/mt8195-clk.h>

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692 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH 0>;
693 clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>,
694 <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>;
695 clock-names = "spi", "wrap";
696 assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC>;
697 assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>;
698 };
699
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (c) 2021 MediaTek Inc.
4 * Author: Seiya Wang <seiya.wang@mediatek.com>
5 */
6
7/dts-v1/;
8#include <dt-bindings/clock/mt8195-clk.h>

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692 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH 0>;
693 clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>,
694 <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>;
695 clock-names = "spi", "wrap";
696 assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC>;
697 assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>;
698 };
699
700 spmi: spmi@10027000 {
701 compatible = "mediatek,mt8195-spmi";
702 reg = <0 0x10027000 0 0x000e00>,
703 <0 0x10029000 0 0x000100>;
704 reg-names = "pmif", "spmimst";
705 clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>,
706 <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>,
707 <&topckgen CLK_TOP_SPMI_M_MST>;
708 clock-names = "pmif_sys_ck",
709 "pmif_tmr_ck",
710 "spmimst_clk_mux";
711 assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC>;
712 assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>;
713 };
714
700 scp_adsp: clock-controller@10720000 {
701 compatible = "mediatek,mt8195-scp_adsp";
702 reg = <0 0x10720000 0 0x1000>;
703 #clock-cells = <1>;
704 };
705
706 uart0: serial@11001100 {
707 compatible = "mediatek,mt8195-uart",

--- 755 unchanged lines hidden --- 		715 scp_adsp: clock-controller@10720000 {
716 compatible = "mediatek,mt8195-scp_adsp";
717 reg = <0 0x10720000 0 0x1000>;
718 #clock-cells = <1>;
719 };
720
721 uart0: serial@11001100 {
722 compatible = "mediatek,mt8195-uart",

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