mt8195.dtsi (0f1c806b65d136a5fe0b88adad5ff1cb451fc401) mt8195.dtsi (b68188a70ee9e532f637f6107657c90be055cf69)
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (c) 2021 MediaTek Inc.
4 * Author: Seiya Wang <seiya.wang@mediatek.com>
5 */
6
7/dts-v1/;
8#include <dt-bindings/clock/mt8195-clk.h>

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34 device_type = "cpu";
35 compatible = "arm,cortex-a55";
36 reg = <0x000>;
37 enable-method = "psci";
38 performance-domains = <&performance 0>;
39 clock-frequency = <1701000000>;
40 capacity-dmips-mhz = <308>;
41 cpu-idle-states = <&cpu_off_l &cluster_off_l>;
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (c) 2021 MediaTek Inc.
4 * Author: Seiya Wang <seiya.wang@mediatek.com>
5 */
6
7/dts-v1/;
8#include <dt-bindings/clock/mt8195-clk.h>

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34 device_type = "cpu";
35 compatible = "arm,cortex-a55";
36 reg = <0x000>;
37 enable-method = "psci";
38 performance-domains = <&performance 0>;
39 clock-frequency = <1701000000>;
40 capacity-dmips-mhz = <308>;
41 cpu-idle-states = <&cpu_off_l &cluster_off_l>;
42 i-cache-size = <32768>;
43 i-cache-line-size = <64>;
44 i-cache-sets = <128>;
45 d-cache-size = <32768>;
46 d-cache-line-size = <64>;
47 d-cache-sets = <128>;
42 next-level-cache = <&l2_0>;
43 #cooling-cells = <2>;
44 };
45
46 cpu1: cpu@100 {
47 device_type = "cpu";
48 compatible = "arm,cortex-a55";
49 reg = <0x100>;
50 enable-method = "psci";
51 performance-domains = <&performance 0>;
52 clock-frequency = <1701000000>;
53 capacity-dmips-mhz = <308>;
54 cpu-idle-states = <&cpu_off_l &cluster_off_l>;
48 next-level-cache = <&l2_0>;
49 #cooling-cells = <2>;
50 };
51
52 cpu1: cpu@100 {
53 device_type = "cpu";
54 compatible = "arm,cortex-a55";
55 reg = <0x100>;
56 enable-method = "psci";
57 performance-domains = <&performance 0>;
58 clock-frequency = <1701000000>;
59 capacity-dmips-mhz = <308>;
60 cpu-idle-states = <&cpu_off_l &cluster_off_l>;
61 i-cache-size = <32768>;
62 i-cache-line-size = <64>;
63 i-cache-sets = <128>;
64 d-cache-size = <32768>;
65 d-cache-line-size = <64>;
66 d-cache-sets = <128>;
55 next-level-cache = <&l2_0>;
56 #cooling-cells = <2>;
57 };
58
59 cpu2: cpu@200 {
60 device_type = "cpu";
61 compatible = "arm,cortex-a55";
62 reg = <0x200>;
63 enable-method = "psci";
64 performance-domains = <&performance 0>;
65 clock-frequency = <1701000000>;
66 capacity-dmips-mhz = <308>;
67 cpu-idle-states = <&cpu_off_l &cluster_off_l>;
67 next-level-cache = <&l2_0>;
68 #cooling-cells = <2>;
69 };
70
71 cpu2: cpu@200 {
72 device_type = "cpu";
73 compatible = "arm,cortex-a55";
74 reg = <0x200>;
75 enable-method = "psci";
76 performance-domains = <&performance 0>;
77 clock-frequency = <1701000000>;
78 capacity-dmips-mhz = <308>;
79 cpu-idle-states = <&cpu_off_l &cluster_off_l>;
80 i-cache-size = <32768>;
81 i-cache-line-size = <64>;
82 i-cache-sets = <128>;
83 d-cache-size = <32768>;
84 d-cache-line-size = <64>;
85 d-cache-sets = <128>;
68 next-level-cache = <&l2_0>;
69 #cooling-cells = <2>;
70 };
71
72 cpu3: cpu@300 {
73 device_type = "cpu";
74 compatible = "arm,cortex-a55";
75 reg = <0x300>;
76 enable-method = "psci";
77 performance-domains = <&performance 0>;
78 clock-frequency = <1701000000>;
79 capacity-dmips-mhz = <308>;
80 cpu-idle-states = <&cpu_off_l &cluster_off_l>;
86 next-level-cache = <&l2_0>;
87 #cooling-cells = <2>;
88 };
89
90 cpu3: cpu@300 {
91 device_type = "cpu";
92 compatible = "arm,cortex-a55";
93 reg = <0x300>;
94 enable-method = "psci";
95 performance-domains = <&performance 0>;
96 clock-frequency = <1701000000>;
97 capacity-dmips-mhz = <308>;
98 cpu-idle-states = <&cpu_off_l &cluster_off_l>;
99 i-cache-size = <32768>;
100 i-cache-line-size = <64>;
101 i-cache-sets = <128>;
102 d-cache-size = <32768>;
103 d-cache-line-size = <64>;
104 d-cache-sets = <128>;
81 next-level-cache = <&l2_0>;
82 #cooling-cells = <2>;
83 };
84
85 cpu4: cpu@400 {
86 device_type = "cpu";
87 compatible = "arm,cortex-a78";
88 reg = <0x400>;
89 enable-method = "psci";
90 performance-domains = <&performance 1>;
91 clock-frequency = <2171000000>;
92 capacity-dmips-mhz = <1024>;
93 cpu-idle-states = <&cpu_off_b &cluster_off_b>;
105 next-level-cache = <&l2_0>;
106 #cooling-cells = <2>;
107 };
108
109 cpu4: cpu@400 {
110 device_type = "cpu";
111 compatible = "arm,cortex-a78";
112 reg = <0x400>;
113 enable-method = "psci";
114 performance-domains = <&performance 1>;
115 clock-frequency = <2171000000>;
116 capacity-dmips-mhz = <1024>;
117 cpu-idle-states = <&cpu_off_b &cluster_off_b>;
118 i-cache-size = <65536>;
119 i-cache-line-size = <64>;
120 i-cache-sets = <256>;
121 d-cache-size = <65536>;
122 d-cache-line-size = <64>;
123 d-cache-sets = <256>;
94 next-level-cache = <&l2_1>;
95 #cooling-cells = <2>;
96 };
97
98 cpu5: cpu@500 {
99 device_type = "cpu";
100 compatible = "arm,cortex-a78";
101 reg = <0x500>;
102 enable-method = "psci";
103 performance-domains = <&performance 1>;
104 clock-frequency = <2171000000>;
105 capacity-dmips-mhz = <1024>;
106 cpu-idle-states = <&cpu_off_b &cluster_off_b>;
124 next-level-cache = <&l2_1>;
125 #cooling-cells = <2>;
126 };
127
128 cpu5: cpu@500 {
129 device_type = "cpu";
130 compatible = "arm,cortex-a78";
131 reg = <0x500>;
132 enable-method = "psci";
133 performance-domains = <&performance 1>;
134 clock-frequency = <2171000000>;
135 capacity-dmips-mhz = <1024>;
136 cpu-idle-states = <&cpu_off_b &cluster_off_b>;
137 i-cache-size = <65536>;
138 i-cache-line-size = <64>;
139 i-cache-sets = <256>;
140 d-cache-size = <65536>;
141 d-cache-line-size = <64>;
142 d-cache-sets = <256>;
107 next-level-cache = <&l2_1>;
108 #cooling-cells = <2>;
109 };
110
111 cpu6: cpu@600 {
112 device_type = "cpu";
113 compatible = "arm,cortex-a78";
114 reg = <0x600>;
115 enable-method = "psci";
116 performance-domains = <&performance 1>;
117 clock-frequency = <2171000000>;
118 capacity-dmips-mhz = <1024>;
119 cpu-idle-states = <&cpu_off_b &cluster_off_b>;
143 next-level-cache = <&l2_1>;
144 #cooling-cells = <2>;
145 };
146
147 cpu6: cpu@600 {
148 device_type = "cpu";
149 compatible = "arm,cortex-a78";
150 reg = <0x600>;
151 enable-method = "psci";
152 performance-domains = <&performance 1>;
153 clock-frequency = <2171000000>;
154 capacity-dmips-mhz = <1024>;
155 cpu-idle-states = <&cpu_off_b &cluster_off_b>;
156 i-cache-size = <65536>;
157 i-cache-line-size = <64>;
158 i-cache-sets = <256>;
159 d-cache-size = <65536>;
160 d-cache-line-size = <64>;
161 d-cache-sets = <256>;
120 next-level-cache = <&l2_1>;
121 #cooling-cells = <2>;
122 };
123
124 cpu7: cpu@700 {
125 device_type = "cpu";
126 compatible = "arm,cortex-a78";
127 reg = <0x700>;
128 enable-method = "psci";
129 performance-domains = <&performance 1>;
130 clock-frequency = <2171000000>;
131 capacity-dmips-mhz = <1024>;
132 cpu-idle-states = <&cpu_off_b &cluster_off_b>;
162 next-level-cache = <&l2_1>;
163 #cooling-cells = <2>;
164 };
165
166 cpu7: cpu@700 {
167 device_type = "cpu";
168 compatible = "arm,cortex-a78";
169 reg = <0x700>;
170 enable-method = "psci";
171 performance-domains = <&performance 1>;
172 clock-frequency = <2171000000>;
173 capacity-dmips-mhz = <1024>;
174 cpu-idle-states = <&cpu_off_b &cluster_off_b>;
175 i-cache-size = <65536>;
176 i-cache-line-size = <64>;
177 i-cache-sets = <256>;
178 d-cache-size = <65536>;
179 d-cache-line-size = <64>;
180 d-cache-sets = <256>;
133 next-level-cache = <&l2_1>;
134 #cooling-cells = <2>;
135 };
136
137 cpu-map {
138 cluster0 {
139 core0 {
140 cpu = <&cpu0>;

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210 exit-latency-us = <200>;
211 min-residency-us = <1000>;
212 };
213 };
214
215 l2_0: l2-cache0 {
216 compatible = "cache";
217 cache-level = <2>;
181 next-level-cache = <&l2_1>;
182 #cooling-cells = <2>;
183 };
184
185 cpu-map {
186 cluster0 {
187 core0 {
188 cpu = <&cpu0>;

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258 exit-latency-us = <200>;
259 min-residency-us = <1000>;
260 };
261 };
262
263 l2_0: l2-cache0 {
264 compatible = "cache";
265 cache-level = <2>;
266 cache-size = <131072>;
267 cache-line-size = <64>;
268 cache-sets = <512>;
218 next-level-cache = <&l3_0>;
219 };
220
221 l2_1: l2-cache1 {
222 compatible = "cache";
223 cache-level = <2>;
269 next-level-cache = <&l3_0>;
270 };
271
272 l2_1: l2-cache1 {
273 compatible = "cache";
274 cache-level = <2>;
275 cache-size = <262144>;
276 cache-line-size = <64>;
277 cache-sets = <512>;
224 next-level-cache = <&l3_0>;
225 };
226
227 l3_0: l3-cache {
228 compatible = "cache";
229 cache-level = <3>;
278 next-level-cache = <&l3_0>;
279 };
280
281 l3_0: l3-cache {
282 compatible = "cache";
283 cache-level = <3>;
284 cache-size = <2097152>;
285 cache-line-size = <64>;
286 cache-sets = <2048>;
287 cache-unified;
230 };
231 };
232
233 dsu-pmu {
234 compatible = "arm,dsu-pmu";
235 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>;
236 cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>,
237 <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;

--- 2157 unchanged lines hidden --- 		288 };
289 };
290
291 dsu-pmu {
292 compatible = "arm,dsu-pmu";
293 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>;
294 cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>,
295 <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;

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