1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (c) 2021 MediaTek Inc. 4 * Author: Seiya Wang <seiya.wang@mediatek.com> 5 */ 6 7/dts-v1/; 8#include <dt-bindings/clock/mt8195-clk.h> 9#include <dt-bindings/gce/mt8195-gce.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/interrupt-controller/irq.h> 12#include <dt-bindings/memory/mt8195-memory-port.h> 13#include <dt-bindings/phy/phy.h> 14#include <dt-bindings/pinctrl/mt8195-pinfunc.h> 15#include <dt-bindings/power/mt8195-power.h> 16#include <dt-bindings/reset/mt8195-resets.h> 17 18/ { 19 compatible = "mediatek,mt8195"; 20 interrupt-parent = <&gic>; 21 #address-cells = <2>; 22 #size-cells = <2>; 23 24 aliases { 25 gce0 = &gce0; 26 gce1 = &gce1; 27 }; 28 29 cpus { 30 #address-cells = <1>; 31 #size-cells = <0>; 32 33 cpu0: cpu@0 { 34 device_type = "cpu"; 35 compatible = "arm,cortex-a55"; 36 reg = <0x000>; 37 enable-method = "psci"; 38 performance-domains = <&performance 0>; 39 clock-frequency = <1701000000>; 40 capacity-dmips-mhz = <308>; 41 cpu-idle-states = <&cpu_off_l &cluster_off_l>; 42 i-cache-size = <32768>; 43 i-cache-line-size = <64>; 44 i-cache-sets = <128>; 45 d-cache-size = <32768>; 46 d-cache-line-size = <64>; 47 d-cache-sets = <128>; 48 next-level-cache = <&l2_0>; 49 #cooling-cells = <2>; 50 }; 51 52 cpu1: cpu@100 { 53 device_type = "cpu"; 54 compatible = "arm,cortex-a55"; 55 reg = <0x100>; 56 enable-method = "psci"; 57 performance-domains = <&performance 0>; 58 clock-frequency = <1701000000>; 59 capacity-dmips-mhz = <308>; 60 cpu-idle-states = <&cpu_off_l &cluster_off_l>; 61 i-cache-size = <32768>; 62 i-cache-line-size = <64>; 63 i-cache-sets = <128>; 64 d-cache-size = <32768>; 65 d-cache-line-size = <64>; 66 d-cache-sets = <128>; 67 next-level-cache = <&l2_0>; 68 #cooling-cells = <2>; 69 }; 70 71 cpu2: cpu@200 { 72 device_type = "cpu"; 73 compatible = "arm,cortex-a55"; 74 reg = <0x200>; 75 enable-method = "psci"; 76 performance-domains = <&performance 0>; 77 clock-frequency = <1701000000>; 78 capacity-dmips-mhz = <308>; 79 cpu-idle-states = <&cpu_off_l &cluster_off_l>; 80 i-cache-size = <32768>; 81 i-cache-line-size = <64>; 82 i-cache-sets = <128>; 83 d-cache-size = <32768>; 84 d-cache-line-size = <64>; 85 d-cache-sets = <128>; 86 next-level-cache = <&l2_0>; 87 #cooling-cells = <2>; 88 }; 89 90 cpu3: cpu@300 { 91 device_type = "cpu"; 92 compatible = "arm,cortex-a55"; 93 reg = <0x300>; 94 enable-method = "psci"; 95 performance-domains = <&performance 0>; 96 clock-frequency = <1701000000>; 97 capacity-dmips-mhz = <308>; 98 cpu-idle-states = <&cpu_off_l &cluster_off_l>; 99 i-cache-size = <32768>; 100 i-cache-line-size = <64>; 101 i-cache-sets = <128>; 102 d-cache-size = <32768>; 103 d-cache-line-size = <64>; 104 d-cache-sets = <128>; 105 next-level-cache = <&l2_0>; 106 #cooling-cells = <2>; 107 }; 108 109 cpu4: cpu@400 { 110 device_type = "cpu"; 111 compatible = "arm,cortex-a78"; 112 reg = <0x400>; 113 enable-method = "psci"; 114 performance-domains = <&performance 1>; 115 clock-frequency = <2171000000>; 116 capacity-dmips-mhz = <1024>; 117 cpu-idle-states = <&cpu_off_b &cluster_off_b>; 118 i-cache-size = <65536>; 119 i-cache-line-size = <64>; 120 i-cache-sets = <256>; 121 d-cache-size = <65536>; 122 d-cache-line-size = <64>; 123 d-cache-sets = <256>; 124 next-level-cache = <&l2_1>; 125 #cooling-cells = <2>; 126 }; 127 128 cpu5: cpu@500 { 129 device_type = "cpu"; 130 compatible = "arm,cortex-a78"; 131 reg = <0x500>; 132 enable-method = "psci"; 133 performance-domains = <&performance 1>; 134 clock-frequency = <2171000000>; 135 capacity-dmips-mhz = <1024>; 136 cpu-idle-states = <&cpu_off_b &cluster_off_b>; 137 i-cache-size = <65536>; 138 i-cache-line-size = <64>; 139 i-cache-sets = <256>; 140 d-cache-size = <65536>; 141 d-cache-line-size = <64>; 142 d-cache-sets = <256>; 143 next-level-cache = <&l2_1>; 144 #cooling-cells = <2>; 145 }; 146 147 cpu6: cpu@600 { 148 device_type = "cpu"; 149 compatible = "arm,cortex-a78"; 150 reg = <0x600>; 151 enable-method = "psci"; 152 performance-domains = <&performance 1>; 153 clock-frequency = <2171000000>; 154 capacity-dmips-mhz = <1024>; 155 cpu-idle-states = <&cpu_off_b &cluster_off_b>; 156 i-cache-size = <65536>; 157 i-cache-line-size = <64>; 158 i-cache-sets = <256>; 159 d-cache-size = <65536>; 160 d-cache-line-size = <64>; 161 d-cache-sets = <256>; 162 next-level-cache = <&l2_1>; 163 #cooling-cells = <2>; 164 }; 165 166 cpu7: cpu@700 { 167 device_type = "cpu"; 168 compatible = "arm,cortex-a78"; 169 reg = <0x700>; 170 enable-method = "psci"; 171 performance-domains = <&performance 1>; 172 clock-frequency = <2171000000>; 173 capacity-dmips-mhz = <1024>; 174 cpu-idle-states = <&cpu_off_b &cluster_off_b>; 175 i-cache-size = <65536>; 176 i-cache-line-size = <64>; 177 i-cache-sets = <256>; 178 d-cache-size = <65536>; 179 d-cache-line-size = <64>; 180 d-cache-sets = <256>; 181 next-level-cache = <&l2_1>; 182 #cooling-cells = <2>; 183 }; 184 185 cpu-map { 186 cluster0 { 187 core0 { 188 cpu = <&cpu0>; 189 }; 190 191 core1 { 192 cpu = <&cpu1>; 193 }; 194 195 core2 { 196 cpu = <&cpu2>; 197 }; 198 199 core3 { 200 cpu = <&cpu3>; 201 }; 202 }; 203 204 cluster1 { 205 core0 { 206 cpu = <&cpu4>; 207 }; 208 209 core1 { 210 cpu = <&cpu5>; 211 }; 212 213 core2 { 214 cpu = <&cpu6>; 215 }; 216 217 core3 { 218 cpu = <&cpu7>; 219 }; 220 }; 221 }; 222 223 idle-states { 224 entry-method = "psci"; 225 226 cpu_off_l: cpu-off-l { 227 compatible = "arm,idle-state"; 228 arm,psci-suspend-param = <0x00010001>; 229 local-timer-stop; 230 entry-latency-us = <50>; 231 exit-latency-us = <95>; 232 min-residency-us = <580>; 233 }; 234 235 cpu_off_b: cpu-off-b { 236 compatible = "arm,idle-state"; 237 arm,psci-suspend-param = <0x00010001>; 238 local-timer-stop; 239 entry-latency-us = <45>; 240 exit-latency-us = <140>; 241 min-residency-us = <740>; 242 }; 243 244 cluster_off_l: cluster-off-l { 245 compatible = "arm,idle-state"; 246 arm,psci-suspend-param = <0x01010002>; 247 local-timer-stop; 248 entry-latency-us = <55>; 249 exit-latency-us = <155>; 250 min-residency-us = <840>; 251 }; 252 253 cluster_off_b: cluster-off-b { 254 compatible = "arm,idle-state"; 255 arm,psci-suspend-param = <0x01010002>; 256 local-timer-stop; 257 entry-latency-us = <50>; 258 exit-latency-us = <200>; 259 min-residency-us = <1000>; 260 }; 261 }; 262 263 l2_0: l2-cache0 { 264 compatible = "cache"; 265 cache-level = <2>; 266 cache-size = <131072>; 267 cache-line-size = <64>; 268 cache-sets = <512>; 269 next-level-cache = <&l3_0>; 270 }; 271 272 l2_1: l2-cache1 { 273 compatible = "cache"; 274 cache-level = <2>; 275 cache-size = <262144>; 276 cache-line-size = <64>; 277 cache-sets = <512>; 278 next-level-cache = <&l3_0>; 279 }; 280 281 l3_0: l3-cache { 282 compatible = "cache"; 283 cache-level = <3>; 284 cache-size = <2097152>; 285 cache-line-size = <64>; 286 cache-sets = <2048>; 287 cache-unified; 288 }; 289 }; 290 291 dsu-pmu { 292 compatible = "arm,dsu-pmu"; 293 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>; 294 cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>, 295 <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>; 296 }; 297 298 dmic_codec: dmic-codec { 299 compatible = "dmic-codec"; 300 num-channels = <2>; 301 wakeup-delay-ms = <50>; 302 }; 303 304 sound: mt8195-sound { 305 mediatek,platform = <&afe>; 306 status = "disabled"; 307 }; 308 309 clk13m: fixed-factor-clock-13m { 310 compatible = "fixed-factor-clock"; 311 #clock-cells = <0>; 312 clocks = <&clk26m>; 313 clock-div = <2>; 314 clock-mult = <1>; 315 clock-output-names = "clk13m"; 316 }; 317 318 clk26m: oscillator-26m { 319 compatible = "fixed-clock"; 320 #clock-cells = <0>; 321 clock-frequency = <26000000>; 322 clock-output-names = "clk26m"; 323 }; 324 325 clk32k: oscillator-32k { 326 compatible = "fixed-clock"; 327 #clock-cells = <0>; 328 clock-frequency = <32768>; 329 clock-output-names = "clk32k"; 330 }; 331 332 performance: performance-controller@11bc10 { 333 compatible = "mediatek,cpufreq-hw"; 334 reg = <0 0x0011bc10 0 0x120>, <0 0x0011bd30 0 0x120>; 335 #performance-domain-cells = <1>; 336 }; 337 338 pmu-a55 { 339 compatible = "arm,cortex-a55-pmu"; 340 interrupt-parent = <&gic>; 341 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>; 342 }; 343 344 pmu-a78 { 345 compatible = "arm,cortex-a78-pmu"; 346 interrupt-parent = <&gic>; 347 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>; 348 }; 349 350 psci { 351 compatible = "arm,psci-1.0"; 352 method = "smc"; 353 }; 354 355 timer: timer { 356 compatible = "arm,armv8-timer"; 357 interrupt-parent = <&gic>; 358 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>, 359 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>, 360 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>, 361 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>; 362 }; 363 364 soc { 365 #address-cells = <2>; 366 #size-cells = <2>; 367 compatible = "simple-bus"; 368 ranges; 369 370 gic: interrupt-controller@c000000 { 371 compatible = "arm,gic-v3"; 372 #interrupt-cells = <4>; 373 #redistributor-regions = <1>; 374 interrupt-parent = <&gic>; 375 interrupt-controller; 376 reg = <0 0x0c000000 0 0x40000>, 377 <0 0x0c040000 0 0x200000>; 378 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 379 380 ppi-partitions { 381 ppi_cluster0: interrupt-partition-0 { 382 affinity = <&cpu0 &cpu1 &cpu2 &cpu3>; 383 }; 384 385 ppi_cluster1: interrupt-partition-1 { 386 affinity = <&cpu4 &cpu5 &cpu6 &cpu7>; 387 }; 388 }; 389 }; 390 391 topckgen: syscon@10000000 { 392 compatible = "mediatek,mt8195-topckgen", "syscon"; 393 reg = <0 0x10000000 0 0x1000>; 394 #clock-cells = <1>; 395 }; 396 397 infracfg_ao: syscon@10001000 { 398 compatible = "mediatek,mt8195-infracfg_ao", "syscon", "simple-mfd"; 399 reg = <0 0x10001000 0 0x1000>; 400 #clock-cells = <1>; 401 #reset-cells = <1>; 402 }; 403 404 pericfg: syscon@10003000 { 405 compatible = "mediatek,mt8195-pericfg", "syscon"; 406 reg = <0 0x10003000 0 0x1000>; 407 #clock-cells = <1>; 408 }; 409 410 pio: pinctrl@10005000 { 411 compatible = "mediatek,mt8195-pinctrl"; 412 reg = <0 0x10005000 0 0x1000>, 413 <0 0x11d10000 0 0x1000>, 414 <0 0x11d30000 0 0x1000>, 415 <0 0x11d40000 0 0x1000>, 416 <0 0x11e20000 0 0x1000>, 417 <0 0x11eb0000 0 0x1000>, 418 <0 0x11f40000 0 0x1000>, 419 <0 0x1000b000 0 0x1000>; 420 reg-names = "iocfg0", "iocfg_bm", "iocfg_bl", 421 "iocfg_br", "iocfg_lm", "iocfg_rb", 422 "iocfg_tl", "eint"; 423 gpio-controller; 424 #gpio-cells = <2>; 425 gpio-ranges = <&pio 0 0 144>; 426 interrupt-controller; 427 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH 0>; 428 #interrupt-cells = <2>; 429 }; 430 431 scpsys: syscon@10006000 { 432 compatible = "mediatek,mt8195-scpsys", "syscon", "simple-mfd"; 433 reg = <0 0x10006000 0 0x1000>; 434 435 /* System Power Manager */ 436 spm: power-controller { 437 compatible = "mediatek,mt8195-power-controller"; 438 #address-cells = <1>; 439 #size-cells = <0>; 440 #power-domain-cells = <1>; 441 442 /* power domain of the SoC */ 443 mfg0: power-domain@MT8195_POWER_DOMAIN_MFG0 { 444 reg = <MT8195_POWER_DOMAIN_MFG0>; 445 #address-cells = <1>; 446 #size-cells = <0>; 447 #power-domain-cells = <1>; 448 449 power-domain@MT8195_POWER_DOMAIN_MFG1 { 450 reg = <MT8195_POWER_DOMAIN_MFG1>; 451 clocks = <&apmixedsys CLK_APMIXED_MFGPLL>; 452 clock-names = "mfg"; 453 mediatek,infracfg = <&infracfg_ao>; 454 #address-cells = <1>; 455 #size-cells = <0>; 456 #power-domain-cells = <1>; 457 458 power-domain@MT8195_POWER_DOMAIN_MFG2 { 459 reg = <MT8195_POWER_DOMAIN_MFG2>; 460 #power-domain-cells = <0>; 461 }; 462 463 power-domain@MT8195_POWER_DOMAIN_MFG3 { 464 reg = <MT8195_POWER_DOMAIN_MFG3>; 465 #power-domain-cells = <0>; 466 }; 467 468 power-domain@MT8195_POWER_DOMAIN_MFG4 { 469 reg = <MT8195_POWER_DOMAIN_MFG4>; 470 #power-domain-cells = <0>; 471 }; 472 473 power-domain@MT8195_POWER_DOMAIN_MFG5 { 474 reg = <MT8195_POWER_DOMAIN_MFG5>; 475 #power-domain-cells = <0>; 476 }; 477 478 power-domain@MT8195_POWER_DOMAIN_MFG6 { 479 reg = <MT8195_POWER_DOMAIN_MFG6>; 480 #power-domain-cells = <0>; 481 }; 482 }; 483 }; 484 485 power-domain@MT8195_POWER_DOMAIN_VPPSYS0 { 486 reg = <MT8195_POWER_DOMAIN_VPPSYS0>; 487 clocks = <&topckgen CLK_TOP_VPP>, 488 <&topckgen CLK_TOP_CAM>, 489 <&topckgen CLK_TOP_CCU>, 490 <&topckgen CLK_TOP_IMG>, 491 <&topckgen CLK_TOP_VENC>, 492 <&topckgen CLK_TOP_VDEC>, 493 <&topckgen CLK_TOP_WPE_VPP>, 494 <&topckgen CLK_TOP_CFG_VPP0>, 495 <&vppsys0 CLK_VPP0_SMI_COMMON>, 496 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB0>, 497 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB1>, 498 <&vppsys0 CLK_VPP0_GALS_VENCSYS>, 499 <&vppsys0 CLK_VPP0_GALS_VENCSYS_CORE1>, 500 <&vppsys0 CLK_VPP0_GALS_INFRA>, 501 <&vppsys0 CLK_VPP0_GALS_CAMSYS>, 502 <&vppsys0 CLK_VPP0_GALS_VPP1_LARB5>, 503 <&vppsys0 CLK_VPP0_GALS_VPP1_LARB6>, 504 <&vppsys0 CLK_VPP0_SMI_REORDER>, 505 <&vppsys0 CLK_VPP0_SMI_IOMMU>, 506 <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>, 507 <&vppsys0 CLK_VPP0_GALS_EMI0_EMI1>, 508 <&vppsys0 CLK_VPP0_SMI_SUB_COMMON_REORDER>, 509 <&vppsys0 CLK_VPP0_SMI_RSI>, 510 <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>, 511 <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>, 512 <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>, 513 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>; 514 clock-names = "vppsys", "vppsys1", "vppsys2", "vppsys3", 515 "vppsys4", "vppsys5", "vppsys6", "vppsys7", 516 "vppsys0-0", "vppsys0-1", "vppsys0-2", "vppsys0-3", 517 "vppsys0-4", "vppsys0-5", "vppsys0-6", "vppsys0-7", 518 "vppsys0-8", "vppsys0-9", "vppsys0-10", "vppsys0-11", 519 "vppsys0-12", "vppsys0-13", "vppsys0-14", 520 "vppsys0-15", "vppsys0-16", "vppsys0-17", 521 "vppsys0-18"; 522 mediatek,infracfg = <&infracfg_ao>; 523 #address-cells = <1>; 524 #size-cells = <0>; 525 #power-domain-cells = <1>; 526 527 power-domain@MT8195_POWER_DOMAIN_VDEC1 { 528 reg = <MT8195_POWER_DOMAIN_VDEC1>; 529 clocks = <&vdecsys CLK_VDEC_LARB1>; 530 clock-names = "vdec1-0"; 531 mediatek,infracfg = <&infracfg_ao>; 532 #power-domain-cells = <0>; 533 }; 534 535 power-domain@MT8195_POWER_DOMAIN_VENC_CORE1 { 536 reg = <MT8195_POWER_DOMAIN_VENC_CORE1>; 537 mediatek,infracfg = <&infracfg_ao>; 538 #power-domain-cells = <0>; 539 }; 540 541 power-domain@MT8195_POWER_DOMAIN_VDOSYS0 { 542 reg = <MT8195_POWER_DOMAIN_VDOSYS0>; 543 clocks = <&topckgen CLK_TOP_CFG_VDO0>, 544 <&vdosys0 CLK_VDO0_SMI_GALS>, 545 <&vdosys0 CLK_VDO0_SMI_COMMON>, 546 <&vdosys0 CLK_VDO0_SMI_EMI>, 547 <&vdosys0 CLK_VDO0_SMI_IOMMU>, 548 <&vdosys0 CLK_VDO0_SMI_LARB>, 549 <&vdosys0 CLK_VDO0_SMI_RSI>; 550 clock-names = "vdosys0", "vdosys0-0", "vdosys0-1", 551 "vdosys0-2", "vdosys0-3", 552 "vdosys0-4", "vdosys0-5"; 553 mediatek,infracfg = <&infracfg_ao>; 554 #address-cells = <1>; 555 #size-cells = <0>; 556 #power-domain-cells = <1>; 557 558 power-domain@MT8195_POWER_DOMAIN_VPPSYS1 { 559 reg = <MT8195_POWER_DOMAIN_VPPSYS1>; 560 clocks = <&topckgen CLK_TOP_CFG_VPP1>, 561 <&vppsys1 CLK_VPP1_VPPSYS1_GALS>, 562 <&vppsys1 CLK_VPP1_VPPSYS1_LARB>; 563 clock-names = "vppsys1", "vppsys1-0", 564 "vppsys1-1"; 565 mediatek,infracfg = <&infracfg_ao>; 566 #power-domain-cells = <0>; 567 }; 568 569 power-domain@MT8195_POWER_DOMAIN_WPESYS { 570 reg = <MT8195_POWER_DOMAIN_WPESYS>; 571 clocks = <&wpesys CLK_WPE_SMI_LARB7>, 572 <&wpesys CLK_WPE_SMI_LARB8>, 573 <&wpesys CLK_WPE_SMI_LARB7_P>, 574 <&wpesys CLK_WPE_SMI_LARB8_P>; 575 clock-names = "wepsys-0", "wepsys-1", "wepsys-2", 576 "wepsys-3"; 577 mediatek,infracfg = <&infracfg_ao>; 578 #power-domain-cells = <0>; 579 }; 580 581 power-domain@MT8195_POWER_DOMAIN_VDEC0 { 582 reg = <MT8195_POWER_DOMAIN_VDEC0>; 583 clocks = <&vdecsys_soc CLK_VDEC_SOC_LARB1>; 584 clock-names = "vdec0-0"; 585 mediatek,infracfg = <&infracfg_ao>; 586 #power-domain-cells = <0>; 587 }; 588 589 power-domain@MT8195_POWER_DOMAIN_VDEC2 { 590 reg = <MT8195_POWER_DOMAIN_VDEC2>; 591 clocks = <&vdecsys_core1 CLK_VDEC_CORE1_LARB1>; 592 clock-names = "vdec2-0"; 593 mediatek,infracfg = <&infracfg_ao>; 594 #power-domain-cells = <0>; 595 }; 596 597 power-domain@MT8195_POWER_DOMAIN_VENC { 598 reg = <MT8195_POWER_DOMAIN_VENC>; 599 mediatek,infracfg = <&infracfg_ao>; 600 #power-domain-cells = <0>; 601 }; 602 603 power-domain@MT8195_POWER_DOMAIN_VDOSYS1 { 604 reg = <MT8195_POWER_DOMAIN_VDOSYS1>; 605 clocks = <&topckgen CLK_TOP_CFG_VDO1>, 606 <&vdosys1 CLK_VDO1_SMI_LARB2>, 607 <&vdosys1 CLK_VDO1_SMI_LARB3>, 608 <&vdosys1 CLK_VDO1_GALS>; 609 clock-names = "vdosys1", "vdosys1-0", 610 "vdosys1-1", "vdosys1-2"; 611 mediatek,infracfg = <&infracfg_ao>; 612 #address-cells = <1>; 613 #size-cells = <0>; 614 #power-domain-cells = <1>; 615 616 power-domain@MT8195_POWER_DOMAIN_DP_TX { 617 reg = <MT8195_POWER_DOMAIN_DP_TX>; 618 mediatek,infracfg = <&infracfg_ao>; 619 #power-domain-cells = <0>; 620 }; 621 622 power-domain@MT8195_POWER_DOMAIN_EPD_TX { 623 reg = <MT8195_POWER_DOMAIN_EPD_TX>; 624 mediatek,infracfg = <&infracfg_ao>; 625 #power-domain-cells = <0>; 626 }; 627 628 power-domain@MT8195_POWER_DOMAIN_HDMI_TX { 629 reg = <MT8195_POWER_DOMAIN_HDMI_TX>; 630 clocks = <&topckgen CLK_TOP_HDMI_APB>; 631 clock-names = "hdmi_tx"; 632 #power-domain-cells = <0>; 633 }; 634 }; 635 636 power-domain@MT8195_POWER_DOMAIN_IMG { 637 reg = <MT8195_POWER_DOMAIN_IMG>; 638 clocks = <&imgsys CLK_IMG_LARB9>, 639 <&imgsys CLK_IMG_GALS>; 640 clock-names = "img-0", "img-1"; 641 mediatek,infracfg = <&infracfg_ao>; 642 #address-cells = <1>; 643 #size-cells = <0>; 644 #power-domain-cells = <1>; 645 646 power-domain@MT8195_POWER_DOMAIN_DIP { 647 reg = <MT8195_POWER_DOMAIN_DIP>; 648 #power-domain-cells = <0>; 649 }; 650 651 power-domain@MT8195_POWER_DOMAIN_IPE { 652 reg = <MT8195_POWER_DOMAIN_IPE>; 653 clocks = <&topckgen CLK_TOP_IPE>, 654 <&imgsys CLK_IMG_IPE>, 655 <&ipesys CLK_IPE_SMI_LARB12>; 656 clock-names = "ipe", "ipe-0", "ipe-1"; 657 mediatek,infracfg = <&infracfg_ao>; 658 #power-domain-cells = <0>; 659 }; 660 }; 661 662 power-domain@MT8195_POWER_DOMAIN_CAM { 663 reg = <MT8195_POWER_DOMAIN_CAM>; 664 clocks = <&camsys CLK_CAM_LARB13>, 665 <&camsys CLK_CAM_LARB14>, 666 <&camsys CLK_CAM_CAM2MM0_GALS>, 667 <&camsys CLK_CAM_CAM2MM1_GALS>, 668 <&camsys CLK_CAM_CAM2SYS_GALS>; 669 clock-names = "cam-0", "cam-1", "cam-2", "cam-3", 670 "cam-4"; 671 mediatek,infracfg = <&infracfg_ao>; 672 #address-cells = <1>; 673 #size-cells = <0>; 674 #power-domain-cells = <1>; 675 676 power-domain@MT8195_POWER_DOMAIN_CAM_RAWA { 677 reg = <MT8195_POWER_DOMAIN_CAM_RAWA>; 678 #power-domain-cells = <0>; 679 }; 680 681 power-domain@MT8195_POWER_DOMAIN_CAM_RAWB { 682 reg = <MT8195_POWER_DOMAIN_CAM_RAWB>; 683 #power-domain-cells = <0>; 684 }; 685 686 power-domain@MT8195_POWER_DOMAIN_CAM_MRAW { 687 reg = <MT8195_POWER_DOMAIN_CAM_MRAW>; 688 #power-domain-cells = <0>; 689 }; 690 }; 691 }; 692 }; 693 694 power-domain@MT8195_POWER_DOMAIN_PCIE_MAC_P0 { 695 reg = <MT8195_POWER_DOMAIN_PCIE_MAC_P0>; 696 mediatek,infracfg = <&infracfg_ao>; 697 #power-domain-cells = <0>; 698 }; 699 700 power-domain@MT8195_POWER_DOMAIN_PCIE_MAC_P1 { 701 reg = <MT8195_POWER_DOMAIN_PCIE_MAC_P1>; 702 mediatek,infracfg = <&infracfg_ao>; 703 #power-domain-cells = <0>; 704 }; 705 706 power-domain@MT8195_POWER_DOMAIN_PCIE_PHY { 707 reg = <MT8195_POWER_DOMAIN_PCIE_PHY>; 708 #power-domain-cells = <0>; 709 }; 710 711 power-domain@MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY { 712 reg = <MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY>; 713 #power-domain-cells = <0>; 714 }; 715 716 power-domain@MT8195_POWER_DOMAIN_CSI_RX_TOP { 717 reg = <MT8195_POWER_DOMAIN_CSI_RX_TOP>; 718 clocks = <&topckgen CLK_TOP_SENINF>, 719 <&topckgen CLK_TOP_SENINF2>; 720 clock-names = "csi_rx_top", "csi_rx_top1"; 721 #power-domain-cells = <0>; 722 }; 723 724 power-domain@MT8195_POWER_DOMAIN_ETHER { 725 reg = <MT8195_POWER_DOMAIN_ETHER>; 726 clocks = <&pericfg_ao CLK_PERI_AO_ETHERNET_MAC>; 727 clock-names = "ether"; 728 #power-domain-cells = <0>; 729 }; 730 731 power-domain@MT8195_POWER_DOMAIN_ADSP { 732 reg = <MT8195_POWER_DOMAIN_ADSP>; 733 clocks = <&topckgen CLK_TOP_ADSP>, 734 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>; 735 clock-names = "adsp", "adsp1"; 736 #address-cells = <1>; 737 #size-cells = <0>; 738 mediatek,infracfg = <&infracfg_ao>; 739 #power-domain-cells = <1>; 740 741 power-domain@MT8195_POWER_DOMAIN_AUDIO { 742 reg = <MT8195_POWER_DOMAIN_AUDIO>; 743 clocks = <&topckgen CLK_TOP_A1SYS_HP>, 744 <&topckgen CLK_TOP_AUD_INTBUS>, 745 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>, 746 <&infracfg_ao CLK_INFRA_AO_AUDIO_26M_B>; 747 clock-names = "audio", "audio1", "audio2", 748 "audio3"; 749 mediatek,infracfg = <&infracfg_ao>; 750 #power-domain-cells = <0>; 751 }; 752 }; 753 }; 754 }; 755 756 watchdog: watchdog@10007000 { 757 compatible = "mediatek,mt8195-wdt", 758 "mediatek,mt6589-wdt"; 759 mediatek,disable-extrst; 760 reg = <0 0x10007000 0 0x100>; 761 #reset-cells = <1>; 762 }; 763 764 apmixedsys: syscon@1000c000 { 765 compatible = "mediatek,mt8195-apmixedsys", "syscon"; 766 reg = <0 0x1000c000 0 0x1000>; 767 #clock-cells = <1>; 768 }; 769 770 systimer: timer@10017000 { 771 compatible = "mediatek,mt8195-timer", 772 "mediatek,mt6765-timer"; 773 reg = <0 0x10017000 0 0x1000>; 774 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>; 775 clocks = <&clk13m>; 776 }; 777 778 pwrap: pwrap@10024000 { 779 compatible = "mediatek,mt8195-pwrap", "syscon"; 780 reg = <0 0x10024000 0 0x1000>; 781 reg-names = "pwrap"; 782 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH 0>; 783 clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>, 784 <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>; 785 clock-names = "spi", "wrap"; 786 assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC>; 787 assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>; 788 }; 789 790 spmi: spmi@10027000 { 791 compatible = "mediatek,mt8195-spmi"; 792 reg = <0 0x10027000 0 0x000e00>, 793 <0 0x10029000 0 0x000100>; 794 reg-names = "pmif", "spmimst"; 795 clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>, 796 <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>, 797 <&topckgen CLK_TOP_SPMI_M_MST>; 798 clock-names = "pmif_sys_ck", 799 "pmif_tmr_ck", 800 "spmimst_clk_mux"; 801 assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC>; 802 assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>; 803 }; 804 805 iommu_infra: infra-iommu@10315000 { 806 compatible = "mediatek,mt8195-iommu-infra"; 807 reg = <0 0x10315000 0 0x5000>; 808 interrupts = <GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH 0>, 809 <GIC_SPI 796 IRQ_TYPE_LEVEL_HIGH 0>, 810 <GIC_SPI 797 IRQ_TYPE_LEVEL_HIGH 0>, 811 <GIC_SPI 798 IRQ_TYPE_LEVEL_HIGH 0>, 812 <GIC_SPI 799 IRQ_TYPE_LEVEL_HIGH 0>; 813 #iommu-cells = <1>; 814 }; 815 816 gce0: mailbox@10320000 { 817 compatible = "mediatek,mt8195-gce"; 818 reg = <0 0x10320000 0 0x4000>; 819 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH 0>; 820 #mbox-cells = <2>; 821 clocks = <&infracfg_ao CLK_INFRA_AO_GCE>; 822 }; 823 824 gce1: mailbox@10330000 { 825 compatible = "mediatek,mt8195-gce"; 826 reg = <0 0x10330000 0 0x4000>; 827 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH 0>; 828 #mbox-cells = <2>; 829 clocks = <&infracfg_ao CLK_INFRA_AO_GCE2>; 830 }; 831 832 scp: scp@10500000 { 833 compatible = "mediatek,mt8195-scp"; 834 reg = <0 0x10500000 0 0x100000>, 835 <0 0x10720000 0 0xe0000>, 836 <0 0x10700000 0 0x8000>; 837 reg-names = "sram", "cfg", "l1tcm"; 838 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH 0>; 839 status = "disabled"; 840 }; 841 842 scp_adsp: clock-controller@10720000 { 843 compatible = "mediatek,mt8195-scp_adsp"; 844 reg = <0 0x10720000 0 0x1000>; 845 #clock-cells = <1>; 846 }; 847 848 adsp: dsp@10803000 { 849 compatible = "mediatek,mt8195-dsp"; 850 reg = <0 0x10803000 0 0x1000>, 851 <0 0x10840000 0 0x40000>; 852 reg-names = "cfg", "sram"; 853 clocks = <&topckgen CLK_TOP_ADSP>, 854 <&clk26m>, 855 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>, 856 <&topckgen CLK_TOP_MAINPLL_D7_D2>, 857 <&scp_adsp CLK_SCP_ADSP_AUDIODSP>, 858 <&topckgen CLK_TOP_AUDIO_H>; 859 clock-names = "adsp_sel", 860 "clk26m_ck", 861 "audio_local_bus", 862 "mainpll_d7_d2", 863 "scp_adsp_audiodsp", 864 "audio_h"; 865 power-domains = <&spm MT8195_POWER_DOMAIN_ADSP>; 866 mbox-names = "rx", "tx"; 867 mboxes = <&adsp_mailbox0>, <&adsp_mailbox1>; 868 status = "disabled"; 869 }; 870 871 adsp_mailbox0: mailbox@10816000 { 872 compatible = "mediatek,mt8195-adsp-mbox"; 873 #mbox-cells = <0>; 874 reg = <0 0x10816000 0 0x1000>; 875 interrupts = <GIC_SPI 702 IRQ_TYPE_LEVEL_HIGH 0>; 876 }; 877 878 adsp_mailbox1: mailbox@10817000 { 879 compatible = "mediatek,mt8195-adsp-mbox"; 880 #mbox-cells = <0>; 881 reg = <0 0x10817000 0 0x1000>; 882 interrupts = <GIC_SPI 703 IRQ_TYPE_LEVEL_HIGH 0>; 883 }; 884 885 afe: mt8195-afe-pcm@10890000 { 886 compatible = "mediatek,mt8195-audio"; 887 reg = <0 0x10890000 0 0x10000>; 888 mediatek,topckgen = <&topckgen>; 889 power-domains = <&spm MT8195_POWER_DOMAIN_AUDIO>; 890 interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH 0>; 891 resets = <&watchdog 14>; 892 reset-names = "audiosys"; 893 clocks = <&clk26m>, 894 <&apmixedsys CLK_APMIXED_APLL1>, 895 <&apmixedsys CLK_APMIXED_APLL2>, 896 <&topckgen CLK_TOP_APLL12_DIV0>, 897 <&topckgen CLK_TOP_APLL12_DIV1>, 898 <&topckgen CLK_TOP_APLL12_DIV2>, 899 <&topckgen CLK_TOP_APLL12_DIV3>, 900 <&topckgen CLK_TOP_APLL12_DIV9>, 901 <&topckgen CLK_TOP_A1SYS_HP>, 902 <&topckgen CLK_TOP_AUD_INTBUS>, 903 <&topckgen CLK_TOP_AUDIO_H>, 904 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>, 905 <&topckgen CLK_TOP_DPTX_MCK>, 906 <&topckgen CLK_TOP_I2SO1_MCK>, 907 <&topckgen CLK_TOP_I2SO2_MCK>, 908 <&topckgen CLK_TOP_I2SI1_MCK>, 909 <&topckgen CLK_TOP_I2SI2_MCK>, 910 <&infracfg_ao CLK_INFRA_AO_AUDIO_26M_B>, 911 <&scp_adsp CLK_SCP_ADSP_AUDIODSP>; 912 clock-names = "clk26m", 913 "apll1_ck", 914 "apll2_ck", 915 "apll12_div0", 916 "apll12_div1", 917 "apll12_div2", 918 "apll12_div3", 919 "apll12_div9", 920 "a1sys_hp_sel", 921 "aud_intbus_sel", 922 "audio_h_sel", 923 "audio_local_bus_sel", 924 "dptx_m_sel", 925 "i2so1_m_sel", 926 "i2so2_m_sel", 927 "i2si1_m_sel", 928 "i2si2_m_sel", 929 "infra_ao_audio_26m_b", 930 "scp_adsp_audiodsp"; 931 status = "disabled"; 932 }; 933 934 uart0: serial@11001100 { 935 compatible = "mediatek,mt8195-uart", 936 "mediatek,mt6577-uart"; 937 reg = <0 0x11001100 0 0x100>; 938 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH 0>; 939 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART0>; 940 clock-names = "baud", "bus"; 941 status = "disabled"; 942 }; 943 944 uart1: serial@11001200 { 945 compatible = "mediatek,mt8195-uart", 946 "mediatek,mt6577-uart"; 947 reg = <0 0x11001200 0 0x100>; 948 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH 0>; 949 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART1>; 950 clock-names = "baud", "bus"; 951 status = "disabled"; 952 }; 953 954 uart2: serial@11001300 { 955 compatible = "mediatek,mt8195-uart", 956 "mediatek,mt6577-uart"; 957 reg = <0 0x11001300 0 0x100>; 958 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH 0>; 959 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART2>; 960 clock-names = "baud", "bus"; 961 status = "disabled"; 962 }; 963 964 uart3: serial@11001400 { 965 compatible = "mediatek,mt8195-uart", 966 "mediatek,mt6577-uart"; 967 reg = <0 0x11001400 0 0x100>; 968 interrupts = <GIC_SPI 723 IRQ_TYPE_LEVEL_HIGH 0>; 969 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART3>; 970 clock-names = "baud", "bus"; 971 status = "disabled"; 972 }; 973 974 uart4: serial@11001500 { 975 compatible = "mediatek,mt8195-uart", 976 "mediatek,mt6577-uart"; 977 reg = <0 0x11001500 0 0x100>; 978 interrupts = <GIC_SPI 724 IRQ_TYPE_LEVEL_HIGH 0>; 979 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART4>; 980 clock-names = "baud", "bus"; 981 status = "disabled"; 982 }; 983 984 uart5: serial@11001600 { 985 compatible = "mediatek,mt8195-uart", 986 "mediatek,mt6577-uart"; 987 reg = <0 0x11001600 0 0x100>; 988 interrupts = <GIC_SPI 725 IRQ_TYPE_LEVEL_HIGH 0>; 989 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART5>; 990 clock-names = "baud", "bus"; 991 status = "disabled"; 992 }; 993 994 auxadc: auxadc@11002000 { 995 compatible = "mediatek,mt8195-auxadc", 996 "mediatek,mt8173-auxadc"; 997 reg = <0 0x11002000 0 0x1000>; 998 clocks = <&infracfg_ao CLK_INFRA_AO_AUXADC>; 999 clock-names = "main"; 1000 #io-channel-cells = <1>; 1001 status = "disabled"; 1002 }; 1003 1004 pericfg_ao: syscon@11003000 { 1005 compatible = "mediatek,mt8195-pericfg_ao", "syscon"; 1006 reg = <0 0x11003000 0 0x1000>; 1007 #clock-cells = <1>; 1008 }; 1009 1010 spi0: spi@1100a000 { 1011 compatible = "mediatek,mt8195-spi", 1012 "mediatek,mt6765-spi"; 1013 #address-cells = <1>; 1014 #size-cells = <0>; 1015 reg = <0 0x1100a000 0 0x1000>; 1016 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH 0>; 1017 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 1018 <&topckgen CLK_TOP_SPI>, 1019 <&infracfg_ao CLK_INFRA_AO_SPI0>; 1020 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1021 status = "disabled"; 1022 }; 1023 1024 spi1: spi@11010000 { 1025 compatible = "mediatek,mt8195-spi", 1026 "mediatek,mt6765-spi"; 1027 #address-cells = <1>; 1028 #size-cells = <0>; 1029 reg = <0 0x11010000 0 0x1000>; 1030 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH 0>; 1031 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 1032 <&topckgen CLK_TOP_SPI>, 1033 <&infracfg_ao CLK_INFRA_AO_SPI1>; 1034 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1035 status = "disabled"; 1036 }; 1037 1038 spi2: spi@11012000 { 1039 compatible = "mediatek,mt8195-spi", 1040 "mediatek,mt6765-spi"; 1041 #address-cells = <1>; 1042 #size-cells = <0>; 1043 reg = <0 0x11012000 0 0x1000>; 1044 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH 0>; 1045 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 1046 <&topckgen CLK_TOP_SPI>, 1047 <&infracfg_ao CLK_INFRA_AO_SPI2>; 1048 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1049 status = "disabled"; 1050 }; 1051 1052 spi3: spi@11013000 { 1053 compatible = "mediatek,mt8195-spi", 1054 "mediatek,mt6765-spi"; 1055 #address-cells = <1>; 1056 #size-cells = <0>; 1057 reg = <0 0x11013000 0 0x1000>; 1058 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH 0>; 1059 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 1060 <&topckgen CLK_TOP_SPI>, 1061 <&infracfg_ao CLK_INFRA_AO_SPI3>; 1062 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1063 status = "disabled"; 1064 }; 1065 1066 spi4: spi@11018000 { 1067 compatible = "mediatek,mt8195-spi", 1068 "mediatek,mt6765-spi"; 1069 #address-cells = <1>; 1070 #size-cells = <0>; 1071 reg = <0 0x11018000 0 0x1000>; 1072 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH 0>; 1073 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 1074 <&topckgen CLK_TOP_SPI>, 1075 <&infracfg_ao CLK_INFRA_AO_SPI4>; 1076 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1077 status = "disabled"; 1078 }; 1079 1080 spi5: spi@11019000 { 1081 compatible = "mediatek,mt8195-spi", 1082 "mediatek,mt6765-spi"; 1083 #address-cells = <1>; 1084 #size-cells = <0>; 1085 reg = <0 0x11019000 0 0x1000>; 1086 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH 0>; 1087 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 1088 <&topckgen CLK_TOP_SPI>, 1089 <&infracfg_ao CLK_INFRA_AO_SPI5>; 1090 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1091 status = "disabled"; 1092 }; 1093 1094 spis0: spi@1101d000 { 1095 compatible = "mediatek,mt8195-spi-slave"; 1096 reg = <0 0x1101d000 0 0x1000>; 1097 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH 0>; 1098 clocks = <&infracfg_ao CLK_INFRA_AO_SPIS0>; 1099 clock-names = "spi"; 1100 assigned-clocks = <&topckgen CLK_TOP_SPIS>; 1101 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>; 1102 status = "disabled"; 1103 }; 1104 1105 spis1: spi@1101e000 { 1106 compatible = "mediatek,mt8195-spi-slave"; 1107 reg = <0 0x1101e000 0 0x1000>; 1108 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH 0>; 1109 clocks = <&infracfg_ao CLK_INFRA_AO_SPIS1>; 1110 clock-names = "spi"; 1111 assigned-clocks = <&topckgen CLK_TOP_SPIS>; 1112 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>; 1113 status = "disabled"; 1114 }; 1115 1116 xhci0: usb@11200000 { 1117 compatible = "mediatek,mt8195-xhci", 1118 "mediatek,mtk-xhci"; 1119 reg = <0 0x11200000 0 0x1000>, 1120 <0 0x11203e00 0 0x0100>; 1121 reg-names = "mac", "ippc"; 1122 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH 0>; 1123 phys = <&u2port0 PHY_TYPE_USB2>, 1124 <&u3port0 PHY_TYPE_USB3>; 1125 assigned-clocks = <&topckgen CLK_TOP_USB_TOP>, 1126 <&topckgen CLK_TOP_SSUSB_XHCI>; 1127 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, 1128 <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 1129 clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB>, 1130 <&topckgen CLK_TOP_SSUSB_REF>, 1131 <&apmixedsys CLK_APMIXED_USB1PLL>, 1132 <&clk26m>, 1133 <&infracfg_ao CLK_INFRA_AO_SSUSB_XHCI>; 1134 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", 1135 "xhci_ck"; 1136 mediatek,syscon-wakeup = <&pericfg 0x400 103>; 1137 wakeup-source; 1138 status = "disabled"; 1139 }; 1140 1141 mmc0: mmc@11230000 { 1142 compatible = "mediatek,mt8195-mmc", 1143 "mediatek,mt8183-mmc"; 1144 reg = <0 0x11230000 0 0x10000>, 1145 <0 0x11f50000 0 0x1000>; 1146 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>; 1147 clocks = <&topckgen CLK_TOP_MSDC50_0>, 1148 <&infracfg_ao CLK_INFRA_AO_MSDC0>, 1149 <&infracfg_ao CLK_INFRA_AO_MSDC0_SRC>; 1150 clock-names = "source", "hclk", "source_cg"; 1151 status = "disabled"; 1152 }; 1153 1154 mmc1: mmc@11240000 { 1155 compatible = "mediatek,mt8195-mmc", 1156 "mediatek,mt8183-mmc"; 1157 reg = <0 0x11240000 0 0x1000>, 1158 <0 0x11c70000 0 0x1000>; 1159 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH 0>; 1160 clocks = <&topckgen CLK_TOP_MSDC30_1>, 1161 <&infracfg_ao CLK_INFRA_AO_MSDC1>, 1162 <&infracfg_ao CLK_INFRA_AO_MSDC1_SRC>; 1163 clock-names = "source", "hclk", "source_cg"; 1164 assigned-clocks = <&topckgen CLK_TOP_MSDC30_1>; 1165 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>; 1166 status = "disabled"; 1167 }; 1168 1169 mmc2: mmc@11250000 { 1170 compatible = "mediatek,mt8195-mmc", 1171 "mediatek,mt8183-mmc"; 1172 reg = <0 0x11250000 0 0x1000>, 1173 <0 0x11e60000 0 0x1000>; 1174 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH 0>; 1175 clocks = <&topckgen CLK_TOP_MSDC30_2>, 1176 <&infracfg_ao CLK_INFRA_AO_CG1_MSDC2>, 1177 <&infracfg_ao CLK_INFRA_AO_CG3_MSDC2>; 1178 clock-names = "source", "hclk", "source_cg"; 1179 assigned-clocks = <&topckgen CLK_TOP_MSDC30_2>; 1180 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>; 1181 status = "disabled"; 1182 }; 1183 1184 xhci1: usb@11290000 { 1185 compatible = "mediatek,mt8195-xhci", 1186 "mediatek,mtk-xhci"; 1187 reg = <0 0x11290000 0 0x1000>, 1188 <0 0x11293e00 0 0x0100>; 1189 reg-names = "mac", "ippc"; 1190 interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH 0>; 1191 phys = <&u2port1 PHY_TYPE_USB2>; 1192 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_1P>, 1193 <&topckgen CLK_TOP_SSUSB_XHCI_1P>; 1194 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, 1195 <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 1196 clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_1P_BUS>, 1197 <&topckgen CLK_TOP_SSUSB_P1_REF>, 1198 <&apmixedsys CLK_APMIXED_USB1PLL>, 1199 <&clk26m>, 1200 <&pericfg_ao CLK_PERI_AO_SSUSB_1P_XHCI>; 1201 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", 1202 "xhci_ck"; 1203 mediatek,syscon-wakeup = <&pericfg 0x400 104>; 1204 wakeup-source; 1205 status = "disabled"; 1206 }; 1207 1208 xhci2: usb@112a0000 { 1209 compatible = "mediatek,mt8195-xhci", 1210 "mediatek,mtk-xhci"; 1211 reg = <0 0x112a0000 0 0x1000>, 1212 <0 0x112a3e00 0 0x0100>; 1213 reg-names = "mac", "ippc"; 1214 interrupts = <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH 0>; 1215 phys = <&u2port2 PHY_TYPE_USB2>; 1216 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_2P>, 1217 <&topckgen CLK_TOP_SSUSB_XHCI_2P>; 1218 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, 1219 <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 1220 clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_2P_BUS>, 1221 <&topckgen CLK_TOP_SSUSB_P2_REF>, 1222 <&clk26m>, 1223 <&clk26m>, 1224 <&pericfg_ao CLK_PERI_AO_SSUSB_2P_XHCI>; 1225 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", 1226 "xhci_ck"; 1227 mediatek,syscon-wakeup = <&pericfg 0x400 105>; 1228 wakeup-source; 1229 status = "disabled"; 1230 }; 1231 1232 xhci3: usb@112b0000 { 1233 compatible = "mediatek,mt8195-xhci", 1234 "mediatek,mtk-xhci"; 1235 reg = <0 0x112b0000 0 0x1000>, 1236 <0 0x112b3e00 0 0x0100>; 1237 reg-names = "mac", "ippc"; 1238 interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH 0>; 1239 phys = <&u2port3 PHY_TYPE_USB2>; 1240 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_3P>, 1241 <&topckgen CLK_TOP_SSUSB_XHCI_3P>; 1242 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, 1243 <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 1244 clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_3P_BUS>, 1245 <&topckgen CLK_TOP_SSUSB_P3_REF>, 1246 <&clk26m>, 1247 <&clk26m>, 1248 <&pericfg_ao CLK_PERI_AO_SSUSB_3P_XHCI>; 1249 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", 1250 "xhci_ck"; 1251 mediatek,syscon-wakeup = <&pericfg 0x400 106>; 1252 wakeup-source; 1253 status = "disabled"; 1254 }; 1255 1256 pcie0: pcie@112f0000 { 1257 compatible = "mediatek,mt8195-pcie", 1258 "mediatek,mt8192-pcie"; 1259 device_type = "pci"; 1260 #address-cells = <3>; 1261 #size-cells = <2>; 1262 reg = <0 0x112f0000 0 0x4000>; 1263 reg-names = "pcie-mac"; 1264 interrupts = <GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH 0>; 1265 bus-range = <0x00 0xff>; 1266 ranges = <0x81000000 0 0x20000000 1267 0x0 0x20000000 0 0x200000>, 1268 <0x82000000 0 0x20200000 1269 0x0 0x20200000 0 0x3e00000>; 1270 1271 iommu-map = <0 &iommu_infra IOMMU_PORT_INFRA_PCIE0 0x2>; 1272 iommu-map-mask = <0x0>; 1273 1274 clocks = <&infracfg_ao CLK_INFRA_AO_PCIE_PL_P_250M_P0>, 1275 <&infracfg_ao CLK_INFRA_AO_PCIE_TL_26M>, 1276 <&infracfg_ao CLK_INFRA_AO_PCIE_TL_96M>, 1277 <&infracfg_ao CLK_INFRA_AO_PCIE_TL_32K>, 1278 <&infracfg_ao CLK_INFRA_AO_PCIE_PERI_26M>, 1279 <&pericfg_ao CLK_PERI_AO_PCIE_P0_MEM>; 1280 clock-names = "pl_250m", "tl_26m", "tl_96m", 1281 "tl_32k", "peri_26m", "peri_mem"; 1282 assigned-clocks = <&topckgen CLK_TOP_TL>; 1283 assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4_D4>; 1284 1285 phys = <&pciephy>; 1286 phy-names = "pcie-phy"; 1287 1288 power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_MAC_P0>; 1289 1290 resets = <&infracfg_ao MT8195_INFRA_RST2_PCIE_P0_SWRST>; 1291 reset-names = "mac"; 1292 1293 #interrupt-cells = <1>; 1294 interrupt-map-mask = <0 0 0 7>; 1295 interrupt-map = <0 0 0 1 &pcie_intc0 0>, 1296 <0 0 0 2 &pcie_intc0 1>, 1297 <0 0 0 3 &pcie_intc0 2>, 1298 <0 0 0 4 &pcie_intc0 3>; 1299 status = "disabled"; 1300 1301 pcie_intc0: interrupt-controller { 1302 interrupt-controller; 1303 #address-cells = <0>; 1304 #interrupt-cells = <1>; 1305 }; 1306 }; 1307 1308 pcie1: pcie@112f8000 { 1309 compatible = "mediatek,mt8195-pcie", 1310 "mediatek,mt8192-pcie"; 1311 device_type = "pci"; 1312 #address-cells = <3>; 1313 #size-cells = <2>; 1314 reg = <0 0x112f8000 0 0x4000>; 1315 reg-names = "pcie-mac"; 1316 interrupts = <GIC_SPI 792 IRQ_TYPE_LEVEL_HIGH 0>; 1317 bus-range = <0x00 0xff>; 1318 ranges = <0x81000000 0 0x24000000 1319 0x0 0x24000000 0 0x200000>, 1320 <0x82000000 0 0x24200000 1321 0x0 0x24200000 0 0x3e00000>; 1322 1323 iommu-map = <0 &iommu_infra IOMMU_PORT_INFRA_PCIE1 0x2>; 1324 iommu-map-mask = <0x0>; 1325 1326 clocks = <&infracfg_ao CLK_INFRA_AO_PCIE_PL_P_250M_P1>, 1327 <&clk26m>, 1328 <&infracfg_ao CLK_INFRA_AO_PCIE_P1_TL_96M>, 1329 <&clk26m>, 1330 <&infracfg_ao CLK_INFRA_AO_PCIE_P1_PERI_26M>, 1331 /* Designer has connect pcie1 with peri_mem_p0 clock */ 1332 <&pericfg_ao CLK_PERI_AO_PCIE_P0_MEM>; 1333 clock-names = "pl_250m", "tl_26m", "tl_96m", 1334 "tl_32k", "peri_26m", "peri_mem"; 1335 assigned-clocks = <&topckgen CLK_TOP_TL_P1>; 1336 assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4_D4>; 1337 1338 phys = <&u3port1 PHY_TYPE_PCIE>; 1339 phy-names = "pcie-phy"; 1340 power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_MAC_P1>; 1341 1342 resets = <&infracfg_ao MT8195_INFRA_RST2_PCIE_P1_SWRST>; 1343 reset-names = "mac"; 1344 1345 #interrupt-cells = <1>; 1346 interrupt-map-mask = <0 0 0 7>; 1347 interrupt-map = <0 0 0 1 &pcie_intc1 0>, 1348 <0 0 0 2 &pcie_intc1 1>, 1349 <0 0 0 3 &pcie_intc1 2>, 1350 <0 0 0 4 &pcie_intc1 3>; 1351 status = "disabled"; 1352 1353 pcie_intc1: interrupt-controller { 1354 interrupt-controller; 1355 #address-cells = <0>; 1356 #interrupt-cells = <1>; 1357 }; 1358 }; 1359 1360 nor_flash: spi@1132c000 { 1361 compatible = "mediatek,mt8195-nor", 1362 "mediatek,mt8173-nor"; 1363 reg = <0 0x1132c000 0 0x1000>; 1364 interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH 0>; 1365 clocks = <&topckgen CLK_TOP_SPINOR>, 1366 <&pericfg_ao CLK_PERI_AO_FLASHIF_FLASH>, 1367 <&pericfg_ao CLK_PERI_AO_FLASHIF_BUS>; 1368 clock-names = "spi", "sf", "axi"; 1369 #address-cells = <1>; 1370 #size-cells = <0>; 1371 status = "disabled"; 1372 }; 1373 1374 efuse: efuse@11c10000 { 1375 compatible = "mediatek,mt8195-efuse", "mediatek,efuse"; 1376 reg = <0 0x11c10000 0 0x1000>; 1377 #address-cells = <1>; 1378 #size-cells = <1>; 1379 u3_tx_imp_p0: usb3-tx-imp@184,1 { 1380 reg = <0x184 0x1>; 1381 bits = <0 5>; 1382 }; 1383 u3_rx_imp_p0: usb3-rx-imp@184,2 { 1384 reg = <0x184 0x2>; 1385 bits = <5 5>; 1386 }; 1387 u3_intr_p0: usb3-intr@185 { 1388 reg = <0x185 0x1>; 1389 bits = <2 6>; 1390 }; 1391 comb_tx_imp_p1: usb3-tx-imp@186,1 { 1392 reg = <0x186 0x1>; 1393 bits = <0 5>; 1394 }; 1395 comb_rx_imp_p1: usb3-rx-imp@186,2 { 1396 reg = <0x186 0x2>; 1397 bits = <5 5>; 1398 }; 1399 comb_intr_p1: usb3-intr@187 { 1400 reg = <0x187 0x1>; 1401 bits = <2 6>; 1402 }; 1403 u2_intr_p0: usb2-intr-p0@188,1 { 1404 reg = <0x188 0x1>; 1405 bits = <0 5>; 1406 }; 1407 u2_intr_p1: usb2-intr-p1@188,2 { 1408 reg = <0x188 0x2>; 1409 bits = <5 5>; 1410 }; 1411 u2_intr_p2: usb2-intr-p2@189,1 { 1412 reg = <0x189 0x1>; 1413 bits = <2 5>; 1414 }; 1415 u2_intr_p3: usb2-intr-p3@189,2 { 1416 reg = <0x189 0x2>; 1417 bits = <7 5>; 1418 }; 1419 pciephy_rx_ln1: pciephy-rx-ln1@190,1 { 1420 reg = <0x190 0x1>; 1421 bits = <0 4>; 1422 }; 1423 pciephy_tx_ln1_nmos: pciephy-tx-ln1-nmos@190,2 { 1424 reg = <0x190 0x1>; 1425 bits = <4 4>; 1426 }; 1427 pciephy_tx_ln1_pmos: pciephy-tx-ln1-pmos@191,1 { 1428 reg = <0x191 0x1>; 1429 bits = <0 4>; 1430 }; 1431 pciephy_rx_ln0: pciephy-rx-ln0@191,2 { 1432 reg = <0x191 0x1>; 1433 bits = <4 4>; 1434 }; 1435 pciephy_tx_ln0_nmos: pciephy-tx-ln0-nmos@192,1 { 1436 reg = <0x192 0x1>; 1437 bits = <0 4>; 1438 }; 1439 pciephy_tx_ln0_pmos: pciephy-tx-ln0-pmos@192,2 { 1440 reg = <0x192 0x1>; 1441 bits = <4 4>; 1442 }; 1443 pciephy_glb_intr: pciephy-glb-intr@193 { 1444 reg = <0x193 0x1>; 1445 bits = <0 4>; 1446 }; 1447 dp_calibration: dp-data@1ac { 1448 reg = <0x1ac 0x10>; 1449 }; 1450 }; 1451 1452 u3phy2: t-phy@11c40000 { 1453 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3"; 1454 #address-cells = <1>; 1455 #size-cells = <1>; 1456 ranges = <0 0 0x11c40000 0x700>; 1457 status = "disabled"; 1458 1459 u2port2: usb-phy@0 { 1460 reg = <0x0 0x700>; 1461 clocks = <&topckgen CLK_TOP_SSUSB_PHY_P2_REF>; 1462 clock-names = "ref"; 1463 #phy-cells = <1>; 1464 }; 1465 }; 1466 1467 u3phy3: t-phy@11c50000 { 1468 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3"; 1469 #address-cells = <1>; 1470 #size-cells = <1>; 1471 ranges = <0 0 0x11c50000 0x700>; 1472 status = "disabled"; 1473 1474 u2port3: usb-phy@0 { 1475 reg = <0x0 0x700>; 1476 clocks = <&topckgen CLK_TOP_SSUSB_PHY_P3_REF>; 1477 clock-names = "ref"; 1478 #phy-cells = <1>; 1479 }; 1480 }; 1481 1482 i2c5: i2c@11d00000 { 1483 compatible = "mediatek,mt8195-i2c", 1484 "mediatek,mt8192-i2c"; 1485 reg = <0 0x11d00000 0 0x1000>, 1486 <0 0x10220580 0 0x80>; 1487 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH 0>; 1488 clock-div = <1>; 1489 clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C5>, 1490 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1491 clock-names = "main", "dma"; 1492 #address-cells = <1>; 1493 #size-cells = <0>; 1494 status = "disabled"; 1495 }; 1496 1497 i2c6: i2c@11d01000 { 1498 compatible = "mediatek,mt8195-i2c", 1499 "mediatek,mt8192-i2c"; 1500 reg = <0 0x11d01000 0 0x1000>, 1501 <0 0x10220600 0 0x80>; 1502 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH 0>; 1503 clock-div = <1>; 1504 clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C6>, 1505 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1506 clock-names = "main", "dma"; 1507 #address-cells = <1>; 1508 #size-cells = <0>; 1509 status = "disabled"; 1510 }; 1511 1512 i2c7: i2c@11d02000 { 1513 compatible = "mediatek,mt8195-i2c", 1514 "mediatek,mt8192-i2c"; 1515 reg = <0 0x11d02000 0 0x1000>, 1516 <0 0x10220680 0 0x80>; 1517 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>; 1518 clock-div = <1>; 1519 clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C7>, 1520 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1521 clock-names = "main", "dma"; 1522 #address-cells = <1>; 1523 #size-cells = <0>; 1524 status = "disabled"; 1525 }; 1526 1527 imp_iic_wrap_s: clock-controller@11d03000 { 1528 compatible = "mediatek,mt8195-imp_iic_wrap_s"; 1529 reg = <0 0x11d03000 0 0x1000>; 1530 #clock-cells = <1>; 1531 }; 1532 1533 i2c0: i2c@11e00000 { 1534 compatible = "mediatek,mt8195-i2c", 1535 "mediatek,mt8192-i2c"; 1536 reg = <0 0x11e00000 0 0x1000>, 1537 <0 0x10220080 0 0x80>; 1538 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH 0>; 1539 clock-div = <1>; 1540 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C0>, 1541 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1542 clock-names = "main", "dma"; 1543 #address-cells = <1>; 1544 #size-cells = <0>; 1545 status = "disabled"; 1546 }; 1547 1548 i2c1: i2c@11e01000 { 1549 compatible = "mediatek,mt8195-i2c", 1550 "mediatek,mt8192-i2c"; 1551 reg = <0 0x11e01000 0 0x1000>, 1552 <0 0x10220200 0 0x80>; 1553 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH 0>; 1554 clock-div = <1>; 1555 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C1>, 1556 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1557 clock-names = "main", "dma"; 1558 #address-cells = <1>; 1559 #size-cells = <0>; 1560 status = "disabled"; 1561 }; 1562 1563 i2c2: i2c@11e02000 { 1564 compatible = "mediatek,mt8195-i2c", 1565 "mediatek,mt8192-i2c"; 1566 reg = <0 0x11e02000 0 0x1000>, 1567 <0 0x10220380 0 0x80>; 1568 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH 0>; 1569 clock-div = <1>; 1570 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C2>, 1571 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1572 clock-names = "main", "dma"; 1573 #address-cells = <1>; 1574 #size-cells = <0>; 1575 status = "disabled"; 1576 }; 1577 1578 i2c3: i2c@11e03000 { 1579 compatible = "mediatek,mt8195-i2c", 1580 "mediatek,mt8192-i2c"; 1581 reg = <0 0x11e03000 0 0x1000>, 1582 <0 0x10220480 0 0x80>; 1583 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH 0>; 1584 clock-div = <1>; 1585 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C3>, 1586 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1587 clock-names = "main", "dma"; 1588 #address-cells = <1>; 1589 #size-cells = <0>; 1590 status = "disabled"; 1591 }; 1592 1593 i2c4: i2c@11e04000 { 1594 compatible = "mediatek,mt8195-i2c", 1595 "mediatek,mt8192-i2c"; 1596 reg = <0 0x11e04000 0 0x1000>, 1597 <0 0x10220500 0 0x80>; 1598 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH 0>; 1599 clock-div = <1>; 1600 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C4>, 1601 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1602 clock-names = "main", "dma"; 1603 #address-cells = <1>; 1604 #size-cells = <0>; 1605 status = "disabled"; 1606 }; 1607 1608 imp_iic_wrap_w: clock-controller@11e05000 { 1609 compatible = "mediatek,mt8195-imp_iic_wrap_w"; 1610 reg = <0 0x11e05000 0 0x1000>; 1611 #clock-cells = <1>; 1612 }; 1613 1614 u3phy1: t-phy@11e30000 { 1615 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3"; 1616 #address-cells = <1>; 1617 #size-cells = <1>; 1618 ranges = <0 0 0x11e30000 0xe00>; 1619 power-domains = <&spm MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY>; 1620 status = "disabled"; 1621 1622 u2port1: usb-phy@0 { 1623 reg = <0x0 0x700>; 1624 clocks = <&topckgen CLK_TOP_SSUSB_PHY_P1_REF>, 1625 <&clk26m>; 1626 clock-names = "ref", "da_ref"; 1627 #phy-cells = <1>; 1628 }; 1629 1630 u3port1: usb-phy@700 { 1631 reg = <0x700 0x700>; 1632 clocks = <&apmixedsys CLK_APMIXED_PLL_SSUSB26M>, 1633 <&topckgen CLK_TOP_SSUSB_PHY_P1_REF>; 1634 clock-names = "ref", "da_ref"; 1635 nvmem-cells = <&comb_intr_p1>, 1636 <&comb_rx_imp_p1>, 1637 <&comb_tx_imp_p1>; 1638 nvmem-cell-names = "intr", "rx_imp", "tx_imp"; 1639 #phy-cells = <1>; 1640 }; 1641 }; 1642 1643 u3phy0: t-phy@11e40000 { 1644 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3"; 1645 #address-cells = <1>; 1646 #size-cells = <1>; 1647 ranges = <0 0 0x11e40000 0xe00>; 1648 status = "disabled"; 1649 1650 u2port0: usb-phy@0 { 1651 reg = <0x0 0x700>; 1652 clocks = <&topckgen CLK_TOP_SSUSB_PHY_REF>, 1653 <&clk26m>; 1654 clock-names = "ref", "da_ref"; 1655 #phy-cells = <1>; 1656 }; 1657 1658 u3port0: usb-phy@700 { 1659 reg = <0x700 0x700>; 1660 clocks = <&apmixedsys CLK_APMIXED_PLL_SSUSB26M>, 1661 <&topckgen CLK_TOP_SSUSB_PHY_REF>; 1662 clock-names = "ref", "da_ref"; 1663 nvmem-cells = <&u3_intr_p0>, 1664 <&u3_rx_imp_p0>, 1665 <&u3_tx_imp_p0>; 1666 nvmem-cell-names = "intr", "rx_imp", "tx_imp"; 1667 #phy-cells = <1>; 1668 }; 1669 }; 1670 1671 pciephy: phy@11e80000 { 1672 compatible = "mediatek,mt8195-pcie-phy"; 1673 reg = <0 0x11e80000 0 0x10000>; 1674 reg-names = "sif"; 1675 nvmem-cells = <&pciephy_glb_intr>, <&pciephy_tx_ln0_pmos>, 1676 <&pciephy_tx_ln0_nmos>, <&pciephy_rx_ln0>, 1677 <&pciephy_tx_ln1_pmos>, <&pciephy_tx_ln1_nmos>, 1678 <&pciephy_rx_ln1>; 1679 nvmem-cell-names = "glb_intr", "tx_ln0_pmos", 1680 "tx_ln0_nmos", "rx_ln0", 1681 "tx_ln1_pmos", "tx_ln1_nmos", 1682 "rx_ln1"; 1683 power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_PHY>; 1684 #phy-cells = <0>; 1685 status = "disabled"; 1686 }; 1687 1688 ufsphy: ufs-phy@11fa0000 { 1689 compatible = "mediatek,mt8195-ufsphy", "mediatek,mt8183-ufsphy"; 1690 reg = <0 0x11fa0000 0 0xc000>; 1691 clocks = <&clk26m>, <&clk26m>; 1692 clock-names = "unipro", "mp"; 1693 #phy-cells = <0>; 1694 status = "disabled"; 1695 }; 1696 1697 mfgcfg: clock-controller@13fbf000 { 1698 compatible = "mediatek,mt8195-mfgcfg"; 1699 reg = <0 0x13fbf000 0 0x1000>; 1700 #clock-cells = <1>; 1701 }; 1702 1703 vppsys0: clock-controller@14000000 { 1704 compatible = "mediatek,mt8195-vppsys0"; 1705 reg = <0 0x14000000 0 0x1000>; 1706 #clock-cells = <1>; 1707 }; 1708 1709 smi_sub_common_vpp0_vpp1_2x1: smi@14010000 { 1710 compatible = "mediatek,mt8195-smi-sub-common"; 1711 reg = <0 0x14010000 0 0x1000>; 1712 clocks = <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>, 1713 <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>, 1714 <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>; 1715 clock-names = "apb", "smi", "gals0"; 1716 mediatek,smi = <&smi_common_vpp>; 1717 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; 1718 }; 1719 1720 smi_sub_common_vdec_vpp0_2x1: smi@14011000 { 1721 compatible = "mediatek,mt8195-smi-sub-common"; 1722 reg = <0 0x14011000 0 0x1000>; 1723 clocks = <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>, 1724 <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>, 1725 <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>; 1726 clock-names = "apb", "smi", "gals0"; 1727 mediatek,smi = <&smi_common_vpp>; 1728 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; 1729 }; 1730 1731 smi_common_vpp: smi@14012000 { 1732 compatible = "mediatek,mt8195-smi-common-vpp"; 1733 reg = <0 0x14012000 0 0x1000>; 1734 clocks = <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>, 1735 <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>, 1736 <&vppsys0 CLK_VPP0_SMI_RSI>, 1737 <&vppsys0 CLK_VPP0_SMI_RSI>; 1738 clock-names = "apb", "smi", "gals0", "gals1"; 1739 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; 1740 }; 1741 1742 larb4: larb@14013000 { 1743 compatible = "mediatek,mt8195-smi-larb"; 1744 reg = <0 0x14013000 0 0x1000>; 1745 mediatek,larb-id = <4>; 1746 mediatek,smi = <&smi_sub_common_vpp0_vpp1_2x1>; 1747 clocks = <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>, 1748 <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>; 1749 clock-names = "apb", "smi"; 1750 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; 1751 }; 1752 1753 iommu_vpp: iommu@14018000 { 1754 compatible = "mediatek,mt8195-iommu-vpp"; 1755 reg = <0 0x14018000 0 0x1000>; 1756 mediatek,larbs = <&larb1 &larb3 &larb4 &larb6 &larb8 1757 &larb12 &larb14 &larb16 &larb18 1758 &larb20 &larb22 &larb23 &larb26 1759 &larb27>; 1760 interrupts = <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH 0>; 1761 clocks = <&vppsys0 CLK_VPP0_SMI_IOMMU>; 1762 clock-names = "bclk"; 1763 #iommu-cells = <1>; 1764 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; 1765 }; 1766 1767 wpesys: clock-controller@14e00000 { 1768 compatible = "mediatek,mt8195-wpesys"; 1769 reg = <0 0x14e00000 0 0x1000>; 1770 #clock-cells = <1>; 1771 }; 1772 1773 wpesys_vpp0: clock-controller@14e02000 { 1774 compatible = "mediatek,mt8195-wpesys_vpp0"; 1775 reg = <0 0x14e02000 0 0x1000>; 1776 #clock-cells = <1>; 1777 }; 1778 1779 wpesys_vpp1: clock-controller@14e03000 { 1780 compatible = "mediatek,mt8195-wpesys_vpp1"; 1781 reg = <0 0x14e03000 0 0x1000>; 1782 #clock-cells = <1>; 1783 }; 1784 1785 larb7: larb@14e04000 { 1786 compatible = "mediatek,mt8195-smi-larb"; 1787 reg = <0 0x14e04000 0 0x1000>; 1788 mediatek,larb-id = <7>; 1789 mediatek,smi = <&smi_common_vdo>; 1790 clocks = <&wpesys CLK_WPE_SMI_LARB7>, 1791 <&wpesys CLK_WPE_SMI_LARB7>; 1792 clock-names = "apb", "smi"; 1793 power-domains = <&spm MT8195_POWER_DOMAIN_WPESYS>; 1794 }; 1795 1796 larb8: larb@14e05000 { 1797 compatible = "mediatek,mt8195-smi-larb"; 1798 reg = <0 0x14e05000 0 0x1000>; 1799 mediatek,larb-id = <8>; 1800 mediatek,smi = <&smi_common_vpp>; 1801 clocks = <&wpesys CLK_WPE_SMI_LARB8>, 1802 <&wpesys CLK_WPE_SMI_LARB8>, 1803 <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>; 1804 clock-names = "apb", "smi", "gals"; 1805 power-domains = <&spm MT8195_POWER_DOMAIN_WPESYS>; 1806 }; 1807 1808 vppsys1: clock-controller@14f00000 { 1809 compatible = "mediatek,mt8195-vppsys1"; 1810 reg = <0 0x14f00000 0 0x1000>; 1811 #clock-cells = <1>; 1812 }; 1813 1814 larb5: larb@14f02000 { 1815 compatible = "mediatek,mt8195-smi-larb"; 1816 reg = <0 0x14f02000 0 0x1000>; 1817 mediatek,larb-id = <5>; 1818 mediatek,smi = <&smi_common_vdo>; 1819 clocks = <&vppsys1 CLK_VPP1_VPPSYS1_LARB>, 1820 <&vppsys1 CLK_VPP1_VPPSYS1_GALS>, 1821 <&vppsys0 CLK_VPP0_GALS_VPP1_LARB5>; 1822 clock-names = "apb", "smi", "gals"; 1823 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 1824 }; 1825 1826 larb6: larb@14f03000 { 1827 compatible = "mediatek,mt8195-smi-larb"; 1828 reg = <0 0x14f03000 0 0x1000>; 1829 mediatek,larb-id = <6>; 1830 mediatek,smi = <&smi_sub_common_vpp0_vpp1_2x1>; 1831 clocks = <&vppsys1 CLK_VPP1_VPPSYS1_LARB>, 1832 <&vppsys1 CLK_VPP1_VPPSYS1_GALS>, 1833 <&vppsys0 CLK_VPP0_GALS_VPP1_LARB6>; 1834 clock-names = "apb", "smi", "gals"; 1835 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 1836 }; 1837 1838 imgsys: clock-controller@15000000 { 1839 compatible = "mediatek,mt8195-imgsys"; 1840 reg = <0 0x15000000 0 0x1000>; 1841 #clock-cells = <1>; 1842 }; 1843 1844 larb9: larb@15001000 { 1845 compatible = "mediatek,mt8195-smi-larb"; 1846 reg = <0 0x15001000 0 0x1000>; 1847 mediatek,larb-id = <9>; 1848 mediatek,smi = <&smi_sub_common_img1_3x1>; 1849 clocks = <&imgsys CLK_IMG_LARB9>, 1850 <&imgsys CLK_IMG_LARB9>, 1851 <&imgsys CLK_IMG_GALS>; 1852 clock-names = "apb", "smi", "gals"; 1853 power-domains = <&spm MT8195_POWER_DOMAIN_IMG>; 1854 }; 1855 1856 smi_sub_common_img0_3x1: smi@15002000 { 1857 compatible = "mediatek,mt8195-smi-sub-common"; 1858 reg = <0 0x15002000 0 0x1000>; 1859 clocks = <&imgsys CLK_IMG_IPE>, 1860 <&imgsys CLK_IMG_IPE>, 1861 <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>; 1862 clock-names = "apb", "smi", "gals0"; 1863 mediatek,smi = <&smi_common_vpp>; 1864 power-domains = <&spm MT8195_POWER_DOMAIN_IMG>; 1865 }; 1866 1867 smi_sub_common_img1_3x1: smi@15003000 { 1868 compatible = "mediatek,mt8195-smi-sub-common"; 1869 reg = <0 0x15003000 0 0x1000>; 1870 clocks = <&imgsys CLK_IMG_LARB9>, 1871 <&imgsys CLK_IMG_LARB9>, 1872 <&imgsys CLK_IMG_GALS>; 1873 clock-names = "apb", "smi", "gals0"; 1874 mediatek,smi = <&smi_common_vdo>; 1875 power-domains = <&spm MT8195_POWER_DOMAIN_IMG>; 1876 }; 1877 1878 imgsys1_dip_top: clock-controller@15110000 { 1879 compatible = "mediatek,mt8195-imgsys1_dip_top"; 1880 reg = <0 0x15110000 0 0x1000>; 1881 #clock-cells = <1>; 1882 }; 1883 1884 larb10: larb@15120000 { 1885 compatible = "mediatek,mt8195-smi-larb"; 1886 reg = <0 0x15120000 0 0x1000>; 1887 mediatek,larb-id = <10>; 1888 mediatek,smi = <&smi_sub_common_img1_3x1>; 1889 clocks = <&imgsys CLK_IMG_DIP0>, 1890 <&imgsys1_dip_top CLK_IMG1_DIP_TOP_LARB10>; 1891 clock-names = "apb", "smi"; 1892 power-domains = <&spm MT8195_POWER_DOMAIN_DIP>; 1893 }; 1894 1895 imgsys1_dip_nr: clock-controller@15130000 { 1896 compatible = "mediatek,mt8195-imgsys1_dip_nr"; 1897 reg = <0 0x15130000 0 0x1000>; 1898 #clock-cells = <1>; 1899 }; 1900 1901 imgsys1_wpe: clock-controller@15220000 { 1902 compatible = "mediatek,mt8195-imgsys1_wpe"; 1903 reg = <0 0x15220000 0 0x1000>; 1904 #clock-cells = <1>; 1905 }; 1906 1907 larb11: larb@15230000 { 1908 compatible = "mediatek,mt8195-smi-larb"; 1909 reg = <0 0x15230000 0 0x1000>; 1910 mediatek,larb-id = <11>; 1911 mediatek,smi = <&smi_sub_common_img1_3x1>; 1912 clocks = <&imgsys CLK_IMG_WPE0>, 1913 <&imgsys1_wpe CLK_IMG1_WPE_LARB11>; 1914 clock-names = "apb", "smi"; 1915 power-domains = <&spm MT8195_POWER_DOMAIN_DIP>; 1916 }; 1917 1918 ipesys: clock-controller@15330000 { 1919 compatible = "mediatek,mt8195-ipesys"; 1920 reg = <0 0x15330000 0 0x1000>; 1921 #clock-cells = <1>; 1922 }; 1923 1924 larb12: larb@15340000 { 1925 compatible = "mediatek,mt8195-smi-larb"; 1926 reg = <0 0x15340000 0 0x1000>; 1927 mediatek,larb-id = <12>; 1928 mediatek,smi = <&smi_sub_common_img0_3x1>; 1929 clocks = <&ipesys CLK_IPE_SMI_LARB12>, 1930 <&ipesys CLK_IPE_SMI_LARB12>; 1931 clock-names = "apb", "smi"; 1932 power-domains = <&spm MT8195_POWER_DOMAIN_IPE>; 1933 }; 1934 1935 camsys: clock-controller@16000000 { 1936 compatible = "mediatek,mt8195-camsys"; 1937 reg = <0 0x16000000 0 0x1000>; 1938 #clock-cells = <1>; 1939 }; 1940 1941 larb13: larb@16001000 { 1942 compatible = "mediatek,mt8195-smi-larb"; 1943 reg = <0 0x16001000 0 0x1000>; 1944 mediatek,larb-id = <13>; 1945 mediatek,smi = <&smi_sub_common_cam_4x1>; 1946 clocks = <&camsys CLK_CAM_LARB13>, 1947 <&camsys CLK_CAM_LARB13>, 1948 <&camsys CLK_CAM_CAM2MM0_GALS>; 1949 clock-names = "apb", "smi", "gals"; 1950 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>; 1951 }; 1952 1953 larb14: larb@16002000 { 1954 compatible = "mediatek,mt8195-smi-larb"; 1955 reg = <0 0x16002000 0 0x1000>; 1956 mediatek,larb-id = <14>; 1957 mediatek,smi = <&smi_sub_common_cam_7x1>; 1958 clocks = <&camsys CLK_CAM_LARB14>, 1959 <&camsys CLK_CAM_LARB14>; 1960 clock-names = "apb", "smi"; 1961 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>; 1962 }; 1963 1964 smi_sub_common_cam_4x1: smi@16004000 { 1965 compatible = "mediatek,mt8195-smi-sub-common"; 1966 reg = <0 0x16004000 0 0x1000>; 1967 clocks = <&camsys CLK_CAM_LARB13>, 1968 <&camsys CLK_CAM_LARB13>, 1969 <&camsys CLK_CAM_CAM2MM0_GALS>; 1970 clock-names = "apb", "smi", "gals0"; 1971 mediatek,smi = <&smi_common_vdo>; 1972 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>; 1973 }; 1974 1975 smi_sub_common_cam_7x1: smi@16005000 { 1976 compatible = "mediatek,mt8195-smi-sub-common"; 1977 reg = <0 0x16005000 0 0x1000>; 1978 clocks = <&camsys CLK_CAM_LARB14>, 1979 <&camsys CLK_CAM_CAM2MM1_GALS>, 1980 <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>; 1981 clock-names = "apb", "smi", "gals0"; 1982 mediatek,smi = <&smi_common_vpp>; 1983 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>; 1984 }; 1985 1986 larb16: larb@16012000 { 1987 compatible = "mediatek,mt8195-smi-larb"; 1988 reg = <0 0x16012000 0 0x1000>; 1989 mediatek,larb-id = <16>; 1990 mediatek,smi = <&smi_sub_common_cam_7x1>; 1991 clocks = <&camsys_rawa CLK_CAM_RAWA_LARBX>, 1992 <&camsys_rawa CLK_CAM_RAWA_LARBX>; 1993 clock-names = "apb", "smi"; 1994 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWA>; 1995 }; 1996 1997 larb17: larb@16013000 { 1998 compatible = "mediatek,mt8195-smi-larb"; 1999 reg = <0 0x16013000 0 0x1000>; 2000 mediatek,larb-id = <17>; 2001 mediatek,smi = <&smi_sub_common_cam_4x1>; 2002 clocks = <&camsys_yuva CLK_CAM_YUVA_LARBX>, 2003 <&camsys_yuva CLK_CAM_YUVA_LARBX>; 2004 clock-names = "apb", "smi"; 2005 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWA>; 2006 }; 2007 2008 larb27: larb@16014000 { 2009 compatible = "mediatek,mt8195-smi-larb"; 2010 reg = <0 0x16014000 0 0x1000>; 2011 mediatek,larb-id = <27>; 2012 mediatek,smi = <&smi_sub_common_cam_7x1>; 2013 clocks = <&camsys_rawb CLK_CAM_RAWB_LARBX>, 2014 <&camsys_rawb CLK_CAM_RAWB_LARBX>; 2015 clock-names = "apb", "smi"; 2016 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWB>; 2017 }; 2018 2019 larb28: larb@16015000 { 2020 compatible = "mediatek,mt8195-smi-larb"; 2021 reg = <0 0x16015000 0 0x1000>; 2022 mediatek,larb-id = <28>; 2023 mediatek,smi = <&smi_sub_common_cam_4x1>; 2024 clocks = <&camsys_yuvb CLK_CAM_YUVB_LARBX>, 2025 <&camsys_yuvb CLK_CAM_YUVB_LARBX>; 2026 clock-names = "apb", "smi"; 2027 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWB>; 2028 }; 2029 2030 camsys_rawa: clock-controller@1604f000 { 2031 compatible = "mediatek,mt8195-camsys_rawa"; 2032 reg = <0 0x1604f000 0 0x1000>; 2033 #clock-cells = <1>; 2034 }; 2035 2036 camsys_yuva: clock-controller@1606f000 { 2037 compatible = "mediatek,mt8195-camsys_yuva"; 2038 reg = <0 0x1606f000 0 0x1000>; 2039 #clock-cells = <1>; 2040 }; 2041 2042 camsys_rawb: clock-controller@1608f000 { 2043 compatible = "mediatek,mt8195-camsys_rawb"; 2044 reg = <0 0x1608f000 0 0x1000>; 2045 #clock-cells = <1>; 2046 }; 2047 2048 camsys_yuvb: clock-controller@160af000 { 2049 compatible = "mediatek,mt8195-camsys_yuvb"; 2050 reg = <0 0x160af000 0 0x1000>; 2051 #clock-cells = <1>; 2052 }; 2053 2054 camsys_mraw: clock-controller@16140000 { 2055 compatible = "mediatek,mt8195-camsys_mraw"; 2056 reg = <0 0x16140000 0 0x1000>; 2057 #clock-cells = <1>; 2058 }; 2059 2060 larb25: larb@16141000 { 2061 compatible = "mediatek,mt8195-smi-larb"; 2062 reg = <0 0x16141000 0 0x1000>; 2063 mediatek,larb-id = <25>; 2064 mediatek,smi = <&smi_sub_common_cam_4x1>; 2065 clocks = <&camsys CLK_CAM_LARB13>, 2066 <&camsys_mraw CLK_CAM_MRAW_LARBX>, 2067 <&camsys CLK_CAM_CAM2MM0_GALS>; 2068 clock-names = "apb", "smi", "gals"; 2069 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_MRAW>; 2070 }; 2071 2072 larb26: larb@16142000 { 2073 compatible = "mediatek,mt8195-smi-larb"; 2074 reg = <0 0x16142000 0 0x1000>; 2075 mediatek,larb-id = <26>; 2076 mediatek,smi = <&smi_sub_common_cam_7x1>; 2077 clocks = <&camsys_mraw CLK_CAM_MRAW_LARBX>, 2078 <&camsys_mraw CLK_CAM_MRAW_LARBX>; 2079 clock-names = "apb", "smi"; 2080 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_MRAW>; 2081 2082 }; 2083 2084 ccusys: clock-controller@17200000 { 2085 compatible = "mediatek,mt8195-ccusys"; 2086 reg = <0 0x17200000 0 0x1000>; 2087 #clock-cells = <1>; 2088 }; 2089 2090 larb18: larb@17201000 { 2091 compatible = "mediatek,mt8195-smi-larb"; 2092 reg = <0 0x17201000 0 0x1000>; 2093 mediatek,larb-id = <18>; 2094 mediatek,smi = <&smi_sub_common_cam_7x1>; 2095 clocks = <&ccusys CLK_CCU_LARB18>, 2096 <&ccusys CLK_CCU_LARB18>; 2097 clock-names = "apb", "smi"; 2098 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>; 2099 }; 2100 2101 larb24: larb@1800d000 { 2102 compatible = "mediatek,mt8195-smi-larb"; 2103 reg = <0 0x1800d000 0 0x1000>; 2104 mediatek,larb-id = <24>; 2105 mediatek,smi = <&smi_common_vdo>; 2106 clocks = <&vdecsys_soc CLK_VDEC_SOC_LARB1>, 2107 <&vdecsys_soc CLK_VDEC_SOC_LARB1>; 2108 clock-names = "apb", "smi"; 2109 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>; 2110 }; 2111 2112 larb23: larb@1800e000 { 2113 compatible = "mediatek,mt8195-smi-larb"; 2114 reg = <0 0x1800e000 0 0x1000>; 2115 mediatek,larb-id = <23>; 2116 mediatek,smi = <&smi_sub_common_vdec_vpp0_2x1>; 2117 clocks = <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>, 2118 <&vdecsys_soc CLK_VDEC_SOC_LARB1>; 2119 clock-names = "apb", "smi"; 2120 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>; 2121 }; 2122 2123 vdecsys_soc: clock-controller@1800f000 { 2124 compatible = "mediatek,mt8195-vdecsys_soc"; 2125 reg = <0 0x1800f000 0 0x1000>; 2126 #clock-cells = <1>; 2127 }; 2128 2129 larb21: larb@1802e000 { 2130 compatible = "mediatek,mt8195-smi-larb"; 2131 reg = <0 0x1802e000 0 0x1000>; 2132 mediatek,larb-id = <21>; 2133 mediatek,smi = <&smi_common_vdo>; 2134 clocks = <&vdecsys CLK_VDEC_LARB1>, 2135 <&vdecsys CLK_VDEC_LARB1>; 2136 clock-names = "apb", "smi"; 2137 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>; 2138 }; 2139 2140 vdecsys: clock-controller@1802f000 { 2141 compatible = "mediatek,mt8195-vdecsys"; 2142 reg = <0 0x1802f000 0 0x1000>; 2143 #clock-cells = <1>; 2144 }; 2145 2146 larb22: larb@1803e000 { 2147 compatible = "mediatek,mt8195-smi-larb"; 2148 reg = <0 0x1803e000 0 0x1000>; 2149 mediatek,larb-id = <22>; 2150 mediatek,smi = <&smi_sub_common_vdec_vpp0_2x1>; 2151 clocks = <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>, 2152 <&vdecsys_core1 CLK_VDEC_CORE1_LARB1>; 2153 clock-names = "apb", "smi"; 2154 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC2>; 2155 }; 2156 2157 vdecsys_core1: clock-controller@1803f000 { 2158 compatible = "mediatek,mt8195-vdecsys_core1"; 2159 reg = <0 0x1803f000 0 0x1000>; 2160 #clock-cells = <1>; 2161 }; 2162 2163 apusys_pll: clock-controller@190f3000 { 2164 compatible = "mediatek,mt8195-apusys_pll"; 2165 reg = <0 0x190f3000 0 0x1000>; 2166 #clock-cells = <1>; 2167 }; 2168 2169 vencsys: clock-controller@1a000000 { 2170 compatible = "mediatek,mt8195-vencsys"; 2171 reg = <0 0x1a000000 0 0x1000>; 2172 #clock-cells = <1>; 2173 }; 2174 2175 larb19: larb@1a010000 { 2176 compatible = "mediatek,mt8195-smi-larb"; 2177 reg = <0 0x1a010000 0 0x1000>; 2178 mediatek,larb-id = <19>; 2179 mediatek,smi = <&smi_common_vdo>; 2180 clocks = <&vencsys CLK_VENC_VENC>, 2181 <&vencsys CLK_VENC_GALS>; 2182 clock-names = "apb", "smi"; 2183 power-domains = <&spm MT8195_POWER_DOMAIN_VENC>; 2184 }; 2185 2186 venc: video-codec@1a020000 { 2187 compatible = "mediatek,mt8195-vcodec-enc"; 2188 reg = <0 0x1a020000 0 0x10000>; 2189 iommus = <&iommu_vdo M4U_PORT_L19_VENC_RCPU>, 2190 <&iommu_vdo M4U_PORT_L19_VENC_REC>, 2191 <&iommu_vdo M4U_PORT_L19_VENC_BSDMA>, 2192 <&iommu_vdo M4U_PORT_L19_VENC_SV_COMV>, 2193 <&iommu_vdo M4U_PORT_L19_VENC_RD_COMV>, 2194 <&iommu_vdo M4U_PORT_L19_VENC_CUR_LUMA>, 2195 <&iommu_vdo M4U_PORT_L19_VENC_CUR_CHROMA>, 2196 <&iommu_vdo M4U_PORT_L19_VENC_REF_LUMA>, 2197 <&iommu_vdo M4U_PORT_L19_VENC_REF_CHROMA>; 2198 interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH 0>; 2199 mediatek,scp = <&scp>; 2200 clocks = <&vencsys CLK_VENC_VENC>; 2201 clock-names = "venc_sel"; 2202 assigned-clocks = <&topckgen CLK_TOP_VENC>; 2203 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>; 2204 power-domains = <&spm MT8195_POWER_DOMAIN_VENC>; 2205 #address-cells = <2>; 2206 #size-cells = <2>; 2207 dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>; 2208 }; 2209 2210 vencsys_core1: clock-controller@1b000000 { 2211 compatible = "mediatek,mt8195-vencsys_core1"; 2212 reg = <0 0x1b000000 0 0x1000>; 2213 #clock-cells = <1>; 2214 }; 2215 2216 vdosys0: syscon@1c01a000 { 2217 compatible = "mediatek,mt8195-mmsys", "syscon"; 2218 reg = <0 0x1c01a000 0 0x1000>; 2219 mboxes = <&gce0 0 CMDQ_THR_PRIO_4>; 2220 #clock-cells = <1>; 2221 }; 2222 2223 larb20: larb@1b010000 { 2224 compatible = "mediatek,mt8195-smi-larb"; 2225 reg = <0 0x1b010000 0 0x1000>; 2226 mediatek,larb-id = <20>; 2227 mediatek,smi = <&smi_common_vpp>; 2228 clocks = <&vencsys_core1 CLK_VENC_CORE1_LARB>, 2229 <&vencsys_core1 CLK_VENC_CORE1_GALS>, 2230 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>; 2231 clock-names = "apb", "smi", "gals"; 2232 power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>; 2233 }; 2234 2235 ovl0: ovl@1c000000 { 2236 compatible = "mediatek,mt8195-disp-ovl", "mediatek,mt8183-disp-ovl"; 2237 reg = <0 0x1c000000 0 0x1000>; 2238 interrupts = <GIC_SPI 636 IRQ_TYPE_LEVEL_HIGH 0>; 2239 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2240 clocks = <&vdosys0 CLK_VDO0_DISP_OVL0>; 2241 iommus = <&iommu_vdo M4U_PORT_L0_DISP_OVL0_RDMA0>; 2242 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x0000 0x1000>; 2243 }; 2244 2245 rdma0: rdma@1c002000 { 2246 compatible = "mediatek,mt8195-disp-rdma"; 2247 reg = <0 0x1c002000 0 0x1000>; 2248 interrupts = <GIC_SPI 638 IRQ_TYPE_LEVEL_HIGH 0>; 2249 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2250 clocks = <&vdosys0 CLK_VDO0_DISP_RDMA0>; 2251 iommus = <&iommu_vdo M4U_PORT_L0_DISP_RDMA0>; 2252 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x2000 0x1000>; 2253 }; 2254 2255 color0: color@1c003000 { 2256 compatible = "mediatek,mt8195-disp-color", "mediatek,mt8173-disp-color"; 2257 reg = <0 0x1c003000 0 0x1000>; 2258 interrupts = <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH 0>; 2259 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2260 clocks = <&vdosys0 CLK_VDO0_DISP_COLOR0>; 2261 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x3000 0x1000>; 2262 }; 2263 2264 ccorr0: ccorr@1c004000 { 2265 compatible = "mediatek,mt8195-disp-ccorr", "mediatek,mt8192-disp-ccorr"; 2266 reg = <0 0x1c004000 0 0x1000>; 2267 interrupts = <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH 0>; 2268 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2269 clocks = <&vdosys0 CLK_VDO0_DISP_CCORR0>; 2270 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x4000 0x1000>; 2271 }; 2272 2273 aal0: aal@1c005000 { 2274 compatible = "mediatek,mt8195-disp-aal", "mediatek,mt8183-disp-aal"; 2275 reg = <0 0x1c005000 0 0x1000>; 2276 interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH 0>; 2277 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2278 clocks = <&vdosys0 CLK_VDO0_DISP_AAL0>; 2279 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x5000 0x1000>; 2280 }; 2281 2282 gamma0: gamma@1c006000 { 2283 compatible = "mediatek,mt8195-disp-gamma", "mediatek,mt8183-disp-gamma"; 2284 reg = <0 0x1c006000 0 0x1000>; 2285 interrupts = <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH 0>; 2286 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2287 clocks = <&vdosys0 CLK_VDO0_DISP_GAMMA0>; 2288 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x6000 0x1000>; 2289 }; 2290 2291 dither0: dither@1c007000 { 2292 compatible = "mediatek,mt8195-disp-dither", "mediatek,mt8183-disp-dither"; 2293 reg = <0 0x1c007000 0 0x1000>; 2294 interrupts = <GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH 0>; 2295 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2296 clocks = <&vdosys0 CLK_VDO0_DISP_DITHER0>; 2297 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x7000 0x1000>; 2298 }; 2299 2300 dsc0: dsc@1c009000 { 2301 compatible = "mediatek,mt8195-disp-dsc"; 2302 reg = <0 0x1c009000 0 0x1000>; 2303 interrupts = <GIC_SPI 645 IRQ_TYPE_LEVEL_HIGH 0>; 2304 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2305 clocks = <&vdosys0 CLK_VDO0_DSC_WRAP0>; 2306 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x9000 0x1000>; 2307 }; 2308 2309 merge0: merge@1c014000 { 2310 compatible = "mediatek,mt8195-disp-merge"; 2311 reg = <0 0x1c014000 0 0x1000>; 2312 interrupts = <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH 0>; 2313 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2314 clocks = <&vdosys0 CLK_VDO0_VPP_MERGE0>; 2315 mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0x4000 0x1000>; 2316 }; 2317 2318 dp_intf0: dp-intf@1c015000 { 2319 compatible = "mediatek,mt8195-dp-intf"; 2320 reg = <0 0x1c015000 0 0x1000>; 2321 interrupts = <GIC_SPI 657 IRQ_TYPE_LEVEL_HIGH 0>; 2322 clocks = <&vdosys0 CLK_VDO0_DP_INTF0>, 2323 <&vdosys0 CLK_VDO0_DP_INTF0_DP_INTF>, 2324 <&apmixedsys CLK_APMIXED_TVDPLL1>; 2325 clock-names = "engine", "pixel", "pll"; 2326 status = "disabled"; 2327 }; 2328 2329 mutex: mutex@1c016000 { 2330 compatible = "mediatek,mt8195-disp-mutex"; 2331 reg = <0 0x1c016000 0 0x1000>; 2332 interrupts = <GIC_SPI 658 IRQ_TYPE_LEVEL_HIGH 0>; 2333 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2334 clocks = <&vdosys0 CLK_VDO0_DISP_MUTEX0>; 2335 mediatek,gce-events = <CMDQ_EVENT_VDO0_DISP_STREAM_DONE_0>; 2336 }; 2337 2338 larb0: larb@1c018000 { 2339 compatible = "mediatek,mt8195-smi-larb"; 2340 reg = <0 0x1c018000 0 0x1000>; 2341 mediatek,larb-id = <0>; 2342 mediatek,smi = <&smi_common_vdo>; 2343 clocks = <&vdosys0 CLK_VDO0_SMI_LARB>, 2344 <&vdosys0 CLK_VDO0_SMI_LARB>, 2345 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB0>; 2346 clock-names = "apb", "smi", "gals"; 2347 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2348 }; 2349 2350 larb1: larb@1c019000 { 2351 compatible = "mediatek,mt8195-smi-larb"; 2352 reg = <0 0x1c019000 0 0x1000>; 2353 mediatek,larb-id = <1>; 2354 mediatek,smi = <&smi_common_vpp>; 2355 clocks = <&vdosys0 CLK_VDO0_SMI_LARB>, 2356 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>, 2357 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB1>; 2358 clock-names = "apb", "smi", "gals"; 2359 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2360 }; 2361 2362 vdosys1: syscon@1c100000 { 2363 compatible = "mediatek,mt8195-mmsys", "syscon"; 2364 reg = <0 0x1c100000 0 0x1000>; 2365 #clock-cells = <1>; 2366 }; 2367 2368 smi_common_vdo: smi@1c01b000 { 2369 compatible = "mediatek,mt8195-smi-common-vdo"; 2370 reg = <0 0x1c01b000 0 0x1000>; 2371 clocks = <&vdosys0 CLK_VDO0_SMI_COMMON>, 2372 <&vdosys0 CLK_VDO0_SMI_EMI>, 2373 <&vdosys0 CLK_VDO0_SMI_RSI>, 2374 <&vdosys0 CLK_VDO0_SMI_GALS>; 2375 clock-names = "apb", "smi", "gals0", "gals1"; 2376 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2377 2378 }; 2379 2380 iommu_vdo: iommu@1c01f000 { 2381 compatible = "mediatek,mt8195-iommu-vdo"; 2382 reg = <0 0x1c01f000 0 0x1000>; 2383 mediatek,larbs = <&larb0 &larb2 &larb5 &larb7 &larb9 2384 &larb10 &larb11 &larb13 &larb17 2385 &larb19 &larb21 &larb24 &larb25 2386 &larb28>; 2387 interrupts = <GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH 0>; 2388 #iommu-cells = <1>; 2389 clocks = <&vdosys0 CLK_VDO0_SMI_IOMMU>; 2390 clock-names = "bclk"; 2391 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2392 }; 2393 2394 larb2: larb@1c102000 { 2395 compatible = "mediatek,mt8195-smi-larb"; 2396 reg = <0 0x1c102000 0 0x1000>; 2397 mediatek,larb-id = <2>; 2398 mediatek,smi = <&smi_common_vdo>; 2399 clocks = <&vdosys1 CLK_VDO1_SMI_LARB2>, 2400 <&vdosys1 CLK_VDO1_SMI_LARB2>, 2401 <&vdosys1 CLK_VDO1_GALS>; 2402 clock-names = "apb", "smi", "gals"; 2403 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 2404 }; 2405 2406 larb3: larb@1c103000 { 2407 compatible = "mediatek,mt8195-smi-larb"; 2408 reg = <0 0x1c103000 0 0x1000>; 2409 mediatek,larb-id = <3>; 2410 mediatek,smi = <&smi_common_vpp>; 2411 clocks = <&vdosys1 CLK_VDO1_SMI_LARB3>, 2412 <&vdosys1 CLK_VDO1_GALS>, 2413 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>; 2414 clock-names = "apb", "smi", "gals"; 2415 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 2416 }; 2417 2418 dp_intf1: dp-intf@1c113000 { 2419 compatible = "mediatek,mt8195-dp-intf"; 2420 reg = <0 0x1c113000 0 0x1000>; 2421 interrupts = <GIC_SPI 513 IRQ_TYPE_LEVEL_HIGH 0>; 2422 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 2423 clocks = <&vdosys1 CLK_VDO1_DP_INTF0_MM>, 2424 <&vdosys1 CLK_VDO1_DPINTF>, 2425 <&apmixedsys CLK_APMIXED_TVDPLL2>; 2426 clock-names = "engine", "pixel", "pll"; 2427 status = "disabled"; 2428 }; 2429 2430 edp_tx: edp-tx@1c500000 { 2431 compatible = "mediatek,mt8195-edp-tx"; 2432 reg = <0 0x1c500000 0 0x8000>; 2433 nvmem-cells = <&dp_calibration>; 2434 nvmem-cell-names = "dp_calibration_data"; 2435 power-domains = <&spm MT8195_POWER_DOMAIN_EPD_TX>; 2436 interrupts = <GIC_SPI 676 IRQ_TYPE_LEVEL_HIGH 0>; 2437 max-linkrate-mhz = <8100>; 2438 status = "disabled"; 2439 }; 2440 2441 dp_tx: dp-tx@1c600000 { 2442 compatible = "mediatek,mt8195-dp-tx"; 2443 reg = <0 0x1c600000 0 0x8000>; 2444 nvmem-cells = <&dp_calibration>; 2445 nvmem-cell-names = "dp_calibration_data"; 2446 power-domains = <&spm MT8195_POWER_DOMAIN_DP_TX>; 2447 interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH 0>; 2448 max-linkrate-mhz = <8100>; 2449 status = "disabled"; 2450 }; 2451 }; 2452}; 2453