mt8192.dtsi (d93618da6b6d453c6a9684a3460ffd51b9b4ef2e) mt8192.dtsi (ce459b1da752cf1dc0b81aba999a6542ab866993)
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (C) 2020 MediaTek Inc.
4 * Author: Seiya Wang <seiya.wang@mediatek.com>
5 */
6
7/dts-v1/;
8#include <dt-bindings/clock/mt8192-clk.h>

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164 core3 {
165 cpu = <&cpu7>;
166 };
167 };
168 };
169
170 l2_0: l2-cache0 {
171 compatible = "cache";
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (C) 2020 MediaTek Inc.
4 * Author: Seiya Wang <seiya.wang@mediatek.com>
5 */
6
7/dts-v1/;
8#include <dt-bindings/clock/mt8192-clk.h>

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164 core3 {
165 cpu = <&cpu7>;
166 };
167 };
168 };
169
170 l2_0: l2-cache0 {
171 compatible = "cache";
172 cache-level = <2>;
172 next-level-cache = <&l3_0>;
173 };
174
175 l2_1: l2-cache1 {
176 compatible = "cache";
173 next-level-cache = <&l3_0>;
174 };
175
176 l2_1: l2-cache1 {
177 compatible = "cache";
178 cache-level = <2>;
177 next-level-cache = <&l3_0>;
178 };
179
180 l3_0: l3-cache {
181 compatible = "cache";
179 next-level-cache = <&l3_0>;
180 };
181
182 l3_0: l3-cache {
183 compatible = "cache";
184 cache-level = <3>;
182 };
183
184 idle-states {
185 entry-method = "psci";
186 cpu_sleep_l: cpu-sleep-l {
187 compatible = "arm,idle-state";
188 arm,psci-suspend-param = <0x00010001>;
189 local-timer-stop;

--- 1461 unchanged lines hidden --- 		185 };
186
187 idle-states {
188 entry-method = "psci";
189 cpu_sleep_l: cpu-sleep-l {
190 compatible = "arm,idle-state";
191 arm,psci-suspend-param = <0x00010001>;
192 local-timer-stop;

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