1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (C) 2020 MediaTek Inc. 4 * Author: Seiya Wang <seiya.wang@mediatek.com> 5 */ 6 7/dts-v1/; 8#include <dt-bindings/clock/mt8192-clk.h> 9#include <dt-bindings/gce/mt8192-gce.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/interrupt-controller/irq.h> 12#include <dt-bindings/memory/mt8192-larb-port.h> 13#include <dt-bindings/pinctrl/mt8192-pinfunc.h> 14#include <dt-bindings/phy/phy.h> 15#include <dt-bindings/power/mt8192-power.h> 16#include <dt-bindings/reset/mt8192-resets.h> 17 18/ { 19 compatible = "mediatek,mt8192"; 20 interrupt-parent = <&gic>; 21 #address-cells = <2>; 22 #size-cells = <2>; 23 24 aliases { 25 ovl0 = &ovl0; 26 ovl-2l0 = &ovl_2l0; 27 ovl-2l2 = &ovl_2l2; 28 rdma0 = &rdma0; 29 rdma4 = &rdma4; 30 }; 31 32 clk26m: oscillator0 { 33 compatible = "fixed-clock"; 34 #clock-cells = <0>; 35 clock-frequency = <26000000>; 36 clock-output-names = "clk26m"; 37 }; 38 39 clk32k: oscillator1 { 40 compatible = "fixed-clock"; 41 #clock-cells = <0>; 42 clock-frequency = <32768>; 43 clock-output-names = "clk32k"; 44 }; 45 46 cpus { 47 #address-cells = <1>; 48 #size-cells = <0>; 49 50 cpu0: cpu@0 { 51 device_type = "cpu"; 52 compatible = "arm,cortex-a55"; 53 reg = <0x000>; 54 enable-method = "psci"; 55 clock-frequency = <1701000000>; 56 cpu-idle-states = <&cpu_sleep_l &cluster_sleep_l>; 57 next-level-cache = <&l2_0>; 58 capacity-dmips-mhz = <530>; 59 }; 60 61 cpu1: cpu@100 { 62 device_type = "cpu"; 63 compatible = "arm,cortex-a55"; 64 reg = <0x100>; 65 enable-method = "psci"; 66 clock-frequency = <1701000000>; 67 cpu-idle-states = <&cpu_sleep_l &cluster_sleep_l>; 68 next-level-cache = <&l2_0>; 69 capacity-dmips-mhz = <530>; 70 }; 71 72 cpu2: cpu@200 { 73 device_type = "cpu"; 74 compatible = "arm,cortex-a55"; 75 reg = <0x200>; 76 enable-method = "psci"; 77 clock-frequency = <1701000000>; 78 cpu-idle-states = <&cpu_sleep_l &cluster_sleep_l>; 79 next-level-cache = <&l2_0>; 80 capacity-dmips-mhz = <530>; 81 }; 82 83 cpu3: cpu@300 { 84 device_type = "cpu"; 85 compatible = "arm,cortex-a55"; 86 reg = <0x300>; 87 enable-method = "psci"; 88 clock-frequency = <1701000000>; 89 cpu-idle-states = <&cpu_sleep_l &cluster_sleep_l>; 90 next-level-cache = <&l2_0>; 91 capacity-dmips-mhz = <530>; 92 }; 93 94 cpu4: cpu@400 { 95 device_type = "cpu"; 96 compatible = "arm,cortex-a76"; 97 reg = <0x400>; 98 enable-method = "psci"; 99 clock-frequency = <2171000000>; 100 cpu-idle-states = <&cpu_sleep_b &cluster_sleep_b>; 101 next-level-cache = <&l2_1>; 102 capacity-dmips-mhz = <1024>; 103 }; 104 105 cpu5: cpu@500 { 106 device_type = "cpu"; 107 compatible = "arm,cortex-a76"; 108 reg = <0x500>; 109 enable-method = "psci"; 110 clock-frequency = <2171000000>; 111 cpu-idle-states = <&cpu_sleep_b &cluster_sleep_b>; 112 next-level-cache = <&l2_1>; 113 capacity-dmips-mhz = <1024>; 114 }; 115 116 cpu6: cpu@600 { 117 device_type = "cpu"; 118 compatible = "arm,cortex-a76"; 119 reg = <0x600>; 120 enable-method = "psci"; 121 clock-frequency = <2171000000>; 122 cpu-idle-states = <&cpu_sleep_b &cluster_sleep_b>; 123 next-level-cache = <&l2_1>; 124 capacity-dmips-mhz = <1024>; 125 }; 126 127 cpu7: cpu@700 { 128 device_type = "cpu"; 129 compatible = "arm,cortex-a76"; 130 reg = <0x700>; 131 enable-method = "psci"; 132 clock-frequency = <2171000000>; 133 cpu-idle-states = <&cpu_sleep_b &cluster_sleep_b>; 134 next-level-cache = <&l2_1>; 135 capacity-dmips-mhz = <1024>; 136 }; 137 138 cpu-map { 139 cluster0 { 140 core0 { 141 cpu = <&cpu0>; 142 }; 143 core1 { 144 cpu = <&cpu1>; 145 }; 146 core2 { 147 cpu = <&cpu2>; 148 }; 149 core3 { 150 cpu = <&cpu3>; 151 }; 152 }; 153 154 cluster1 { 155 core0 { 156 cpu = <&cpu4>; 157 }; 158 core1 { 159 cpu = <&cpu5>; 160 }; 161 core2 { 162 cpu = <&cpu6>; 163 }; 164 core3 { 165 cpu = <&cpu7>; 166 }; 167 }; 168 }; 169 170 l2_0: l2-cache0 { 171 compatible = "cache"; 172 next-level-cache = <&l3_0>; 173 }; 174 175 l2_1: l2-cache1 { 176 compatible = "cache"; 177 next-level-cache = <&l3_0>; 178 }; 179 180 l3_0: l3-cache { 181 compatible = "cache"; 182 }; 183 184 idle-states { 185 entry-method = "psci"; 186 cpu_sleep_l: cpu-sleep-l { 187 compatible = "arm,idle-state"; 188 arm,psci-suspend-param = <0x00010001>; 189 local-timer-stop; 190 entry-latency-us = <55>; 191 exit-latency-us = <140>; 192 min-residency-us = <780>; 193 }; 194 cpu_sleep_b: cpu-sleep-b { 195 compatible = "arm,idle-state"; 196 arm,psci-suspend-param = <0x00010001>; 197 local-timer-stop; 198 entry-latency-us = <35>; 199 exit-latency-us = <145>; 200 min-residency-us = <720>; 201 }; 202 cluster_sleep_l: cluster-sleep-l { 203 compatible = "arm,idle-state"; 204 arm,psci-suspend-param = <0x01010002>; 205 local-timer-stop; 206 entry-latency-us = <60>; 207 exit-latency-us = <155>; 208 min-residency-us = <860>; 209 }; 210 cluster_sleep_b: cluster-sleep-b { 211 compatible = "arm,idle-state"; 212 arm,psci-suspend-param = <0x01010002>; 213 local-timer-stop; 214 entry-latency-us = <40>; 215 exit-latency-us = <155>; 216 min-residency-us = <780>; 217 }; 218 }; 219 }; 220 221 pmu-a55 { 222 compatible = "arm,cortex-a55-pmu"; 223 interrupt-parent = <&gic>; 224 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>; 225 }; 226 227 pmu-a76 { 228 compatible = "arm,cortex-a76-pmu"; 229 interrupt-parent = <&gic>; 230 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>; 231 }; 232 233 psci { 234 compatible = "arm,psci-1.0"; 235 method = "smc"; 236 }; 237 238 timer: timer { 239 compatible = "arm,armv8-timer"; 240 interrupt-parent = <&gic>; 241 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>, 242 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>, 243 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>, 244 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>; 245 clock-frequency = <13000000>; 246 }; 247 248 soc { 249 #address-cells = <2>; 250 #size-cells = <2>; 251 compatible = "simple-bus"; 252 ranges; 253 254 gic: interrupt-controller@c000000 { 255 compatible = "arm,gic-v3"; 256 #interrupt-cells = <4>; 257 #redistributor-regions = <1>; 258 interrupt-parent = <&gic>; 259 interrupt-controller; 260 reg = <0 0x0c000000 0 0x40000>, 261 <0 0x0c040000 0 0x200000>; 262 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 263 264 ppi-partitions { 265 ppi_cluster0: interrupt-partition-0 { 266 affinity = <&cpu0 &cpu1 &cpu2 &cpu3>; 267 }; 268 ppi_cluster1: interrupt-partition-1 { 269 affinity = <&cpu4 &cpu5 &cpu6 &cpu7>; 270 }; 271 }; 272 }; 273 274 topckgen: syscon@10000000 { 275 compatible = "mediatek,mt8192-topckgen", "syscon"; 276 reg = <0 0x10000000 0 0x1000>; 277 #clock-cells = <1>; 278 }; 279 280 infracfg: syscon@10001000 { 281 compatible = "mediatek,mt8192-infracfg", "syscon"; 282 reg = <0 0x10001000 0 0x1000>; 283 #clock-cells = <1>; 284 #reset-cells = <1>; 285 }; 286 287 pericfg: syscon@10003000 { 288 compatible = "mediatek,mt8192-pericfg", "syscon"; 289 reg = <0 0x10003000 0 0x1000>; 290 #clock-cells = <1>; 291 }; 292 293 pio: pinctrl@10005000 { 294 compatible = "mediatek,mt8192-pinctrl"; 295 reg = <0 0x10005000 0 0x1000>, 296 <0 0x11c20000 0 0x1000>, 297 <0 0x11d10000 0 0x1000>, 298 <0 0x11d30000 0 0x1000>, 299 <0 0x11d40000 0 0x1000>, 300 <0 0x11e20000 0 0x1000>, 301 <0 0x11e70000 0 0x1000>, 302 <0 0x11ea0000 0 0x1000>, 303 <0 0x11f20000 0 0x1000>, 304 <0 0x11f30000 0 0x1000>, 305 <0 0x1000b000 0 0x1000>; 306 reg-names = "iocfg0", "iocfg_rm", "iocfg_bm", 307 "iocfg_bl", "iocfg_br", "iocfg_lm", 308 "iocfg_lb", "iocfg_rt", "iocfg_lt", 309 "iocfg_tl", "eint"; 310 gpio-controller; 311 #gpio-cells = <2>; 312 gpio-ranges = <&pio 0 0 220>; 313 interrupt-controller; 314 interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH 0>; 315 #interrupt-cells = <2>; 316 }; 317 318 scpsys: syscon@10006000 { 319 compatible = "mediatek,mt8192-scpsys", "syscon", "simple-mfd"; 320 reg = <0 0x10006000 0 0x1000>; 321 322 /* System Power Manager */ 323 spm: power-controller { 324 compatible = "mediatek,mt8192-power-controller"; 325 #address-cells = <1>; 326 #size-cells = <0>; 327 #power-domain-cells = <1>; 328 329 /* power domain of the SoC */ 330 power-domain@MT8192_POWER_DOMAIN_AUDIO { 331 reg = <MT8192_POWER_DOMAIN_AUDIO>; 332 clocks = <&topckgen CLK_TOP_AUD_INTBUS_SEL>, 333 <&infracfg CLK_INFRA_AUDIO_26M_B>, 334 <&infracfg CLK_INFRA_AUDIO>; 335 clock-names = "audio", "audio1", "audio2"; 336 mediatek,infracfg = <&infracfg>; 337 #power-domain-cells = <0>; 338 }; 339 340 power-domain@MT8192_POWER_DOMAIN_CONN { 341 reg = <MT8192_POWER_DOMAIN_CONN>; 342 clocks = <&infracfg CLK_INFRA_PMIC_CONN>; 343 clock-names = "conn"; 344 mediatek,infracfg = <&infracfg>; 345 #power-domain-cells = <0>; 346 }; 347 348 power-domain@MT8192_POWER_DOMAIN_MFG0 { 349 reg = <MT8192_POWER_DOMAIN_MFG0>; 350 clocks = <&topckgen CLK_TOP_MFG_PLL_SEL>; 351 clock-names = "mfg"; 352 #address-cells = <1>; 353 #size-cells = <0>; 354 #power-domain-cells = <1>; 355 356 power-domain@MT8192_POWER_DOMAIN_MFG1 { 357 reg = <MT8192_POWER_DOMAIN_MFG1>; 358 mediatek,infracfg = <&infracfg>; 359 #address-cells = <1>; 360 #size-cells = <0>; 361 #power-domain-cells = <1>; 362 363 power-domain@MT8192_POWER_DOMAIN_MFG2 { 364 reg = <MT8192_POWER_DOMAIN_MFG2>; 365 #power-domain-cells = <0>; 366 }; 367 368 power-domain@MT8192_POWER_DOMAIN_MFG3 { 369 reg = <MT8192_POWER_DOMAIN_MFG3>; 370 #power-domain-cells = <0>; 371 }; 372 373 power-domain@MT8192_POWER_DOMAIN_MFG4 { 374 reg = <MT8192_POWER_DOMAIN_MFG4>; 375 #power-domain-cells = <0>; 376 }; 377 378 power-domain@MT8192_POWER_DOMAIN_MFG5 { 379 reg = <MT8192_POWER_DOMAIN_MFG5>; 380 #power-domain-cells = <0>; 381 }; 382 383 power-domain@MT8192_POWER_DOMAIN_MFG6 { 384 reg = <MT8192_POWER_DOMAIN_MFG6>; 385 #power-domain-cells = <0>; 386 }; 387 }; 388 }; 389 390 power-domain@MT8192_POWER_DOMAIN_DISP { 391 reg = <MT8192_POWER_DOMAIN_DISP>; 392 clocks = <&topckgen CLK_TOP_DISP_SEL>, 393 <&mmsys CLK_MM_SMI_INFRA>, 394 <&mmsys CLK_MM_SMI_COMMON>, 395 <&mmsys CLK_MM_SMI_GALS>, 396 <&mmsys CLK_MM_SMI_IOMMU>; 397 clock-names = "disp", "disp-0", "disp-1", "disp-2", 398 "disp-3"; 399 mediatek,infracfg = <&infracfg>; 400 #address-cells = <1>; 401 #size-cells = <0>; 402 #power-domain-cells = <1>; 403 404 power-domain@MT8192_POWER_DOMAIN_IPE { 405 reg = <MT8192_POWER_DOMAIN_IPE>; 406 clocks = <&topckgen CLK_TOP_IPE_SEL>, 407 <&ipesys CLK_IPE_LARB19>, 408 <&ipesys CLK_IPE_LARB20>, 409 <&ipesys CLK_IPE_SMI_SUBCOM>, 410 <&ipesys CLK_IPE_GALS>; 411 clock-names = "ipe", "ipe-0", "ipe-1", "ipe-2", 412 "ipe-3"; 413 mediatek,infracfg = <&infracfg>; 414 #power-domain-cells = <0>; 415 }; 416 417 power-domain@MT8192_POWER_DOMAIN_ISP { 418 reg = <MT8192_POWER_DOMAIN_ISP>; 419 clocks = <&topckgen CLK_TOP_IMG1_SEL>, 420 <&imgsys CLK_IMG_LARB9>, 421 <&imgsys CLK_IMG_GALS>; 422 clock-names = "isp", "isp-0", "isp-1"; 423 mediatek,infracfg = <&infracfg>; 424 #power-domain-cells = <0>; 425 }; 426 427 power-domain@MT8192_POWER_DOMAIN_ISP2 { 428 reg = <MT8192_POWER_DOMAIN_ISP2>; 429 clocks = <&topckgen CLK_TOP_IMG2_SEL>, 430 <&imgsys2 CLK_IMG2_LARB11>, 431 <&imgsys2 CLK_IMG2_GALS>; 432 clock-names = "isp2", "isp2-0", "isp2-1"; 433 mediatek,infracfg = <&infracfg>; 434 #power-domain-cells = <0>; 435 }; 436 437 power-domain@MT8192_POWER_DOMAIN_MDP { 438 reg = <MT8192_POWER_DOMAIN_MDP>; 439 clocks = <&topckgen CLK_TOP_MDP_SEL>, 440 <&mdpsys CLK_MDP_SMI0>; 441 clock-names = "mdp", "mdp-0"; 442 mediatek,infracfg = <&infracfg>; 443 #power-domain-cells = <0>; 444 }; 445 446 power-domain@MT8192_POWER_DOMAIN_VENC { 447 reg = <MT8192_POWER_DOMAIN_VENC>; 448 clocks = <&topckgen CLK_TOP_VENC_SEL>, 449 <&vencsys CLK_VENC_SET1_VENC>; 450 clock-names = "venc", "venc-0"; 451 mediatek,infracfg = <&infracfg>; 452 #power-domain-cells = <0>; 453 }; 454 455 power-domain@MT8192_POWER_DOMAIN_VDEC { 456 reg = <MT8192_POWER_DOMAIN_VDEC>; 457 clocks = <&topckgen CLK_TOP_VDEC_SEL>, 458 <&vdecsys_soc CLK_VDEC_SOC_VDEC>, 459 <&vdecsys_soc CLK_VDEC_SOC_LAT>, 460 <&vdecsys_soc CLK_VDEC_SOC_LARB1>; 461 clock-names = "vdec", "vdec-0", "vdec-1", "vdec-2"; 462 mediatek,infracfg = <&infracfg>; 463 #address-cells = <1>; 464 #size-cells = <0>; 465 #power-domain-cells = <1>; 466 467 power-domain@MT8192_POWER_DOMAIN_VDEC2 { 468 reg = <MT8192_POWER_DOMAIN_VDEC2>; 469 clocks = <&vdecsys CLK_VDEC_VDEC>, 470 <&vdecsys CLK_VDEC_LAT>, 471 <&vdecsys CLK_VDEC_LARB1>; 472 clock-names = "vdec2-0", "vdec2-1", 473 "vdec2-2"; 474 #power-domain-cells = <0>; 475 }; 476 }; 477 478 power-domain@MT8192_POWER_DOMAIN_CAM { 479 reg = <MT8192_POWER_DOMAIN_CAM>; 480 clocks = <&topckgen CLK_TOP_CAM_SEL>, 481 <&camsys CLK_CAM_LARB13>, 482 <&camsys CLK_CAM_LARB14>, 483 <&camsys CLK_CAM_CCU_GALS>, 484 <&camsys CLK_CAM_CAM2MM_GALS>; 485 clock-names = "cam", "cam-0", "cam-1", "cam-2", 486 "cam-3"; 487 mediatek,infracfg = <&infracfg>; 488 #address-cells = <1>; 489 #size-cells = <0>; 490 #power-domain-cells = <1>; 491 492 power-domain@MT8192_POWER_DOMAIN_CAM_RAWA { 493 reg = <MT8192_POWER_DOMAIN_CAM_RAWA>; 494 clocks = <&camsys_rawa CLK_CAM_RAWA_LARBX>; 495 clock-names = "cam_rawa-0"; 496 #power-domain-cells = <0>; 497 }; 498 499 power-domain@MT8192_POWER_DOMAIN_CAM_RAWB { 500 reg = <MT8192_POWER_DOMAIN_CAM_RAWB>; 501 clocks = <&camsys_rawb CLK_CAM_RAWB_LARBX>; 502 clock-names = "cam_rawb-0"; 503 #power-domain-cells = <0>; 504 }; 505 506 power-domain@MT8192_POWER_DOMAIN_CAM_RAWC { 507 reg = <MT8192_POWER_DOMAIN_CAM_RAWC>; 508 clocks = <&camsys_rawc CLK_CAM_RAWC_LARBX>; 509 clock-names = "cam_rawc-0"; 510 #power-domain-cells = <0>; 511 }; 512 }; 513 }; 514 }; 515 }; 516 517 watchdog: watchdog@10007000 { 518 compatible = "mediatek,mt8192-wdt"; 519 reg = <0 0x10007000 0 0x100>; 520 #reset-cells = <1>; 521 }; 522 523 apmixedsys: syscon@1000c000 { 524 compatible = "mediatek,mt8192-apmixedsys", "syscon"; 525 reg = <0 0x1000c000 0 0x1000>; 526 #clock-cells = <1>; 527 }; 528 529 systimer: timer@10017000 { 530 compatible = "mediatek,mt8192-timer", 531 "mediatek,mt6765-timer"; 532 reg = <0 0x10017000 0 0x1000>; 533 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH 0>; 534 clocks = <&topckgen CLK_TOP_CSW_F26M_D2>; 535 clock-names = "clk13m"; 536 }; 537 538 pwrap: pwrap@10026000 { 539 compatible = "mediatek,mt6873-pwrap"; 540 reg = <0 0x10026000 0 0x1000>; 541 reg-names = "pwrap"; 542 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 0>; 543 clocks = <&infracfg CLK_INFRA_PMIC_AP>, 544 <&infracfg CLK_INFRA_PMIC_TMR>; 545 clock-names = "spi", "wrap"; 546 assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC_SEL>; 547 assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>; 548 }; 549 550 spmi: spmi@10027000 { 551 compatible = "mediatek,mt6873-spmi"; 552 reg = <0 0x10027000 0 0x000e00>, 553 <0 0x10029000 0 0x000100>; 554 reg-names = "pmif", "spmimst"; 555 clocks = <&infracfg CLK_INFRA_PMIC_AP>, 556 <&infracfg CLK_INFRA_PMIC_TMR>, 557 <&topckgen CLK_TOP_SPMI_MST_SEL>; 558 clock-names = "pmif_sys_ck", 559 "pmif_tmr_ck", 560 "spmimst_clk_mux"; 561 assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC_SEL>; 562 assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>; 563 }; 564 565 gce: mailbox@10228000 { 566 compatible = "mediatek,mt8192-gce"; 567 reg = <0 0x10228000 0 0x4000>; 568 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 0>; 569 #mbox-cells = <2>; 570 clocks = <&infracfg CLK_INFRA_GCE>; 571 clock-names = "gce"; 572 }; 573 574 scp_adsp: clock-controller@10720000 { 575 compatible = "mediatek,mt8192-scp_adsp"; 576 reg = <0 0x10720000 0 0x1000>; 577 #clock-cells = <1>; 578 }; 579 580 uart0: serial@11002000 { 581 compatible = "mediatek,mt8192-uart", 582 "mediatek,mt6577-uart"; 583 reg = <0 0x11002000 0 0x1000>; 584 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>; 585 clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>; 586 clock-names = "baud", "bus"; 587 status = "disabled"; 588 }; 589 590 uart1: serial@11003000 { 591 compatible = "mediatek,mt8192-uart", 592 "mediatek,mt6577-uart"; 593 reg = <0 0x11003000 0 0x1000>; 594 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>; 595 clocks = <&clk26m>, <&infracfg CLK_INFRA_UART1>; 596 clock-names = "baud", "bus"; 597 status = "disabled"; 598 }; 599 600 imp_iic_wrap_c: clock-controller@11007000 { 601 compatible = "mediatek,mt8192-imp_iic_wrap_c"; 602 reg = <0 0x11007000 0 0x1000>; 603 #clock-cells = <1>; 604 }; 605 606 spi0: spi@1100a000 { 607 compatible = "mediatek,mt8192-spi", 608 "mediatek,mt6765-spi"; 609 #address-cells = <1>; 610 #size-cells = <0>; 611 reg = <0 0x1100a000 0 0x1000>; 612 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH 0>; 613 clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 614 <&topckgen CLK_TOP_SPI_SEL>, 615 <&infracfg CLK_INFRA_SPI0>; 616 clock-names = "parent-clk", "sel-clk", "spi-clk"; 617 status = "disabled"; 618 }; 619 620 pwm0: pwm@1100e000 { 621 compatible = "mediatek,mt8183-disp-pwm"; 622 reg = <0 0x1100e000 0 0x1000>; 623 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH 0>; 624 #pwm-cells = <2>; 625 clocks = <&topckgen CLK_TOP_DISP_PWM_SEL>, 626 <&infracfg CLK_INFRA_DISP_PWM>; 627 clock-names = "main", "mm"; 628 status = "disabled"; 629 }; 630 631 spi1: spi@11010000 { 632 compatible = "mediatek,mt8192-spi", 633 "mediatek,mt6765-spi"; 634 #address-cells = <1>; 635 #size-cells = <0>; 636 reg = <0 0x11010000 0 0x1000>; 637 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH 0>; 638 clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 639 <&topckgen CLK_TOP_SPI_SEL>, 640 <&infracfg CLK_INFRA_SPI1>; 641 clock-names = "parent-clk", "sel-clk", "spi-clk"; 642 status = "disabled"; 643 }; 644 645 spi2: spi@11012000 { 646 compatible = "mediatek,mt8192-spi", 647 "mediatek,mt6765-spi"; 648 #address-cells = <1>; 649 #size-cells = <0>; 650 reg = <0 0x11012000 0 0x1000>; 651 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH 0>; 652 clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 653 <&topckgen CLK_TOP_SPI_SEL>, 654 <&infracfg CLK_INFRA_SPI2>; 655 clock-names = "parent-clk", "sel-clk", "spi-clk"; 656 status = "disabled"; 657 }; 658 659 spi3: spi@11013000 { 660 compatible = "mediatek,mt8192-spi", 661 "mediatek,mt6765-spi"; 662 #address-cells = <1>; 663 #size-cells = <0>; 664 reg = <0 0x11013000 0 0x1000>; 665 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH 0>; 666 clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 667 <&topckgen CLK_TOP_SPI_SEL>, 668 <&infracfg CLK_INFRA_SPI3>; 669 clock-names = "parent-clk", "sel-clk", "spi-clk"; 670 status = "disabled"; 671 }; 672 673 spi4: spi@11018000 { 674 compatible = "mediatek,mt8192-spi", 675 "mediatek,mt6765-spi"; 676 #address-cells = <1>; 677 #size-cells = <0>; 678 reg = <0 0x11018000 0 0x1000>; 679 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH 0>; 680 clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 681 <&topckgen CLK_TOP_SPI_SEL>, 682 <&infracfg CLK_INFRA_SPI4>; 683 clock-names = "parent-clk", "sel-clk", "spi-clk"; 684 status = "disabled"; 685 }; 686 687 spi5: spi@11019000 { 688 compatible = "mediatek,mt8192-spi", 689 "mediatek,mt6765-spi"; 690 #address-cells = <1>; 691 #size-cells = <0>; 692 reg = <0 0x11019000 0 0x1000>; 693 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH 0>; 694 clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 695 <&topckgen CLK_TOP_SPI_SEL>, 696 <&infracfg CLK_INFRA_SPI5>; 697 clock-names = "parent-clk", "sel-clk", "spi-clk"; 698 status = "disabled"; 699 }; 700 701 spi6: spi@1101d000 { 702 compatible = "mediatek,mt8192-spi", 703 "mediatek,mt6765-spi"; 704 #address-cells = <1>; 705 #size-cells = <0>; 706 reg = <0 0x1101d000 0 0x1000>; 707 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH 0>; 708 clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 709 <&topckgen CLK_TOP_SPI_SEL>, 710 <&infracfg CLK_INFRA_SPI6>; 711 clock-names = "parent-clk", "sel-clk", "spi-clk"; 712 status = "disabled"; 713 }; 714 715 spi7: spi@1101e000 { 716 compatible = "mediatek,mt8192-spi", 717 "mediatek,mt6765-spi"; 718 #address-cells = <1>; 719 #size-cells = <0>; 720 reg = <0 0x1101e000 0 0x1000>; 721 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH 0>; 722 clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 723 <&topckgen CLK_TOP_SPI_SEL>, 724 <&infracfg CLK_INFRA_SPI7>; 725 clock-names = "parent-clk", "sel-clk", "spi-clk"; 726 status = "disabled"; 727 }; 728 729 scp: scp@10500000 { 730 compatible = "mediatek,mt8192-scp"; 731 reg = <0 0x10500000 0 0x100000>, 732 <0 0x10720000 0 0xe0000>, 733 <0 0x10700000 0 0x8000>; 734 reg-names = "sram", "cfg", "l1tcm"; 735 interrupts = <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH 0>; 736 clocks = <&infracfg CLK_INFRA_SCPSYS>; 737 clock-names = "main"; 738 status = "disabled"; 739 }; 740 741 xhci: usb@11200000 { 742 compatible = "mediatek,mt8192-xhci", 743 "mediatek,mtk-xhci"; 744 reg = <0 0x11200000 0 0x1000>, 745 <0 0x11203e00 0 0x0100>; 746 reg-names = "mac", "ippc"; 747 interrupts-extended = <&gic GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>; 748 interrupt-names = "host"; 749 phys = <&u2port0 PHY_TYPE_USB2>, 750 <&u3port0 PHY_TYPE_USB3>; 751 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_SEL>, 752 <&topckgen CLK_TOP_SSUSB_XHCI_SEL>; 753 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, 754 <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 755 clocks = <&infracfg CLK_INFRA_SSUSB>, 756 <&apmixedsys CLK_APMIXED_USBPLL>, 757 <&clk26m>, 758 <&clk26m>, 759 <&infracfg CLK_INFRA_SSUSB_XHCI>; 760 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", 761 "xhci_ck"; 762 wakeup-source; 763 mediatek,syscon-wakeup = <&pericfg 0x420 102>; 764 status = "disabled"; 765 }; 766 767 audsys: syscon@11210000 { 768 compatible = "mediatek,mt8192-audsys", "syscon"; 769 reg = <0 0x11210000 0 0x2000>; 770 #clock-cells = <1>; 771 772 afe: mt8192-afe-pcm { 773 compatible = "mediatek,mt8192-audio"; 774 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH 0>; 775 resets = <&watchdog 17>; 776 reset-names = "audiosys"; 777 mediatek,apmixedsys = <&apmixedsys>; 778 mediatek,infracfg = <&infracfg>; 779 mediatek,topckgen = <&topckgen>; 780 power-domains = <&spm MT8192_POWER_DOMAIN_AUDIO>; 781 clocks = <&audsys CLK_AUD_AFE>, 782 <&audsys CLK_AUD_DAC>, 783 <&audsys CLK_AUD_DAC_PREDIS>, 784 <&audsys CLK_AUD_ADC>, 785 <&audsys CLK_AUD_ADDA6_ADC>, 786 <&audsys CLK_AUD_22M>, 787 <&audsys CLK_AUD_24M>, 788 <&audsys CLK_AUD_APLL_TUNER>, 789 <&audsys CLK_AUD_APLL2_TUNER>, 790 <&audsys CLK_AUD_TDM>, 791 <&audsys CLK_AUD_TML>, 792 <&audsys CLK_AUD_NLE>, 793 <&audsys CLK_AUD_DAC_HIRES>, 794 <&audsys CLK_AUD_ADC_HIRES>, 795 <&audsys CLK_AUD_ADC_HIRES_TML>, 796 <&audsys CLK_AUD_ADDA6_ADC_HIRES>, 797 <&audsys CLK_AUD_3RD_DAC>, 798 <&audsys CLK_AUD_3RD_DAC_PREDIS>, 799 <&audsys CLK_AUD_3RD_DAC_TML>, 800 <&audsys CLK_AUD_3RD_DAC_HIRES>, 801 <&infracfg CLK_INFRA_AUDIO>, 802 <&infracfg CLK_INFRA_AUDIO_26M_B>, 803 <&topckgen CLK_TOP_AUDIO_SEL>, 804 <&topckgen CLK_TOP_AUD_INTBUS_SEL>, 805 <&topckgen CLK_TOP_MAINPLL_D4_D4>, 806 <&topckgen CLK_TOP_AUD_1_SEL>, 807 <&topckgen CLK_TOP_APLL1>, 808 <&topckgen CLK_TOP_AUD_2_SEL>, 809 <&topckgen CLK_TOP_APLL2>, 810 <&topckgen CLK_TOP_AUD_ENGEN1_SEL>, 811 <&topckgen CLK_TOP_APLL1_D4>, 812 <&topckgen CLK_TOP_AUD_ENGEN2_SEL>, 813 <&topckgen CLK_TOP_APLL2_D4>, 814 <&topckgen CLK_TOP_APLL_I2S0_M_SEL>, 815 <&topckgen CLK_TOP_APLL_I2S1_M_SEL>, 816 <&topckgen CLK_TOP_APLL_I2S2_M_SEL>, 817 <&topckgen CLK_TOP_APLL_I2S3_M_SEL>, 818 <&topckgen CLK_TOP_APLL_I2S4_M_SEL>, 819 <&topckgen CLK_TOP_APLL_I2S5_M_SEL>, 820 <&topckgen CLK_TOP_APLL_I2S6_M_SEL>, 821 <&topckgen CLK_TOP_APLL_I2S7_M_SEL>, 822 <&topckgen CLK_TOP_APLL_I2S8_M_SEL>, 823 <&topckgen CLK_TOP_APLL_I2S9_M_SEL>, 824 <&topckgen CLK_TOP_APLL12_DIV0>, 825 <&topckgen CLK_TOP_APLL12_DIV1>, 826 <&topckgen CLK_TOP_APLL12_DIV2>, 827 <&topckgen CLK_TOP_APLL12_DIV3>, 828 <&topckgen CLK_TOP_APLL12_DIV4>, 829 <&topckgen CLK_TOP_APLL12_DIVB>, 830 <&topckgen CLK_TOP_APLL12_DIV5>, 831 <&topckgen CLK_TOP_APLL12_DIV6>, 832 <&topckgen CLK_TOP_APLL12_DIV7>, 833 <&topckgen CLK_TOP_APLL12_DIV8>, 834 <&topckgen CLK_TOP_APLL12_DIV9>, 835 <&topckgen CLK_TOP_AUDIO_H_SEL>, 836 <&clk26m>; 837 clock-names = "aud_afe_clk", 838 "aud_dac_clk", 839 "aud_dac_predis_clk", 840 "aud_adc_clk", 841 "aud_adda6_adc_clk", 842 "aud_apll22m_clk", 843 "aud_apll24m_clk", 844 "aud_apll1_tuner_clk", 845 "aud_apll2_tuner_clk", 846 "aud_tdm_clk", 847 "aud_tml_clk", 848 "aud_nle", 849 "aud_dac_hires_clk", 850 "aud_adc_hires_clk", 851 "aud_adc_hires_tml", 852 "aud_adda6_adc_hires_clk", 853 "aud_3rd_dac_clk", 854 "aud_3rd_dac_predis_clk", 855 "aud_3rd_dac_tml", 856 "aud_3rd_dac_hires_clk", 857 "aud_infra_clk", 858 "aud_infra_26m_clk", 859 "top_mux_audio", 860 "top_mux_audio_int", 861 "top_mainpll_d4_d4", 862 "top_mux_aud_1", 863 "top_apll1_ck", 864 "top_mux_aud_2", 865 "top_apll2_ck", 866 "top_mux_aud_eng1", 867 "top_apll1_d4", 868 "top_mux_aud_eng2", 869 "top_apll2_d4", 870 "top_i2s0_m_sel", 871 "top_i2s1_m_sel", 872 "top_i2s2_m_sel", 873 "top_i2s3_m_sel", 874 "top_i2s4_m_sel", 875 "top_i2s5_m_sel", 876 "top_i2s6_m_sel", 877 "top_i2s7_m_sel", 878 "top_i2s8_m_sel", 879 "top_i2s9_m_sel", 880 "top_apll12_div0", 881 "top_apll12_div1", 882 "top_apll12_div2", 883 "top_apll12_div3", 884 "top_apll12_div4", 885 "top_apll12_divb", 886 "top_apll12_div5", 887 "top_apll12_div6", 888 "top_apll12_div7", 889 "top_apll12_div8", 890 "top_apll12_div9", 891 "top_mux_audio_h", 892 "top_clk26m_clk"; 893 }; 894 }; 895 896 pcie: pcie@11230000 { 897 compatible = "mediatek,mt8192-pcie"; 898 device_type = "pci"; 899 reg = <0 0x11230000 0 0x2000>; 900 reg-names = "pcie-mac"; 901 #address-cells = <3>; 902 #size-cells = <2>; 903 clocks = <&infracfg CLK_INFRA_PCIE_PL_P_250M>, 904 <&infracfg CLK_INFRA_PCIE_TL_26M>, 905 <&infracfg CLK_INFRA_PCIE_TL_96M>, 906 <&infracfg CLK_INFRA_PCIE_TL_32K>, 907 <&infracfg CLK_INFRA_PCIE_PERI_26M>, 908 <&infracfg CLK_INFRA_PCIE_TOP_H_133M>; 909 clock-names = "pl_250m", "tl_26m", "tl_96m", 910 "tl_32k", "peri_26m", "top_133m"; 911 assigned-clocks = <&topckgen CLK_TOP_TL_SEL>; 912 assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D6_D4>; 913 interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0>; 914 bus-range = <0x00 0xff>; 915 ranges = <0x82000000 0 0x12000000 0x0 0x12000000 0 0x0800000>, 916 <0x81000000 0 0x12800000 0x0 0x12800000 0 0x0800000>; 917 #interrupt-cells = <1>; 918 interrupt-map-mask = <0 0 0 7>; 919 interrupt-map = <0 0 0 1 &pcie_intc0 0>, 920 <0 0 0 2 &pcie_intc0 1>, 921 <0 0 0 3 &pcie_intc0 2>, 922 <0 0 0 4 &pcie_intc0 3>; 923 924 pcie_intc0: interrupt-controller { 925 interrupt-controller; 926 #address-cells = <0>; 927 #interrupt-cells = <1>; 928 }; 929 }; 930 931 nor_flash: spi@11234000 { 932 compatible = "mediatek,mt8192-nor"; 933 reg = <0 0x11234000 0 0xe0>; 934 interrupts = <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH 0>; 935 clocks = <&topckgen CLK_TOP_SFLASH_SEL>, 936 <&infracfg CLK_INFRA_FLASHIF_SFLASH>, 937 <&infracfg CLK_INFRA_FLASHIF_TOP_H_133M>; 938 clock-names = "spi", "sf", "axi"; 939 assigned-clocks = <&topckgen CLK_TOP_SFLASH_SEL>; 940 assigned-clock-parents = <&clk26m>; 941 #address-cells = <1>; 942 #size-cells = <0>; 943 status = "disabled"; 944 }; 945 946 efuse: efuse@11c10000 { 947 compatible = "mediatek,mt8192-efuse", "mediatek,efuse"; 948 reg = <0 0x11c10000 0 0x1000>; 949 #address-cells = <1>; 950 #size-cells = <1>; 951 952 lvts_e_data1: data1@1c0 { 953 reg = <0x1c0 0x58>; 954 }; 955 956 svs_calibration: calib@580 { 957 reg = <0x580 0x68>; 958 }; 959 }; 960 961 i2c3: i2c@11cb0000 { 962 compatible = "mediatek,mt8192-i2c"; 963 reg = <0 0x11cb0000 0 0x1000>, 964 <0 0x10217300 0 0x80>; 965 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>; 966 clocks = <&imp_iic_wrap_e CLK_IMP_IIC_WRAP_E_I2C3>, 967 <&infracfg CLK_INFRA_AP_DMA>; 968 clock-names = "main", "dma"; 969 clock-div = <1>; 970 #address-cells = <1>; 971 #size-cells = <0>; 972 status = "disabled"; 973 }; 974 975 imp_iic_wrap_e: clock-controller@11cb1000 { 976 compatible = "mediatek,mt8192-imp_iic_wrap_e"; 977 reg = <0 0x11cb1000 0 0x1000>; 978 #clock-cells = <1>; 979 }; 980 981 i2c7: i2c@11d00000 { 982 compatible = "mediatek,mt8192-i2c"; 983 reg = <0 0x11d00000 0 0x1000>, 984 <0 0x10217600 0 0x180>; 985 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>; 986 clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C7>, 987 <&infracfg CLK_INFRA_AP_DMA>; 988 clock-names = "main", "dma"; 989 clock-div = <1>; 990 #address-cells = <1>; 991 #size-cells = <0>; 992 status = "disabled"; 993 }; 994 995 i2c8: i2c@11d01000 { 996 compatible = "mediatek,mt8192-i2c"; 997 reg = <0 0x11d01000 0 0x1000>, 998 <0 0x10217780 0 0x180>; 999 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>; 1000 clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C8>, 1001 <&infracfg CLK_INFRA_AP_DMA>; 1002 clock-names = "main", "dma"; 1003 clock-div = <1>; 1004 #address-cells = <1>; 1005 #size-cells = <0>; 1006 status = "disabled"; 1007 }; 1008 1009 i2c9: i2c@11d02000 { 1010 compatible = "mediatek,mt8192-i2c"; 1011 reg = <0 0x11d02000 0 0x1000>, 1012 <0 0x10217900 0 0x180>; 1013 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH 0>; 1014 clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C9>, 1015 <&infracfg CLK_INFRA_AP_DMA>; 1016 clock-names = "main", "dma"; 1017 clock-div = <1>; 1018 #address-cells = <1>; 1019 #size-cells = <0>; 1020 status = "disabled"; 1021 }; 1022 1023 imp_iic_wrap_s: clock-controller@11d03000 { 1024 compatible = "mediatek,mt8192-imp_iic_wrap_s"; 1025 reg = <0 0x11d03000 0 0x1000>; 1026 #clock-cells = <1>; 1027 }; 1028 1029 i2c1: i2c@11d20000 { 1030 compatible = "mediatek,mt8192-i2c"; 1031 reg = <0 0x11d20000 0 0x1000>, 1032 <0 0x10217100 0 0x80>; 1033 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>; 1034 clocks = <&imp_iic_wrap_ws CLK_IMP_IIC_WRAP_WS_I2C1>, 1035 <&infracfg CLK_INFRA_AP_DMA>; 1036 clock-names = "main", "dma"; 1037 clock-div = <1>; 1038 #address-cells = <1>; 1039 #size-cells = <0>; 1040 status = "disabled"; 1041 }; 1042 1043 i2c2: i2c@11d21000 { 1044 compatible = "mediatek,mt8192-i2c"; 1045 reg = <0 0x11d21000 0 0x1000>, 1046 <0 0x10217180 0 0x180>; 1047 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>; 1048 clocks = <&imp_iic_wrap_ws CLK_IMP_IIC_WRAP_WS_I2C2>, 1049 <&infracfg CLK_INFRA_AP_DMA>; 1050 clock-names = "main", "dma"; 1051 clock-div = <1>; 1052 #address-cells = <1>; 1053 #size-cells = <0>; 1054 status = "disabled"; 1055 }; 1056 1057 i2c4: i2c@11d22000 { 1058 compatible = "mediatek,mt8192-i2c"; 1059 reg = <0 0x11d22000 0 0x1000>, 1060 <0 0x10217380 0 0x180>; 1061 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>; 1062 clocks = <&imp_iic_wrap_ws CLK_IMP_IIC_WRAP_WS_I2C4>, 1063 <&infracfg CLK_INFRA_AP_DMA>; 1064 clock-names = "main", "dma"; 1065 clock-div = <1>; 1066 #address-cells = <1>; 1067 #size-cells = <0>; 1068 status = "disabled"; 1069 }; 1070 1071 imp_iic_wrap_ws: clock-controller@11d23000 { 1072 compatible = "mediatek,mt8192-imp_iic_wrap_ws"; 1073 reg = <0 0x11d23000 0 0x1000>; 1074 #clock-cells = <1>; 1075 }; 1076 1077 i2c5: i2c@11e00000 { 1078 compatible = "mediatek,mt8192-i2c"; 1079 reg = <0 0x11e00000 0 0x1000>, 1080 <0 0x10217500 0 0x80>; 1081 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>; 1082 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C5>, 1083 <&infracfg CLK_INFRA_AP_DMA>; 1084 clock-names = "main", "dma"; 1085 clock-div = <1>; 1086 #address-cells = <1>; 1087 #size-cells = <0>; 1088 status = "disabled"; 1089 }; 1090 1091 imp_iic_wrap_w: clock-controller@11e01000 { 1092 compatible = "mediatek,mt8192-imp_iic_wrap_w"; 1093 reg = <0 0x11e01000 0 0x1000>; 1094 #clock-cells = <1>; 1095 }; 1096 1097 u3phy0: t-phy@11e40000 { 1098 compatible = "mediatek,mt8192-tphy", 1099 "mediatek,generic-tphy-v2"; 1100 #address-cells = <1>; 1101 #size-cells = <1>; 1102 ranges = <0x0 0x0 0x11e40000 0x1000>; 1103 1104 u2port0: usb-phy@0 { 1105 reg = <0x0 0x700>; 1106 clocks = <&clk26m>; 1107 clock-names = "ref"; 1108 #phy-cells = <1>; 1109 }; 1110 1111 u3port0: usb-phy@700 { 1112 reg = <0x700 0x900>; 1113 clocks = <&clk26m>; 1114 clock-names = "ref"; 1115 #phy-cells = <1>; 1116 }; 1117 }; 1118 1119 mipi_tx0: dsi-phy@11e50000 { 1120 compatible = "mediatek,mt8183-mipi-tx"; 1121 reg = <0 0x11e50000 0 0x1000>; 1122 clocks = <&apmixedsys CLK_APMIXED_MIPID26M>; 1123 #clock-cells = <0>; 1124 #phy-cells = <0>; 1125 clock-output-names = "mipi_tx0_pll"; 1126 status = "disabled"; 1127 }; 1128 1129 i2c0: i2c@11f00000 { 1130 compatible = "mediatek,mt8192-i2c"; 1131 reg = <0 0x11f00000 0 0x1000>, 1132 <0 0x10217080 0 0x80>; 1133 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH 0>; 1134 clocks = <&imp_iic_wrap_n CLK_IMP_IIC_WRAP_N_I2C0>, 1135 <&infracfg CLK_INFRA_AP_DMA>; 1136 clock-names = "main", "dma"; 1137 clock-div = <1>; 1138 #address-cells = <1>; 1139 #size-cells = <0>; 1140 status = "disabled"; 1141 }; 1142 1143 i2c6: i2c@11f01000 { 1144 compatible = "mediatek,mt8192-i2c"; 1145 reg = <0 0x11f01000 0 0x1000>, 1146 <0 0x10217580 0 0x80>; 1147 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>; 1148 clocks = <&imp_iic_wrap_n CLK_IMP_IIC_WRAP_N_I2C6>, 1149 <&infracfg CLK_INFRA_AP_DMA>; 1150 clock-names = "main", "dma"; 1151 clock-div = <1>; 1152 #address-cells = <1>; 1153 #size-cells = <0>; 1154 status = "disabled"; 1155 }; 1156 1157 imp_iic_wrap_n: clock-controller@11f02000 { 1158 compatible = "mediatek,mt8192-imp_iic_wrap_n"; 1159 reg = <0 0x11f02000 0 0x1000>; 1160 #clock-cells = <1>; 1161 }; 1162 1163 msdc_top: clock-controller@11f10000 { 1164 compatible = "mediatek,mt8192-msdc_top"; 1165 reg = <0 0x11f10000 0 0x1000>; 1166 #clock-cells = <1>; 1167 }; 1168 1169 mmc0: mmc@11f60000 { 1170 compatible = "mediatek,mt8192-mmc", "mediatek,mt8183-mmc"; 1171 reg = <0 0x11f60000 0 0x1000>, <0 0x11f50000 0 0x1000>; 1172 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>; 1173 clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>, 1174 <&msdc_top CLK_MSDC_TOP_H_MST_0P>, 1175 <&msdc_top CLK_MSDC_TOP_SRC_0P>, 1176 <&msdc_top CLK_MSDC_TOP_P_CFG>, 1177 <&msdc_top CLK_MSDC_TOP_P_MSDC0>, 1178 <&msdc_top CLK_MSDC_TOP_AXI>, 1179 <&msdc_top CLK_MSDC_TOP_AHB2AXI_BRG_AXI>; 1180 clock-names = "source", "hclk", "source_cg", "sys_cg", 1181 "pclk_cg", "axi_cg", "ahb_cg"; 1182 status = "disabled"; 1183 }; 1184 1185 mmc1: mmc@11f70000 { 1186 compatible = "mediatek,mt8192-mmc", "mediatek,mt8183-mmc"; 1187 reg = <0 0x11f70000 0 0x1000>, <0 0x11c70000 0 0x1000>; 1188 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>; 1189 clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>, 1190 <&msdc_top CLK_MSDC_TOP_H_MST_1P>, 1191 <&msdc_top CLK_MSDC_TOP_SRC_1P>, 1192 <&msdc_top CLK_MSDC_TOP_P_CFG>, 1193 <&msdc_top CLK_MSDC_TOP_P_MSDC1>, 1194 <&msdc_top CLK_MSDC_TOP_AXI>, 1195 <&msdc_top CLK_MSDC_TOP_AHB2AXI_BRG_AXI>; 1196 clock-names = "source", "hclk", "source_cg", "sys_cg", 1197 "pclk_cg", "axi_cg", "ahb_cg"; 1198 status = "disabled"; 1199 }; 1200 1201 mfgcfg: clock-controller@13fbf000 { 1202 compatible = "mediatek,mt8192-mfgcfg"; 1203 reg = <0 0x13fbf000 0 0x1000>; 1204 #clock-cells = <1>; 1205 }; 1206 1207 mmsys: syscon@14000000 { 1208 compatible = "mediatek,mt8192-mmsys", "syscon"; 1209 reg = <0 0x14000000 0 0x1000>; 1210 #clock-cells = <1>; 1211 #reset-cells = <1>; 1212 mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>, 1213 <&gce 1 CMDQ_THR_PRIO_HIGHEST>; 1214 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>; 1215 }; 1216 1217 mutex: mutex@14001000 { 1218 compatible = "mediatek,mt8192-disp-mutex"; 1219 reg = <0 0x14001000 0 0x1000>; 1220 interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>; 1221 clocks = <&mmsys CLK_MM_DISP_MUTEX0>; 1222 mediatek,gce-events = <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_0>, 1223 <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_1>; 1224 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1225 }; 1226 1227 smi_common: smi@14002000 { 1228 compatible = "mediatek,mt8192-smi-common"; 1229 reg = <0 0x14002000 0 0x1000>; 1230 clocks = <&mmsys CLK_MM_SMI_COMMON>, 1231 <&mmsys CLK_MM_SMI_INFRA>, 1232 <&mmsys CLK_MM_SMI_GALS>, 1233 <&mmsys CLK_MM_SMI_GALS>; 1234 clock-names = "apb", "smi", "gals0", "gals1"; 1235 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1236 }; 1237 1238 larb0: larb@14003000 { 1239 compatible = "mediatek,mt8192-smi-larb"; 1240 reg = <0 0x14003000 0 0x1000>; 1241 mediatek,larb-id = <0>; 1242 mediatek,smi = <&smi_common>; 1243 clocks = <&clk26m>, <&clk26m>; 1244 clock-names = "apb", "smi"; 1245 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1246 }; 1247 1248 larb1: larb@14004000 { 1249 compatible = "mediatek,mt8192-smi-larb"; 1250 reg = <0 0x14004000 0 0x1000>; 1251 mediatek,larb-id = <1>; 1252 mediatek,smi = <&smi_common>; 1253 clocks = <&clk26m>, <&clk26m>; 1254 clock-names = "apb", "smi"; 1255 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1256 }; 1257 1258 ovl0: ovl@14005000 { 1259 compatible = "mediatek,mt8192-disp-ovl"; 1260 reg = <0 0x14005000 0 0x1000>; 1261 interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH 0>; 1262 clocks = <&mmsys CLK_MM_DISP_OVL0>; 1263 iommus = <&iommu0 M4U_PORT_L0_OVL_RDMA0>, 1264 <&iommu0 M4U_PORT_L0_OVL_RDMA0_HDR>; 1265 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1266 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>; 1267 }; 1268 1269 ovl_2l0: ovl@14006000 { 1270 compatible = "mediatek,mt8192-disp-ovl-2l"; 1271 reg = <0 0x14006000 0 0x1000>; 1272 interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH 0>; 1273 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1274 clocks = <&mmsys CLK_MM_DISP_OVL0_2L>; 1275 iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0>, 1276 <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0_HDR>; 1277 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>; 1278 }; 1279 1280 rdma0: rdma@14007000 { 1281 compatible = "mediatek,mt8192-disp-rdma", 1282 "mediatek,mt8183-disp-rdma"; 1283 reg = <0 0x14007000 0 0x1000>; 1284 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH 0>; 1285 clocks = <&mmsys CLK_MM_DISP_RDMA0>; 1286 iommus = <&iommu0 M4U_PORT_L0_DISP_RDMA0>; 1287 mediatek,rdma-fifo-size = <5120>; 1288 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1289 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x7000 0x1000>; 1290 }; 1291 1292 color0: color@14009000 { 1293 compatible = "mediatek,mt8192-disp-color", 1294 "mediatek,mt8173-disp-color"; 1295 reg = <0 0x14009000 0 0x1000>; 1296 interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>; 1297 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1298 clocks = <&mmsys CLK_MM_DISP_COLOR0>; 1299 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>; 1300 }; 1301 1302 ccorr0: ccorr@1400a000 { 1303 compatible = "mediatek,mt8192-disp-ccorr"; 1304 reg = <0 0x1400a000 0 0x1000>; 1305 interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>; 1306 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1307 clocks = <&mmsys CLK_MM_DISP_CCORR0>; 1308 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>; 1309 }; 1310 1311 aal0: aal@1400b000 { 1312 compatible = "mediatek,mt8192-disp-aal", 1313 "mediatek,mt8183-disp-aal"; 1314 reg = <0 0x1400b000 0 0x1000>; 1315 interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>; 1316 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1317 clocks = <&mmsys CLK_MM_DISP_AAL0>; 1318 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>; 1319 }; 1320 1321 gamma0: gamma@1400c000 { 1322 compatible = "mediatek,mt8192-disp-gamma", 1323 "mediatek,mt8183-disp-gamma"; 1324 reg = <0 0x1400c000 0 0x1000>; 1325 interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>; 1326 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1327 clocks = <&mmsys CLK_MM_DISP_GAMMA0>; 1328 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>; 1329 }; 1330 1331 postmask0: postmask@1400d000 { 1332 compatible = "mediatek,mt8192-disp-postmask"; 1333 reg = <0 0x1400d000 0 0x1000>; 1334 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>; 1335 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1336 clocks = <&mmsys CLK_MM_DISP_POSTMASK0>; 1337 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>; 1338 }; 1339 1340 dither0: dither@1400e000 { 1341 compatible = "mediatek,mt8192-disp-dither", 1342 "mediatek,mt8183-disp-dither"; 1343 reg = <0 0x1400e000 0 0x1000>; 1344 interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>; 1345 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1346 clocks = <&mmsys CLK_MM_DISP_DITHER0>; 1347 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>; 1348 }; 1349 1350 dsi0: dsi@14010000 { 1351 compatible = "mediatek,mt8183-dsi"; 1352 reg = <0 0x14010000 0 0x1000>; 1353 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>; 1354 clocks = <&mmsys CLK_MM_DSI0>, 1355 <&mmsys CLK_MM_DSI_DSI0>, 1356 <&mipi_tx0>; 1357 clock-names = "engine", "digital", "hs"; 1358 phys = <&mipi_tx0>; 1359 phy-names = "dphy"; 1360 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1361 resets = <&mmsys MT8192_MMSYS_SW0_RST_B_DISP_DSI0>; 1362 status = "disabled"; 1363 1364 port { 1365 dsi_out: endpoint { }; 1366 }; 1367 }; 1368 1369 ovl_2l2: ovl@14014000 { 1370 compatible = "mediatek,mt8192-disp-ovl-2l"; 1371 reg = <0 0x14014000 0 0x1000>; 1372 interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH 0>; 1373 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1374 clocks = <&mmsys CLK_MM_DISP_OVL2_2L>; 1375 iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2>, 1376 <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2_HDR>; 1377 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x4000 0x1000>; 1378 }; 1379 1380 rdma4: rdma@14015000 { 1381 compatible = "mediatek,mt8192-disp-rdma", 1382 "mediatek,mt8183-disp-rdma"; 1383 reg = <0 0x14015000 0 0x1000>; 1384 interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH 0>; 1385 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1386 clocks = <&mmsys CLK_MM_DISP_RDMA4>; 1387 iommus = <&iommu0 M4U_PORT_L1_DISP_RDMA4>; 1388 mediatek,rdma-fifo-size = <2048>; 1389 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>; 1390 }; 1391 1392 dpi0: dpi@14016000 { 1393 compatible = "mediatek,mt8192-dpi"; 1394 reg = <0 0x14016000 0 0x1000>; 1395 interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH 0>; 1396 clocks = <&mmsys CLK_MM_DPI_DPI0>, 1397 <&mmsys CLK_MM_DISP_DPI0>, 1398 <&apmixedsys CLK_APMIXED_TVDPLL>; 1399 clock-names = "pixel", "engine", "pll"; 1400 status = "disabled"; 1401 }; 1402 1403 iommu0: m4u@1401d000 { 1404 compatible = "mediatek,mt8192-m4u"; 1405 reg = <0 0x1401d000 0 0x1000>; 1406 mediatek,larbs = <&larb0>, <&larb1>, <&larb2>, 1407 <&larb4>, <&larb5>, <&larb7>, 1408 <&larb9>, <&larb11>, <&larb13>, 1409 <&larb14>, <&larb16>, <&larb17>, 1410 <&larb18>, <&larb19>, <&larb20>; 1411 interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH 0>; 1412 clocks = <&mmsys CLK_MM_SMI_IOMMU>; 1413 clock-names = "bclk"; 1414 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1415 #iommu-cells = <1>; 1416 }; 1417 1418 imgsys: clock-controller@15020000 { 1419 compatible = "mediatek,mt8192-imgsys"; 1420 reg = <0 0x15020000 0 0x1000>; 1421 #clock-cells = <1>; 1422 }; 1423 1424 larb9: larb@1502e000 { 1425 compatible = "mediatek,mt8192-smi-larb"; 1426 reg = <0 0x1502e000 0 0x1000>; 1427 mediatek,larb-id = <9>; 1428 mediatek,smi = <&smi_common>; 1429 clocks = <&imgsys CLK_IMG_LARB9>, 1430 <&imgsys CLK_IMG_LARB9>; 1431 clock-names = "apb", "smi"; 1432 power-domains = <&spm MT8192_POWER_DOMAIN_ISP>; 1433 }; 1434 1435 imgsys2: clock-controller@15820000 { 1436 compatible = "mediatek,mt8192-imgsys2"; 1437 reg = <0 0x15820000 0 0x1000>; 1438 #clock-cells = <1>; 1439 }; 1440 1441 larb11: larb@1582e000 { 1442 compatible = "mediatek,mt8192-smi-larb"; 1443 reg = <0 0x1582e000 0 0x1000>; 1444 mediatek,larb-id = <11>; 1445 mediatek,smi = <&smi_common>; 1446 clocks = <&imgsys2 CLK_IMG2_LARB11>, 1447 <&imgsys2 CLK_IMG2_LARB11>; 1448 clock-names = "apb", "smi"; 1449 power-domains = <&spm MT8192_POWER_DOMAIN_ISP2>; 1450 }; 1451 1452 larb5: larb@1600d000 { 1453 compatible = "mediatek,mt8192-smi-larb"; 1454 reg = <0 0x1600d000 0 0x1000>; 1455 mediatek,larb-id = <5>; 1456 mediatek,smi = <&smi_common>; 1457 clocks = <&vdecsys_soc CLK_VDEC_SOC_LARB1>, 1458 <&vdecsys_soc CLK_VDEC_SOC_LARB1>; 1459 clock-names = "apb", "smi"; 1460 power-domains = <&spm MT8192_POWER_DOMAIN_VDEC>; 1461 }; 1462 1463 vdecsys_soc: clock-controller@1600f000 { 1464 compatible = "mediatek,mt8192-vdecsys_soc"; 1465 reg = <0 0x1600f000 0 0x1000>; 1466 #clock-cells = <1>; 1467 }; 1468 1469 larb4: larb@1602e000 { 1470 compatible = "mediatek,mt8192-smi-larb"; 1471 reg = <0 0x1602e000 0 0x1000>; 1472 mediatek,larb-id = <4>; 1473 mediatek,smi = <&smi_common>; 1474 clocks = <&vdecsys CLK_VDEC_SOC_LARB1>, 1475 <&vdecsys CLK_VDEC_SOC_LARB1>; 1476 clock-names = "apb", "smi"; 1477 power-domains = <&spm MT8192_POWER_DOMAIN_VDEC2>; 1478 }; 1479 1480 vdecsys: clock-controller@1602f000 { 1481 compatible = "mediatek,mt8192-vdecsys"; 1482 reg = <0 0x1602f000 0 0x1000>; 1483 #clock-cells = <1>; 1484 }; 1485 1486 vencsys: clock-controller@17000000 { 1487 compatible = "mediatek,mt8192-vencsys"; 1488 reg = <0 0x17000000 0 0x1000>; 1489 #clock-cells = <1>; 1490 }; 1491 1492 larb7: larb@17010000 { 1493 compatible = "mediatek,mt8192-smi-larb"; 1494 reg = <0 0x17010000 0 0x1000>; 1495 mediatek,larb-id = <7>; 1496 mediatek,smi = <&smi_common>; 1497 clocks = <&vencsys CLK_VENC_SET0_LARB>, 1498 <&vencsys CLK_VENC_SET1_VENC>; 1499 clock-names = "apb", "smi"; 1500 power-domains = <&spm MT8192_POWER_DOMAIN_VENC>; 1501 }; 1502 1503 vcodec_enc: vcodec@17020000 { 1504 compatible = "mediatek,mt8192-vcodec-enc"; 1505 reg = <0 0x17020000 0 0x2000>; 1506 iommus = <&iommu0 M4U_PORT_L7_VENC_RCPU>, 1507 <&iommu0 M4U_PORT_L7_VENC_REC>, 1508 <&iommu0 M4U_PORT_L7_VENC_BSDMA>, 1509 <&iommu0 M4U_PORT_L7_VENC_SV_COMV>, 1510 <&iommu0 M4U_PORT_L7_VENC_RD_COMV>, 1511 <&iommu0 M4U_PORT_L7_VENC_CUR_LUMA>, 1512 <&iommu0 M4U_PORT_L7_VENC_CUR_CHROMA>, 1513 <&iommu0 M4U_PORT_L7_VENC_REF_LUMA>, 1514 <&iommu0 M4U_PORT_L7_VENC_REF_CHROMA>, 1515 <&iommu0 M4U_PORT_L7_VENC_SUB_R_LUMA>, 1516 <&iommu0 M4U_PORT_L7_VENC_SUB_W_LUMA>; 1517 interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH 0>; 1518 mediatek,scp = <&scp>; 1519 power-domains = <&spm MT8192_POWER_DOMAIN_VENC>; 1520 clocks = <&vencsys CLK_VENC_SET1_VENC>; 1521 clock-names = "venc-set1"; 1522 assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>; 1523 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>; 1524 }; 1525 1526 camsys: clock-controller@1a000000 { 1527 compatible = "mediatek,mt8192-camsys"; 1528 reg = <0 0x1a000000 0 0x1000>; 1529 #clock-cells = <1>; 1530 }; 1531 1532 larb13: larb@1a001000 { 1533 compatible = "mediatek,mt8192-smi-larb"; 1534 reg = <0 0x1a001000 0 0x1000>; 1535 mediatek,larb-id = <13>; 1536 mediatek,smi = <&smi_common>; 1537 clocks = <&camsys CLK_CAM_CAM>, 1538 <&camsys CLK_CAM_LARB13>; 1539 clock-names = "apb", "smi"; 1540 power-domains = <&spm MT8192_POWER_DOMAIN_CAM>; 1541 }; 1542 1543 larb14: larb@1a002000 { 1544 compatible = "mediatek,mt8192-smi-larb"; 1545 reg = <0 0x1a002000 0 0x1000>; 1546 mediatek,larb-id = <14>; 1547 mediatek,smi = <&smi_common>; 1548 clocks = <&camsys CLK_CAM_CAM>, 1549 <&camsys CLK_CAM_LARB14>; 1550 clock-names = "apb", "smi"; 1551 power-domains = <&spm MT8192_POWER_DOMAIN_CAM>; 1552 }; 1553 1554 larb16: larb@1a00f000 { 1555 compatible = "mediatek,mt8192-smi-larb"; 1556 reg = <0 0x1a00f000 0 0x1000>; 1557 mediatek,larb-id = <16>; 1558 mediatek,smi = <&smi_common>; 1559 clocks = <&camsys_rawa CLK_CAM_RAWA_CAM>, 1560 <&camsys_rawa CLK_CAM_RAWA_LARBX>; 1561 clock-names = "apb", "smi"; 1562 power-domains = <&spm MT8192_POWER_DOMAIN_CAM_RAWA>; 1563 }; 1564 1565 larb17: larb@1a010000 { 1566 compatible = "mediatek,mt8192-smi-larb"; 1567 reg = <0 0x1a010000 0 0x1000>; 1568 mediatek,larb-id = <17>; 1569 mediatek,smi = <&smi_common>; 1570 clocks = <&camsys_rawb CLK_CAM_RAWB_CAM>, 1571 <&camsys_rawb CLK_CAM_RAWB_LARBX>; 1572 clock-names = "apb", "smi"; 1573 power-domains = <&spm MT8192_POWER_DOMAIN_CAM_RAWB>; 1574 }; 1575 1576 larb18: larb@1a011000 { 1577 compatible = "mediatek,mt8192-smi-larb"; 1578 reg = <0 0x1a011000 0 0x1000>; 1579 mediatek,larb-id = <18>; 1580 mediatek,smi = <&smi_common>; 1581 clocks = <&camsys_rawc CLK_CAM_RAWC_LARBX>, 1582 <&camsys_rawc CLK_CAM_RAWC_CAM>; 1583 clock-names = "apb", "smi"; 1584 power-domains = <&spm MT8192_POWER_DOMAIN_CAM_RAWC>; 1585 }; 1586 1587 camsys_rawa: clock-controller@1a04f000 { 1588 compatible = "mediatek,mt8192-camsys_rawa"; 1589 reg = <0 0x1a04f000 0 0x1000>; 1590 #clock-cells = <1>; 1591 }; 1592 1593 camsys_rawb: clock-controller@1a06f000 { 1594 compatible = "mediatek,mt8192-camsys_rawb"; 1595 reg = <0 0x1a06f000 0 0x1000>; 1596 #clock-cells = <1>; 1597 }; 1598 1599 camsys_rawc: clock-controller@1a08f000 { 1600 compatible = "mediatek,mt8192-camsys_rawc"; 1601 reg = <0 0x1a08f000 0 0x1000>; 1602 #clock-cells = <1>; 1603 }; 1604 1605 ipesys: clock-controller@1b000000 { 1606 compatible = "mediatek,mt8192-ipesys"; 1607 reg = <0 0x1b000000 0 0x1000>; 1608 #clock-cells = <1>; 1609 }; 1610 1611 larb20: larb@1b00f000 { 1612 compatible = "mediatek,mt8192-smi-larb"; 1613 reg = <0 0x1b00f000 0 0x1000>; 1614 mediatek,larb-id = <20>; 1615 mediatek,smi = <&smi_common>; 1616 clocks = <&ipesys CLK_IPE_SMI_SUBCOM>, 1617 <&ipesys CLK_IPE_LARB20>; 1618 clock-names = "apb", "smi"; 1619 power-domains = <&spm MT8192_POWER_DOMAIN_IPE>; 1620 }; 1621 1622 larb19: larb@1b10f000 { 1623 compatible = "mediatek,mt8192-smi-larb"; 1624 reg = <0 0x1b10f000 0 0x1000>; 1625 mediatek,larb-id = <19>; 1626 mediatek,smi = <&smi_common>; 1627 clocks = <&ipesys CLK_IPE_SMI_SUBCOM>, 1628 <&ipesys CLK_IPE_LARB19>; 1629 clock-names = "apb", "smi"; 1630 power-domains = <&spm MT8192_POWER_DOMAIN_IPE>; 1631 }; 1632 1633 mdpsys: clock-controller@1f000000 { 1634 compatible = "mediatek,mt8192-mdpsys"; 1635 reg = <0 0x1f000000 0 0x1000>; 1636 #clock-cells = <1>; 1637 }; 1638 1639 larb2: larb@1f002000 { 1640 compatible = "mediatek,mt8192-smi-larb"; 1641 reg = <0 0x1f002000 0 0x1000>; 1642 mediatek,larb-id = <2>; 1643 mediatek,smi = <&smi_common>; 1644 clocks = <&mdpsys CLK_MDP_SMI0>, 1645 <&mdpsys CLK_MDP_SMI0>; 1646 clock-names = "apb", "smi"; 1647 power-domains = <&spm MT8192_POWER_DOMAIN_MDP>; 1648 }; 1649 }; 1650}; 1651