mt8186.dtsi (d93618da6b6d453c6a9684a3460ffd51b9b4ef2e) mt8186.dtsi (ce459b1da752cf1dc0b81aba999a6542ab866993)
1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2/*
3 * Copyright (C) 2022 MediaTek Inc.
4 * Author: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
5 */
6/dts-v1/;
7#include <dt-bindings/clock/mt8186-clk.h>
8#include <dt-bindings/interrupt-controller/arm-gic.h>

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193 entry-latency-us = <100>;
194 exit-latency-us = <250>;
195 min-residency-us = <1900>;
196 };
197 };
198
199 l2_0: l2-cache0 {
200 compatible = "cache";
1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2/*
3 * Copyright (C) 2022 MediaTek Inc.
4 * Author: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
5 */
6/dts-v1/;
7#include <dt-bindings/clock/mt8186-clk.h>
8#include <dt-bindings/interrupt-controller/arm-gic.h>

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193 entry-latency-us = <100>;
194 exit-latency-us = <250>;
195 min-residency-us = <1900>;
196 };
197 };
198
199 l2_0: l2-cache0 {
200 compatible = "cache";
201 cache-level = <2>;
201 next-level-cache = <&l3_0>;
202 };
203
204 l2_1: l2-cache1 {
205 compatible = "cache";
202 next-level-cache = <&l3_0>;
203 };
204
205 l2_1: l2-cache1 {
206 compatible = "cache";
207 cache-level = <2>;
206 next-level-cache = <&l3_0>;
207 };
208
209 l3_0: l3-cache {
210 compatible = "cache";
208 next-level-cache = <&l3_0>;
209 };
210
211 l3_0: l3-cache {
212 compatible = "cache";
213 cache-level = <3>;
211 };
212 };
213
214 clk13m: oscillator-13m {
215 compatible = "fixed-clock";
216 #clock-cells = <0>;
217 clock-frequency = <13000000>;
218 clock-output-names = "clk13m";

--- 601 unchanged lines hidden --- 		214 };
215 };
216
217 clk13m: oscillator-13m {
218 compatible = "fixed-clock";
219 #clock-cells = <0>;
220 clock-frequency = <13000000>;
221 clock-output-names = "clk13m";

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