1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2/* 3 * Copyright (C) 2022 MediaTek Inc. 4 * Author: Allen-KH Cheng <allen-kh.cheng@mediatek.com> 5 */ 6/dts-v1/; 7#include <dt-bindings/clock/mt8186-clk.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/pinctrl/mt8186-pinfunc.h> 11#include <dt-bindings/power/mt8186-power.h> 12#include <dt-bindings/phy/phy.h> 13#include <dt-bindings/reset/mt8186-resets.h> 14 15/ { 16 compatible = "mediatek,mt8186"; 17 interrupt-parent = <&gic>; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 cpus { 22 #address-cells = <1>; 23 #size-cells = <0>; 24 25 cpu-map { 26 cluster0 { 27 core0 { 28 cpu = <&cpu0>; 29 }; 30 31 core1 { 32 cpu = <&cpu1>; 33 }; 34 35 core2 { 36 cpu = <&cpu2>; 37 }; 38 39 core3 { 40 cpu = <&cpu3>; 41 }; 42 43 core4 { 44 cpu = <&cpu4>; 45 }; 46 47 core5 { 48 cpu = <&cpu5>; 49 }; 50 }; 51 52 cluster1 { 53 core0 { 54 cpu = <&cpu6>; 55 }; 56 57 core1 { 58 cpu = <&cpu7>; 59 }; 60 }; 61 }; 62 63 cpu0: cpu@0 { 64 device_type = "cpu"; 65 compatible = "arm,cortex-a55"; 66 reg = <0x000>; 67 enable-method = "psci"; 68 clock-frequency = <2000000000>; 69 capacity-dmips-mhz = <382>; 70 cpu-idle-states = <&cpu_off_l &cluster_off_l>; 71 next-level-cache = <&l2_0>; 72 #cooling-cells = <2>; 73 }; 74 75 cpu1: cpu@100 { 76 device_type = "cpu"; 77 compatible = "arm,cortex-a55"; 78 reg = <0x100>; 79 enable-method = "psci"; 80 clock-frequency = <2000000000>; 81 capacity-dmips-mhz = <382>; 82 cpu-idle-states = <&cpu_off_l &cluster_off_l>; 83 next-level-cache = <&l2_0>; 84 #cooling-cells = <2>; 85 }; 86 87 cpu2: cpu@200 { 88 device_type = "cpu"; 89 compatible = "arm,cortex-a55"; 90 reg = <0x200>; 91 enable-method = "psci"; 92 clock-frequency = <2000000000>; 93 capacity-dmips-mhz = <382>; 94 cpu-idle-states = <&cpu_off_l &cluster_off_l>; 95 next-level-cache = <&l2_0>; 96 #cooling-cells = <2>; 97 }; 98 99 cpu3: cpu@300 { 100 device_type = "cpu"; 101 compatible = "arm,cortex-a55"; 102 reg = <0x300>; 103 enable-method = "psci"; 104 clock-frequency = <2000000000>; 105 capacity-dmips-mhz = <382>; 106 cpu-idle-states = <&cpu_off_l &cluster_off_l>; 107 next-level-cache = <&l2_0>; 108 #cooling-cells = <2>; 109 }; 110 111 cpu4: cpu@400 { 112 device_type = "cpu"; 113 compatible = "arm,cortex-a55"; 114 reg = <0x400>; 115 enable-method = "psci"; 116 clock-frequency = <2000000000>; 117 capacity-dmips-mhz = <382>; 118 cpu-idle-states = <&cpu_off_l &cluster_off_l>; 119 next-level-cache = <&l2_0>; 120 #cooling-cells = <2>; 121 }; 122 123 cpu5: cpu@500 { 124 device_type = "cpu"; 125 compatible = "arm,cortex-a55"; 126 reg = <0x500>; 127 enable-method = "psci"; 128 clock-frequency = <2000000000>; 129 capacity-dmips-mhz = <382>; 130 cpu-idle-states = <&cpu_off_l &cluster_off_l>; 131 next-level-cache = <&l2_0>; 132 #cooling-cells = <2>; 133 }; 134 135 cpu6: cpu@600 { 136 device_type = "cpu"; 137 compatible = "arm,cortex-a76"; 138 reg = <0x600>; 139 enable-method = "psci"; 140 clock-frequency = <2050000000>; 141 capacity-dmips-mhz = <1024>; 142 cpu-idle-states = <&cpu_off_b &cluster_off_b>; 143 next-level-cache = <&l2_1>; 144 #cooling-cells = <2>; 145 }; 146 147 cpu7: cpu@700 { 148 device_type = "cpu"; 149 compatible = "arm,cortex-a76"; 150 reg = <0x700>; 151 enable-method = "psci"; 152 clock-frequency = <2050000000>; 153 capacity-dmips-mhz = <1024>; 154 cpu-idle-states = <&cpu_off_b &cluster_off_b>; 155 next-level-cache = <&l2_1>; 156 #cooling-cells = <2>; 157 }; 158 159 idle-states { 160 entry-method = "psci"; 161 162 cpu_off_l: cpu-off-l { 163 compatible = "arm,idle-state"; 164 arm,psci-suspend-param = <0x00010001>; 165 local-timer-stop; 166 entry-latency-us = <50>; 167 exit-latency-us = <100>; 168 min-residency-us = <1600>; 169 }; 170 171 cpu_off_b: cpu-off-b { 172 compatible = "arm,idle-state"; 173 arm,psci-suspend-param = <0x00010001>; 174 local-timer-stop; 175 entry-latency-us = <50>; 176 exit-latency-us = <100>; 177 min-residency-us = <1400>; 178 }; 179 180 cluster_off_l: cluster-off-l { 181 compatible = "arm,idle-state"; 182 arm,psci-suspend-param = <0x01010001>; 183 local-timer-stop; 184 entry-latency-us = <100>; 185 exit-latency-us = <250>; 186 min-residency-us = <2100>; 187 }; 188 189 cluster_off_b: cluster-off-b { 190 compatible = "arm,idle-state"; 191 arm,psci-suspend-param = <0x01010001>; 192 local-timer-stop; 193 entry-latency-us = <100>; 194 exit-latency-us = <250>; 195 min-residency-us = <1900>; 196 }; 197 }; 198 199 l2_0: l2-cache0 { 200 compatible = "cache"; 201 cache-level = <2>; 202 next-level-cache = <&l3_0>; 203 }; 204 205 l2_1: l2-cache1 { 206 compatible = "cache"; 207 cache-level = <2>; 208 next-level-cache = <&l3_0>; 209 }; 210 211 l3_0: l3-cache { 212 compatible = "cache"; 213 cache-level = <3>; 214 }; 215 }; 216 217 clk13m: oscillator-13m { 218 compatible = "fixed-clock"; 219 #clock-cells = <0>; 220 clock-frequency = <13000000>; 221 clock-output-names = "clk13m"; 222 }; 223 224 clk26m: oscillator-26m { 225 compatible = "fixed-clock"; 226 #clock-cells = <0>; 227 clock-frequency = <26000000>; 228 clock-output-names = "clk26m"; 229 }; 230 231 clk32k: oscillator-32k { 232 compatible = "fixed-clock"; 233 #clock-cells = <0>; 234 clock-frequency = <32768>; 235 clock-output-names = "clk32k"; 236 }; 237 238 pmu-a55 { 239 compatible = "arm,cortex-a55-pmu"; 240 interrupt-parent = <&gic>; 241 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>; 242 }; 243 244 pmu-a76 { 245 compatible = "arm,cortex-a76-pmu"; 246 interrupt-parent = <&gic>; 247 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>; 248 }; 249 250 psci { 251 compatible = "arm,psci-1.0"; 252 method = "smc"; 253 }; 254 255 timer { 256 compatible = "arm,armv8-timer"; 257 interrupt-parent = <&gic>; 258 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>, 259 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>, 260 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>, 261 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>; 262 }; 263 264 soc { 265 #address-cells = <2>; 266 #size-cells = <2>; 267 compatible = "simple-bus"; 268 ranges; 269 270 gic: interrupt-controller@c000000 { 271 compatible = "arm,gic-v3"; 272 #interrupt-cells = <4>; 273 #redistributor-regions = <1>; 274 interrupt-parent = <&gic>; 275 interrupt-controller; 276 reg = <0 0x0c000000 0 0x40000>, 277 <0 0x0c040000 0 0x200000>; 278 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 279 280 ppi-partitions { 281 ppi_cluster0: interrupt-partition-0 { 282 affinity = <&cpu0 &cpu1 &cpu2 &cpu3 &cpu4 &cpu5>; 283 }; 284 285 ppi_cluster1: interrupt-partition-1 { 286 affinity = <&cpu6 &cpu7>; 287 }; 288 }; 289 }; 290 291 mcusys: syscon@c53a000 { 292 compatible = "mediatek,mt8186-mcusys", "syscon"; 293 reg = <0 0xc53a000 0 0x1000>; 294 #clock-cells = <1>; 295 }; 296 297 topckgen: syscon@10000000 { 298 compatible = "mediatek,mt8186-topckgen", "syscon"; 299 reg = <0 0x10000000 0 0x1000>; 300 #clock-cells = <1>; 301 }; 302 303 infracfg_ao: syscon@10001000 { 304 compatible = "mediatek,mt8186-infracfg_ao", "syscon"; 305 reg = <0 0x10001000 0 0x1000>; 306 #clock-cells = <1>; 307 #reset-cells = <1>; 308 }; 309 310 pericfg: syscon@10003000 { 311 compatible = "mediatek,mt8186-pericfg", "syscon"; 312 reg = <0 0x10003000 0 0x1000>; 313 }; 314 315 pio: pinctrl@10005000 { 316 compatible = "mediatek,mt8186-pinctrl"; 317 reg = <0 0x10005000 0 0x1000>, 318 <0 0x10002000 0 0x0200>, 319 <0 0x10002200 0 0x0200>, 320 <0 0x10002400 0 0x0200>, 321 <0 0x10002600 0 0x0200>, 322 <0 0x10002a00 0 0x0200>, 323 <0 0x10002c00 0 0x0200>, 324 <0 0x1000b000 0 0x1000>; 325 reg-names = "iocfg0", "iocfg_lt", "iocfg_lm", "iocfg_lb", 326 "iocfg_bl", "iocfg_rb", "iocfg_rt", "eint"; 327 gpio-controller; 328 #gpio-cells = <2>; 329 gpio-ranges = <&pio 0 0 185>; 330 interrupt-controller; 331 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH 0>; 332 #interrupt-cells = <2>; 333 }; 334 335 watchdog: watchdog@10007000 { 336 compatible = "mediatek,mt8186-wdt", 337 "mediatek,mt6589-wdt"; 338 mediatek,disable-extrst; 339 reg = <0 0x10007000 0 0x1000>; 340 #reset-cells = <1>; 341 }; 342 343 apmixedsys: syscon@1000c000 { 344 compatible = "mediatek,mt8186-apmixedsys", "syscon"; 345 reg = <0 0x1000c000 0 0x1000>; 346 #clock-cells = <1>; 347 }; 348 349 pwrap: pwrap@1000d000 { 350 compatible = "mediatek,mt8186-pwrap", "syscon"; 351 reg = <0 0x1000d000 0 0x1000>; 352 reg-names = "pwrap"; 353 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH 0>; 354 clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>, 355 <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>; 356 clock-names = "spi", "wrap"; 357 }; 358 359 systimer: timer@10017000 { 360 compatible = "mediatek,mt8186-timer", 361 "mediatek,mt6765-timer"; 362 reg = <0 0x10017000 0 0x1000>; 363 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH 0>; 364 clocks = <&clk13m>; 365 }; 366 367 scp: scp@10500000 { 368 compatible = "mediatek,mt8186-scp"; 369 reg = <0 0x10500000 0 0x40000>, 370 <0 0x105c0000 0 0x19080>; 371 reg-names = "sram", "cfg"; 372 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH 0>; 373 }; 374 375 nor_flash: spi@11000000 { 376 compatible = "mediatek,mt8186-nor"; 377 reg = <0 0x11000000 0 0x1000>; 378 clocks = <&topckgen CLK_TOP_SPINOR>, 379 <&infracfg_ao CLK_INFRA_AO_SPINOR>, 380 <&infracfg_ao CLK_INFRA_AO_FLASHIF_133M>, 381 <&infracfg_ao CLK_INFRA_AO_FLASHIF_66M>; 382 clock-names = "spi", "sf", "axi", "axi_s"; 383 assigned-clocks = <&topckgen CLK_TOP_SPINOR>; 384 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D3_D8>; 385 interrupts = <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH 0>; 386 status = "disabled"; 387 }; 388 389 auxadc: adc@11001000 { 390 compatible = "mediatek,mt8186-auxadc", "mediatek,mt8173-auxadc"; 391 reg = <0 0x11001000 0 0x1000>; 392 #io-channel-cells = <1>; 393 clocks = <&infracfg_ao CLK_INFRA_AO_AUXADC>; 394 clock-names = "main"; 395 }; 396 397 uart0: serial@11002000 { 398 compatible = "mediatek,mt8186-uart", 399 "mediatek,mt6577-uart"; 400 reg = <0 0x11002000 0 0x1000>; 401 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH 0>; 402 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART0>; 403 clock-names = "baud", "bus"; 404 status = "disabled"; 405 }; 406 407 uart1: serial@11003000 { 408 compatible = "mediatek,mt8186-uart", 409 "mediatek,mt6577-uart"; 410 reg = <0 0x11003000 0 0x1000>; 411 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>; 412 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART1>; 413 clock-names = "baud", "bus"; 414 status = "disabled"; 415 }; 416 417 i2c0: i2c@11007000 { 418 compatible = "mediatek,mt8186-i2c"; 419 reg = <0 0x11007000 0 0x1000>, 420 <0 0x10200100 0 0x100>; 421 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>; 422 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C0>, 423 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 424 clock-names = "main", "dma"; 425 clock-div = <1>; 426 #address-cells = <1>; 427 #size-cells = <0>; 428 status = "disabled"; 429 }; 430 431 i2c1: i2c@11008000 { 432 compatible = "mediatek,mt8186-i2c"; 433 reg = <0 0x11008000 0 0x1000>, 434 <0 0x10200200 0 0x100>; 435 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>; 436 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C1>, 437 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 438 clock-names = "main", "dma"; 439 clock-div = <1>; 440 #address-cells = <1>; 441 #size-cells = <0>; 442 status = "disabled"; 443 }; 444 445 i2c2: i2c@11009000 { 446 compatible = "mediatek,mt8186-i2c"; 447 reg = <0 0x11009000 0 0x1000>, 448 <0 0x10200300 0 0x180>; 449 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH 0>; 450 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C2>, 451 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 452 clock-names = "main", "dma"; 453 clock-div = <1>; 454 #address-cells = <1>; 455 #size-cells = <0>; 456 status = "disabled"; 457 }; 458 459 i2c3: i2c@1100f000 { 460 compatible = "mediatek,mt8186-i2c"; 461 reg = <0 0x1100f000 0 0x1000>, 462 <0 0x10200480 0 0x100>; 463 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>; 464 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C3>, 465 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 466 clock-names = "main", "dma"; 467 clock-div = <1>; 468 #address-cells = <1>; 469 #size-cells = <0>; 470 status = "disabled"; 471 }; 472 473 i2c4: i2c@11011000 { 474 compatible = "mediatek,mt8186-i2c"; 475 reg = <0 0x11011000 0 0x1000>, 476 <0 0x10200580 0 0x180>; 477 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>; 478 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C4>, 479 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 480 clock-names = "main", "dma"; 481 clock-div = <1>; 482 #address-cells = <1>; 483 #size-cells = <0>; 484 status = "disabled"; 485 }; 486 487 i2c5: i2c@11016000 { 488 compatible = "mediatek,mt8186-i2c"; 489 reg = <0 0x11016000 0 0x1000>, 490 <0 0x10200700 0 0x100>; 491 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH 0>; 492 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C5>, 493 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 494 clock-names = "main", "dma"; 495 clock-div = <1>; 496 #address-cells = <1>; 497 #size-cells = <0>; 498 status = "disabled"; 499 }; 500 501 i2c6: i2c@1100d000 { 502 compatible = "mediatek,mt8186-i2c"; 503 reg = <0 0x1100d000 0 0x1000>, 504 <0 0x10200800 0 0x100>; 505 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH 0>; 506 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C6>, 507 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 508 clock-names = "main", "dma"; 509 clock-div = <1>; 510 #address-cells = <1>; 511 #size-cells = <0>; 512 status = "disabled"; 513 }; 514 515 i2c7: i2c@11004000 { 516 compatible = "mediatek,mt8186-i2c"; 517 reg = <0 0x11004000 0 0x1000>, 518 <0 0x10200900 0 0x180>; 519 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>; 520 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C7>, 521 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 522 clock-names = "main", "dma"; 523 clock-div = <1>; 524 #address-cells = <1>; 525 #size-cells = <0>; 526 status = "disabled"; 527 }; 528 529 i2c8: i2c@11005000 { 530 compatible = "mediatek,mt8186-i2c"; 531 reg = <0 0x11005000 0 0x1000>, 532 <0 0x10200A80 0 0x180>; 533 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>; 534 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C8>, 535 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 536 clock-names = "main", "dma"; 537 clock-div = <1>; 538 #address-cells = <1>; 539 #size-cells = <0>; 540 status = "disabled"; 541 }; 542 543 spi0: spi@1100a000 { 544 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi"; 545 #address-cells = <1>; 546 #size-cells = <0>; 547 reg = <0 0x1100a000 0 0x1000>; 548 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH 0>; 549 clocks = <&topckgen CLK_TOP_MAINPLL_D5>, 550 <&topckgen CLK_TOP_SPI>, 551 <&infracfg_ao CLK_INFRA_AO_SPI0>; 552 clock-names = "parent-clk", "sel-clk", "spi-clk"; 553 status = "disabled"; 554 }; 555 556 pwm0: pwm@1100e000 { 557 compatible = "mediatek,mt8186-disp-pwm", "mediatek,mt8183-disp-pwm"; 558 reg = <0 0x1100e000 0 0x1000>; 559 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH 0>; 560 #pwm-cells = <2>; 561 clocks = <&topckgen CLK_TOP_DISP_PWM>, 562 <&infracfg_ao CLK_INFRA_AO_DISP_PWM>; 563 clock-names = "main", "mm"; 564 status = "disabled"; 565 }; 566 567 spi1: spi@11010000 { 568 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi"; 569 #address-cells = <1>; 570 #size-cells = <0>; 571 reg = <0 0x11010000 0 0x1000>; 572 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH 0>; 573 clocks = <&topckgen CLK_TOP_MAINPLL_D5>, 574 <&topckgen CLK_TOP_SPI>, 575 <&infracfg_ao CLK_INFRA_AO_SPI1>; 576 clock-names = "parent-clk", "sel-clk", "spi-clk"; 577 status = "disabled"; 578 }; 579 580 spi2: spi@11012000 { 581 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi"; 582 #address-cells = <1>; 583 #size-cells = <0>; 584 reg = <0 0x11012000 0 0x1000>; 585 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH 0>; 586 clocks = <&topckgen CLK_TOP_MAINPLL_D5>, 587 <&topckgen CLK_TOP_SPI>, 588 <&infracfg_ao CLK_INFRA_AO_SPI2>; 589 clock-names = "parent-clk", "sel-clk", "spi-clk"; 590 status = "disabled"; 591 }; 592 593 spi3: spi@11013000 { 594 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi"; 595 #address-cells = <1>; 596 #size-cells = <0>; 597 reg = <0 0x11013000 0 0x1000>; 598 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH 0>; 599 clocks = <&topckgen CLK_TOP_MAINPLL_D5>, 600 <&topckgen CLK_TOP_SPI>, 601 <&infracfg_ao CLK_INFRA_AO_SPI3>; 602 clock-names = "parent-clk", "sel-clk", "spi-clk"; 603 status = "disabled"; 604 }; 605 606 spi4: spi@11014000 { 607 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi"; 608 #address-cells = <1>; 609 #size-cells = <0>; 610 reg = <0 0x11014000 0 0x1000>; 611 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>; 612 clocks = <&topckgen CLK_TOP_MAINPLL_D5>, 613 <&topckgen CLK_TOP_SPI>, 614 <&infracfg_ao CLK_INFRA_AO_SPI4>; 615 clock-names = "parent-clk", "sel-clk", "spi-clk"; 616 status = "disabled"; 617 }; 618 619 spi5: spi@11015000 { 620 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi"; 621 #address-cells = <1>; 622 #size-cells = <0>; 623 reg = <0 0x11015000 0 0x1000>; 624 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>; 625 clocks = <&topckgen CLK_TOP_MAINPLL_D5>, 626 <&topckgen CLK_TOP_SPI>, 627 <&infracfg_ao CLK_INFRA_AO_SPI5>; 628 clock-names = "parent-clk", "sel-clk", "spi-clk"; 629 status = "disabled"; 630 }; 631 632 imp_iic_wrap: clock-controller@11017000 { 633 compatible = "mediatek,mt8186-imp_iic_wrap"; 634 reg = <0 0x11017000 0 0x1000>; 635 #clock-cells = <1>; 636 }; 637 638 uart2: serial@11018000 { 639 compatible = "mediatek,mt8186-uart", 640 "mediatek,mt6577-uart"; 641 reg = <0 0x11018000 0 0x1000>; 642 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH 0>; 643 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART2>; 644 clock-names = "baud", "bus"; 645 status = "disabled"; 646 }; 647 648 i2c9: i2c@11019000 { 649 compatible = "mediatek,mt8186-i2c"; 650 reg = <0 0x11019000 0 0x1000>, 651 <0 0x10200c00 0 0x180>; 652 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH 0>; 653 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C9>, 654 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 655 clock-names = "main", "dma"; 656 clock-div = <1>; 657 #address-cells = <1>; 658 #size-cells = <0>; 659 status = "disabled"; 660 }; 661 662 mmc0: mmc@11230000 { 663 compatible = "mediatek,mt8186-mmc", 664 "mediatek,mt8183-mmc"; 665 reg = <0 0x11230000 0 0x1000>, 666 <0 0x11cd0000 0 0x1000>; 667 clocks = <&topckgen CLK_TOP_MSDC50_0>, 668 <&infracfg_ao CLK_INFRA_AO_MSDC0>, 669 <&infracfg_ao CLK_INFRA_AO_MSDC0_SRC>; 670 clock-names = "source", "hclk", "source_cg"; 671 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>; 672 assigned-clocks = <&topckgen CLK_TOP_MSDC50_0>; 673 assigned-clock-parents = <&apmixedsys CLK_APMIXED_MSDCPLL>; 674 status = "disabled"; 675 }; 676 677 mmc1: mmc@11240000 { 678 compatible = "mediatek,mt8186-mmc", 679 "mediatek,mt8183-mmc"; 680 reg = <0 0x11240000 0 0x1000>, 681 <0 0x11c90000 0 0x1000>; 682 clocks = <&topckgen CLK_TOP_MSDC30_1>, 683 <&infracfg_ao CLK_INFRA_AO_MSDC1>, 684 <&infracfg_ao CLK_INFRA_AO_MSDC1_SRC>; 685 clock-names = "source", "hclk", "source_cg"; 686 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>; 687 assigned-clocks = <&topckgen CLK_TOP_MSDC30_1>; 688 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>; 689 status = "disabled"; 690 }; 691 692 u3phy0: t-phy@11c80000 { 693 compatible = "mediatek,mt8186-tphy", 694 "mediatek,generic-tphy-v2"; 695 #address-cells = <1>; 696 #size-cells = <1>; 697 ranges = <0x0 0x0 0x11c80000 0x1000>; 698 status = "disabled"; 699 700 u2port1: usb-phy@0 { 701 reg = <0x0 0x700>; 702 clocks = <&clk26m>; 703 clock-names = "ref"; 704 #phy-cells = <1>; 705 }; 706 707 u3port1: usb-phy@700 { 708 reg = <0x700 0x900>; 709 clocks = <&clk26m>; 710 clock-names = "ref"; 711 #phy-cells = <1>; 712 }; 713 }; 714 715 u3phy1: t-phy@11ca0000 { 716 compatible = "mediatek,mt8186-tphy", 717 "mediatek,generic-tphy-v2"; 718 #address-cells = <1>; 719 #size-cells = <1>; 720 ranges = <0x0 0x0 0x11ca0000 0x1000>; 721 status = "disabled"; 722 723 u2port0: usb-phy@0 { 724 reg = <0x0 0x700>; 725 clocks = <&clk26m>; 726 clock-names = "ref"; 727 #phy-cells = <1>; 728 mediatek,discth = <0x8>; 729 }; 730 }; 731 732 efuse: efuse@11cb0000 { 733 compatible = "mediatek,mt8186-efuse", "mediatek,efuse"; 734 reg = <0 0x11cb0000 0 0x1000>; 735 #address-cells = <1>; 736 #size-cells = <1>; 737 }; 738 739 mipi_tx0: dsi-phy@11cc0000 { 740 compatible = "mediatek,mt8183-mipi-tx"; 741 reg = <0 0x11cc0000 0 0x1000>; 742 clocks = <&clk26m>; 743 #clock-cells = <0>; 744 #phy-cells = <0>; 745 clock-output-names = "mipi_tx0_pll"; 746 status = "disabled"; 747 }; 748 749 mfgsys: clock-controller@13000000 { 750 compatible = "mediatek,mt8186-mfgsys"; 751 reg = <0 0x13000000 0 0x1000>; 752 #clock-cells = <1>; 753 }; 754 755 mmsys: syscon@14000000 { 756 compatible = "mediatek,mt8186-mmsys", "syscon"; 757 reg = <0 0x14000000 0 0x1000>; 758 #clock-cells = <1>; 759 #reset-cells = <1>; 760 }; 761 762 wpesys: clock-controller@14020000 { 763 compatible = "mediatek,mt8186-wpesys"; 764 reg = <0 0x14020000 0 0x1000>; 765 #clock-cells = <1>; 766 }; 767 768 imgsys1: clock-controller@15020000 { 769 compatible = "mediatek,mt8186-imgsys1"; 770 reg = <0 0x15020000 0 0x1000>; 771 #clock-cells = <1>; 772 }; 773 774 imgsys2: clock-controller@15820000 { 775 compatible = "mediatek,mt8186-imgsys2"; 776 reg = <0 0x15820000 0 0x1000>; 777 #clock-cells = <1>; 778 }; 779 780 vdecsys: clock-controller@1602f000 { 781 compatible = "mediatek,mt8186-vdecsys"; 782 reg = <0 0x1602f000 0 0x1000>; 783 #clock-cells = <1>; 784 }; 785 786 vencsys: clock-controller@17000000 { 787 compatible = "mediatek,mt8186-vencsys"; 788 reg = <0 0x17000000 0 0x1000>; 789 #clock-cells = <1>; 790 }; 791 792 camsys: clock-controller@1a000000 { 793 compatible = "mediatek,mt8186-camsys"; 794 reg = <0 0x1a000000 0 0x1000>; 795 #clock-cells = <1>; 796 }; 797 798 camsys_rawa: clock-controller@1a04f000 { 799 compatible = "mediatek,mt8186-camsys_rawa"; 800 reg = <0 0x1a04f000 0 0x1000>; 801 #clock-cells = <1>; 802 }; 803 804 camsys_rawb: clock-controller@1a06f000 { 805 compatible = "mediatek,mt8186-camsys_rawb"; 806 reg = <0 0x1a06f000 0 0x1000>; 807 #clock-cells = <1>; 808 }; 809 810 mdpsys: clock-controller@1b000000 { 811 compatible = "mediatek,mt8186-mdpsys"; 812 reg = <0 0x1b000000 0 0x1000>; 813 #clock-cells = <1>; 814 }; 815 816 ipesys: clock-controller@1c000000 { 817 compatible = "mediatek,mt8186-ipesys"; 818 reg = <0 0x1c000000 0 0x1000>; 819 #clock-cells = <1>; 820 }; 821 }; 822}; 823