mt7986a.dtsi (99cce13b82a9366cfdd230ba6ddb48ba30d2741f) mt7986a.dtsi (885e153ed7c1b0ec8bc25651f0644b3cb65ecaf4)
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (C) 2021 MediaTek Inc.
4 * Author: Sam.Shih <sam.shih@mediatek.com>
5 */
6
7#include <dt-bindings/interrupt-controller/irq.h>
8#include <dt-bindings/interrupt-controller/arm-gic.h>

--- 240 unchanged lines hidden (view full) ---

249 clocks = <&infracfg CLK_INFRA_I2C0_CK>,
250 <&infracfg CLK_INFRA_AP_DMA_CK>;
251 clock-names = "main", "dma";
252 #address-cells = <1>;
253 #size-cells = <0>;
254 status = "disabled";
255 };
256
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (C) 2021 MediaTek Inc.
4 * Author: Sam.Shih <sam.shih@mediatek.com>
5 */
6
7#include <dt-bindings/interrupt-controller/irq.h>
8#include <dt-bindings/interrupt-controller/arm-gic.h>

--- 240 unchanged lines hidden (view full) ---

249 clocks = <&infracfg CLK_INFRA_I2C0_CK>,
250 <&infracfg CLK_INFRA_AP_DMA_CK>;
251 clock-names = "main", "dma";
252 #address-cells = <1>;
253 #size-cells = <0>;
254 status = "disabled";
255 };
256
257 spi0: spi@1100a000 {
258 compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
259 #address-cells = <1>;
260 #size-cells = <0>;
261 reg = <0 0x1100a000 0 0x100>;
262 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
263 clocks = <&topckgen CLK_TOP_MPLL_D2>,
264 <&topckgen CLK_TOP_SPI_SEL>,
265 <&infracfg CLK_INFRA_SPI0_CK>,
266 <&infracfg CLK_INFRA_SPI0_HCK_CK>;
267 clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
268 status = "disabled";
269 };
270
271 spi1: spi@1100b000 {
272 compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
273 #address-cells = <1>;
274 #size-cells = <0>;
275 reg = <0 0x1100b000 0 0x100>;
276 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
277 clocks = <&topckgen CLK_TOP_MPLL_D2>,
278 <&topckgen CLK_TOP_SPIM_MST_SEL>,
279 <&infracfg CLK_INFRA_SPI1_CK>,
280 <&infracfg CLK_INFRA_SPI1_HCK_CK>;
281 clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
282 status = "disabled";
283 };
284
257 ethsys: syscon@15000000 {
258 #address-cells = <1>;
259 #size-cells = <1>;
260 compatible = "mediatek,mt7986-ethsys",
261 "syscon";
262 reg = <0 0x15000000 0 0x1000>;
263 #clock-cells = <1>;
264 #reset-cells = <1>;

--- 79 unchanged lines hidden --- 		285 ethsys: syscon@15000000 {
286 #address-cells = <1>;
287 #size-cells = <1>;
288 compatible = "mediatek,mt7986-ethsys",
289 "syscon";
290 reg = <0 0x15000000 0 0x1000>;
291 #clock-cells = <1>;
292 #reset-cells = <1>;

--- 79 unchanged lines hidden ---