1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (C) 2021 MediaTek Inc. 4 * Author: Sam.Shih <sam.shih@mediatek.com> 5 */ 6 7#include <dt-bindings/interrupt-controller/irq.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/clock/mt7986-clk.h> 10#include <dt-bindings/reset/mt7986-resets.h> 11 12/ { 13 compatible = "mediatek,mt7986a"; 14 interrupt-parent = <&gic>; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 clk40m: oscillator-40m { 19 compatible = "fixed-clock"; 20 clock-frequency = <40000000>; 21 #clock-cells = <0>; 22 clock-output-names = "clkxtal"; 23 }; 24 25 cpus { 26 #address-cells = <1>; 27 #size-cells = <0>; 28 cpu0: cpu@0 { 29 device_type = "cpu"; 30 compatible = "arm,cortex-a53"; 31 enable-method = "psci"; 32 reg = <0x0>; 33 #cooling-cells = <2>; 34 }; 35 36 cpu1: cpu@1 { 37 device_type = "cpu"; 38 compatible = "arm,cortex-a53"; 39 enable-method = "psci"; 40 reg = <0x1>; 41 #cooling-cells = <2>; 42 }; 43 44 cpu2: cpu@2 { 45 device_type = "cpu"; 46 compatible = "arm,cortex-a53"; 47 enable-method = "psci"; 48 reg = <0x2>; 49 #cooling-cells = <2>; 50 }; 51 52 cpu3: cpu@3 { 53 device_type = "cpu"; 54 enable-method = "psci"; 55 compatible = "arm,cortex-a53"; 56 reg = <0x3>; 57 #cooling-cells = <2>; 58 }; 59 }; 60 61 psci { 62 compatible = "arm,psci-0.2"; 63 method = "smc"; 64 }; 65 66 reserved-memory { 67 #address-cells = <2>; 68 #size-cells = <2>; 69 ranges; 70 /* 192 KiB reserved for ARM Trusted Firmware (BL31) */ 71 secmon_reserved: secmon@43000000 { 72 reg = <0 0x43000000 0 0x30000>; 73 no-map; 74 }; 75 76 wmcpu_emi: wmcpu-reserved@4fc00000 { 77 no-map; 78 reg = <0 0x4fc00000 0 0x00100000>; 79 }; 80 }; 81 82 timer { 83 compatible = "arm,armv8-timer"; 84 interrupt-parent = <&gic>; 85 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 86 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 87 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 88 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 89 }; 90 91 soc { 92 #address-cells = <2>; 93 #size-cells = <2>; 94 compatible = "simple-bus"; 95 ranges; 96 97 gic: interrupt-controller@c000000 { 98 compatible = "arm,gic-v3"; 99 #interrupt-cells = <3>; 100 interrupt-parent = <&gic>; 101 interrupt-controller; 102 reg = <0 0x0c000000 0 0x10000>, /* GICD */ 103 <0 0x0c080000 0 0x80000>, /* GICR */ 104 <0 0x0c400000 0 0x2000>, /* GICC */ 105 <0 0x0c410000 0 0x1000>, /* GICH */ 106 <0 0x0c420000 0 0x2000>; /* GICV */ 107 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 108 }; 109 110 infracfg: infracfg@10001000 { 111 compatible = "mediatek,mt7986-infracfg", "syscon"; 112 reg = <0 0x10001000 0 0x1000>; 113 #clock-cells = <1>; 114 }; 115 116 wed_pcie: wed-pcie@10003000 { 117 compatible = "mediatek,mt7986-wed-pcie", 118 "syscon"; 119 reg = <0 0x10003000 0 0x10>; 120 }; 121 122 topckgen: topckgen@1001b000 { 123 compatible = "mediatek,mt7986-topckgen", "syscon"; 124 reg = <0 0x1001B000 0 0x1000>; 125 #clock-cells = <1>; 126 }; 127 128 watchdog: watchdog@1001c000 { 129 compatible = "mediatek,mt7986-wdt", 130 "mediatek,mt6589-wdt"; 131 reg = <0 0x1001c000 0 0x1000>; 132 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 133 #reset-cells = <1>; 134 status = "disabled"; 135 }; 136 137 apmixedsys: apmixedsys@1001e000 { 138 compatible = "mediatek,mt7986-apmixedsys"; 139 reg = <0 0x1001E000 0 0x1000>; 140 #clock-cells = <1>; 141 }; 142 143 pio: pinctrl@1001f000 { 144 compatible = "mediatek,mt7986a-pinctrl"; 145 reg = <0 0x1001f000 0 0x1000>, 146 <0 0x11c30000 0 0x1000>, 147 <0 0x11c40000 0 0x1000>, 148 <0 0x11e20000 0 0x1000>, 149 <0 0x11e30000 0 0x1000>, 150 <0 0x11f00000 0 0x1000>, 151 <0 0x11f10000 0 0x1000>, 152 <0 0x1000b000 0 0x1000>; 153 reg-names = "gpio", "iocfg_rt", "iocfg_rb", "iocfg_lt", 154 "iocfg_lb", "iocfg_tr", "iocfg_tl", "eint"; 155 gpio-controller; 156 #gpio-cells = <2>; 157 gpio-ranges = <&pio 0 0 100>; 158 interrupt-controller; 159 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; 160 interrupt-parent = <&gic>; 161 #interrupt-cells = <2>; 162 }; 163 164 sgmiisys0: syscon@10060000 { 165 compatible = "mediatek,mt7986-sgmiisys_0", 166 "syscon"; 167 reg = <0 0x10060000 0 0x1000>; 168 #clock-cells = <1>; 169 }; 170 171 sgmiisys1: syscon@10070000 { 172 compatible = "mediatek,mt7986-sgmiisys_1", 173 "syscon"; 174 reg = <0 0x10070000 0 0x1000>; 175 #clock-cells = <1>; 176 }; 177 178 trng: rng@1020f000 { 179 compatible = "mediatek,mt7986-rng", 180 "mediatek,mt7623-rng"; 181 reg = <0 0x1020f000 0 0x100>; 182 clocks = <&infracfg CLK_INFRA_TRNG_CK>; 183 clock-names = "rng"; 184 status = "disabled"; 185 }; 186 187 crypto: crypto@10320000 { 188 compatible = "inside-secure,safexcel-eip97"; 189 reg = <0 0x10320000 0 0x40000>; 190 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 191 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 192 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 193 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 194 interrupt-names = "ring0", "ring1", "ring2", "ring3"; 195 clocks = <&infracfg CLK_INFRA_EIP97_CK>; 196 clock-names = "infra_eip97_ck"; 197 assigned-clocks = <&topckgen CLK_TOP_EIP_B_SEL>; 198 assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>; 199 status = "disabled"; 200 }; 201 202 uart0: serial@11002000 { 203 compatible = "mediatek,mt7986-uart", 204 "mediatek,mt6577-uart"; 205 reg = <0 0x11002000 0 0x400>; 206 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 207 clocks = <&infracfg CLK_INFRA_UART0_SEL>, 208 <&infracfg CLK_INFRA_UART0_CK>; 209 clock-names = "baud", "bus"; 210 assigned-clocks = <&topckgen CLK_TOP_UART_SEL>, 211 <&infracfg CLK_INFRA_UART0_SEL>; 212 assigned-clock-parents = <&topckgen CLK_TOP_XTAL>, 213 <&topckgen CLK_TOP_UART_SEL>; 214 status = "disabled"; 215 }; 216 217 uart1: serial@11003000 { 218 compatible = "mediatek,mt7986-uart", 219 "mediatek,mt6577-uart"; 220 reg = <0 0x11003000 0 0x400>; 221 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 222 clocks = <&infracfg CLK_INFRA_UART1_SEL>, 223 <&infracfg CLK_INFRA_UART1_CK>; 224 clock-names = "baud", "bus"; 225 assigned-clocks = <&infracfg CLK_INFRA_UART1_SEL>; 226 assigned-clock-parents = <&topckgen CLK_TOP_F26M_SEL>; 227 status = "disabled"; 228 }; 229 230 uart2: serial@11004000 { 231 compatible = "mediatek,mt7986-uart", 232 "mediatek,mt6577-uart"; 233 reg = <0 0x11004000 0 0x400>; 234 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 235 clocks = <&infracfg CLK_INFRA_UART2_SEL>, 236 <&infracfg CLK_INFRA_UART2_CK>; 237 clock-names = "baud", "bus"; 238 assigned-clocks = <&infracfg CLK_INFRA_UART2_SEL>; 239 assigned-clock-parents = <&topckgen CLK_TOP_F26M_SEL>; 240 status = "disabled"; 241 }; 242 243 i2c0: i2c@11008000 { 244 compatible = "mediatek,mt7986-i2c"; 245 reg = <0 0x11008000 0 0x90>, 246 <0 0x10217080 0 0x80>; 247 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 248 clock-div = <5>; 249 clocks = <&infracfg CLK_INFRA_I2C0_CK>, 250 <&infracfg CLK_INFRA_AP_DMA_CK>; 251 clock-names = "main", "dma"; 252 #address-cells = <1>; 253 #size-cells = <0>; 254 status = "disabled"; 255 }; 256 257 ethsys: syscon@15000000 { 258 #address-cells = <1>; 259 #size-cells = <1>; 260 compatible = "mediatek,mt7986-ethsys", 261 "syscon"; 262 reg = <0 0x15000000 0 0x1000>; 263 #clock-cells = <1>; 264 #reset-cells = <1>; 265 }; 266 267 wed0: wed@15010000 { 268 compatible = "mediatek,mt7986-wed", 269 "syscon"; 270 reg = <0 0x15010000 0 0x1000>; 271 interrupt-parent = <&gic>; 272 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; 273 }; 274 275 wed1: wed@15011000 { 276 compatible = "mediatek,mt7986-wed", 277 "syscon"; 278 reg = <0 0x15011000 0 0x1000>; 279 interrupt-parent = <&gic>; 280 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 281 }; 282 283 eth: ethernet@15100000 { 284 compatible = "mediatek,mt7986-eth"; 285 reg = <0 0x15100000 0 0x80000>; 286 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 287 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, 288 <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, 289 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; 290 clocks = <ðsys CLK_ETH_FE_EN>, 291 <ðsys CLK_ETH_GP2_EN>, 292 <ðsys CLK_ETH_GP1_EN>, 293 <ðsys CLK_ETH_WOCPU1_EN>, 294 <ðsys CLK_ETH_WOCPU0_EN>, 295 <&sgmiisys0 CLK_SGMII0_TX250M_EN>, 296 <&sgmiisys0 CLK_SGMII0_RX250M_EN>, 297 <&sgmiisys0 CLK_SGMII0_CDR_REF>, 298 <&sgmiisys0 CLK_SGMII0_CDR_FB>, 299 <&sgmiisys1 CLK_SGMII1_TX250M_EN>, 300 <&sgmiisys1 CLK_SGMII1_RX250M_EN>, 301 <&sgmiisys1 CLK_SGMII1_CDR_REF>, 302 <&sgmiisys1 CLK_SGMII1_CDR_FB>, 303 <&topckgen CLK_TOP_NETSYS_SEL>, 304 <&topckgen CLK_TOP_NETSYS_500M_SEL>; 305 clock-names = "fe", "gp2", "gp1", "wocpu1", "wocpu0", 306 "sgmii_tx250m", "sgmii_rx250m", 307 "sgmii_cdr_ref", "sgmii_cdr_fb", 308 "sgmii2_tx250m", "sgmii2_rx250m", 309 "sgmii2_cdr_ref", "sgmii2_cdr_fb", 310 "netsys0", "netsys1"; 311 assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>, 312 <&topckgen CLK_TOP_SGM_325M_SEL>; 313 assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>, 314 <&apmixedsys CLK_APMIXED_SGMPLL>; 315 mediatek,ethsys = <ðsys>; 316 mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>; 317 mediatek,wed-pcie = <&wed_pcie>; 318 mediatek,wed = <&wed0>, <&wed1>; 319 #reset-cells = <1>; 320 #address-cells = <1>; 321 #size-cells = <0>; 322 status = "disabled"; 323 }; 324 325 wifi: wifi@18000000 { 326 compatible = "mediatek,mt7986-wmac"; 327 resets = <&watchdog MT7986_TOPRGU_CONSYS_SW_RST>; 328 reset-names = "consys"; 329 clocks = <&topckgen CLK_TOP_CONN_MCUSYS_SEL>, 330 <&topckgen CLK_TOP_AP2CNN_HOST_SEL>; 331 clock-names = "mcu", "ap2conn"; 332 reg = <0 0x18000000 0 0x1000000>, 333 <0 0x10003000 0 0x1000>, 334 <0 0x11d10000 0 0x1000>; 335 interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 336 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 337 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>, 338 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>; 339 memory-region = <&wmcpu_emi>; 340 }; 341 }; 342 343}; 344