mt7986a.dtsi (573c38533c0d7f7a8964530c2c606eb691ba28ec) mt7986a.dtsi (ecc5287cfe5359e454ca705ef02aae0c9756eaad)
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (C) 2021 MediaTek Inc.
4 * Author: Sam.Shih <sam.shih@mediatek.com>
5 */
6
7#include <dt-bindings/interrupt-controller/irq.h>
8#include <dt-bindings/interrupt-controller/arm-gic.h>

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71 reg = <0 0x43000000 0 0x30000>;
72 no-map;
73 };
74
75 wmcpu_emi: wmcpu-reserved@4fc00000 {
76 no-map;
77 reg = <0 0x4fc00000 0 0x00100000>;
78 };
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (C) 2021 MediaTek Inc.
4 * Author: Sam.Shih <sam.shih@mediatek.com>
5 */
6
7#include <dt-bindings/interrupt-controller/irq.h>
8#include <dt-bindings/interrupt-controller/arm-gic.h>

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71 reg = <0 0x43000000 0 0x30000>;
72 no-map;
73 };
74
75 wmcpu_emi: wmcpu-reserved@4fc00000 {
76 no-map;
77 reg = <0 0x4fc00000 0 0x00100000>;
78 };
79
80 wo_emi0: wo-emi@4fd00000 {
81 reg = <0 0x4fd00000 0 0x40000>;
82 no-map;
83 };
84
85 wo_emi1: wo-emi@4fd40000 {
86 reg = <0 0x4fd40000 0 0x40000>;
87 no-map;
88 };
89
90 wo_ilm0: wo-ilm@151e0000 {
91 reg = <0 0x151e0000 0 0x8000>;
92 no-map;
93 };
94
95 wo_ilm1: wo-ilm@151f0000 {
96 reg = <0 0x151f0000 0 0x8000>;
97 no-map;
98 };
99
100 wo_data: wo-data@4fd80000 {
101 reg = <0 0x4fd80000 0 0x240000>;
102 no-map;
103 };
104
105 wo_dlm0: wo-dlm@151e8000 {
106 reg = <0 0x151e8000 0 0x2000>;
107 no-map;
108 };
109
110 wo_dlm1: wo-dlm@151f8000 {
111 reg = <0 0x151f8000 0 0x2000>;
112 no-map;
113 };
114
115 wo_boot: wo-boot@15194000 {
116 reg = <0 0x15194000 0 0x1000>;
117 no-map;
118 };
119
120 };
121
122 timer {
123 compatible = "arm,armv8-timer";
124 interrupt-parent = <&gic>;
125 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
126 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
127 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,

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204
205 sgmiisys1: syscon@10070000 {
206 compatible = "mediatek,mt7986-sgmiisys_1",
207 "syscon";
208 reg = <0 0x10070000 0 0x1000>;
209 #clock-cells = <1>;
210 };
211
79 };
80
81 timer {
82 compatible = "arm,armv8-timer";
83 interrupt-parent = <&gic>;
84 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
85 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
86 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,

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163
164 sgmiisys1: syscon@10070000 {
165 compatible = "mediatek,mt7986-sgmiisys_1",
166 "syscon";
167 reg = <0 0x10070000 0 0x1000>;
168 #clock-cells = <1>;
169 };
170
212 trng: trng@1020f000 {
171 trng: rng@1020f000 {
213 compatible = "mediatek,mt7986-rng",
214 "mediatek,mt7623-rng";
215 reg = <0 0x1020f000 0 0x100>;
216 clocks = <&infracfg CLK_INFRA_TRNG_CK>;
217 clock-names = "rng";
218 status = "disabled";
219 };
220
172 compatible = "mediatek,mt7986-rng",
173 "mediatek,mt7623-rng";
174 reg = <0 0x1020f000 0 0x100>;
175 clocks = <&infracfg CLK_INFRA_TRNG_CK>;
176 clock-names = "rng";
177 status = "disabled";
178 };
179
180 crypto: crypto@10320000 {
181 compatible = "inside-secure,safexcel-eip97";
182 reg = <0 0x10320000 0 0x40000>;
183 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
184 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
185 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
186 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
187 interrupt-names = "ring0", "ring1", "ring2", "ring3";
188 clocks = <&infracfg CLK_INFRA_EIP97_CK>;
189 clock-names = "infra_eip97_ck";
190 assigned-clocks = <&topckgen CLK_TOP_EIP_B_SEL>;
191 assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>;
192 status = "disabled";
193 };
194
221 uart0: serial@11002000 {
222 compatible = "mediatek,mt7986-uart",
223 "mediatek,mt6577-uart";
224 reg = <0 0x11002000 0 0x400>;
225 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
226 clocks = <&infracfg CLK_INFRA_UART0_SEL>,
227 <&infracfg CLK_INFRA_UART0_CK>;
228 clock-names = "baud", "bus";

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276 };
277
278 wed0: wed@15010000 {
279 compatible = "mediatek,mt7986-wed",
280 "syscon";
281 reg = <0 0x15010000 0 0x1000>;
282 interrupt-parent = <&gic>;
283 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
195 uart0: serial@11002000 {
196 compatible = "mediatek,mt7986-uart",
197 "mediatek,mt6577-uart";
198 reg = <0 0x11002000 0 0x400>;
199 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
200 clocks = <&infracfg CLK_INFRA_UART0_SEL>,
201 <&infracfg CLK_INFRA_UART0_CK>;
202 clock-names = "baud", "bus";

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250 };
251
252 wed0: wed@15010000 {
253 compatible = "mediatek,mt7986-wed",
254 "syscon";
255 reg = <0 0x15010000 0 0x1000>;
256 interrupt-parent = <&gic>;
257 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
284 memory-region = <&wo_emi0>, <&wo_ilm0>, <&wo_dlm0>,
285 <&wo_data>, <&wo_boot>;
286 memory-region-names = "wo-emi", "wo-ilm", "wo-dlm",
287 "wo-data", "wo-boot";
288 mediatek,wo-ccif = <&wo_ccif0>;
289 };
290
291 wed1: wed@15011000 {
292 compatible = "mediatek,mt7986-wed",
293 "syscon";
294 reg = <0 0x15011000 0 0x1000>;
295 interrupt-parent = <&gic>;
296 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
258 };
259
260 wed1: wed@15011000 {
261 compatible = "mediatek,mt7986-wed",
262 "syscon";
263 reg = <0 0x15011000 0 0x1000>;
264 interrupt-parent = <&gic>;
265 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
297 memory-region = <&wo_emi1>, <&wo_ilm1>, <&wo_dlm1>,
298 <&wo_data>, <&wo_boot>;
299 memory-region-names = "wo-emi", "wo-ilm", "wo-dlm",
300 "wo-data", "wo-boot";
301 mediatek,wo-ccif = <&wo_ccif1>;
302 };
303
266 };
267
304 wo_ccif0: syscon@151a5000 {
305 compatible = "mediatek,mt7986-wo-ccif", "syscon";
306 reg = <0 0x151a5000 0 0x1000>;
307 interrupt-parent = <&gic>;
308 interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
309 };
310
311 wo_ccif1: syscon@151ad000 {
312 compatible = "mediatek,mt7986-wo-ccif", "syscon";
313 reg = <0 0x151ad000 0 0x1000>;
314 interrupt-parent = <&gic>;
315 interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
316 };
317
318 eth: ethernet@15100000 {
319 compatible = "mediatek,mt7986-eth";
320 reg = <0 0x15100000 0 0x80000>;
321 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
322 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
323 <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
324 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
325 clocks = <&ethsys CLK_ETH_FE_EN>,

--- 53 unchanged lines hidden --- 		268 eth: ethernet@15100000 {
269 compatible = "mediatek,mt7986-eth";
270 reg = <0 0x15100000 0 0x80000>;
271 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
272 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
273 <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
274 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
275 clocks = <&ethsys CLK_ETH_FE_EN>,

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