xref: /linux/arch/arm64/boot/dts/mediatek/mt7986a.dtsi (revision 573c38533c0d7f7a8964530c2c606eb691ba28ec) 
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (C) 2021 MediaTek Inc.
4 * Author: Sam.Shih <sam.shih@mediatek.com>
5 */
6
7#include <dt-bindings/interrupt-controller/irq.h>
8#include <dt-bindings/interrupt-controller/arm-gic.h>
9#include <dt-bindings/clock/mt7986-clk.h>
10#include <dt-bindings/reset/mt7986-resets.h>
11
12/ {
13	interrupt-parent = <&gic>;
14	#address-cells = <2>;
15	#size-cells = <2>;
16
17	clk40m: oscillator@0 {
18		compatible = "fixed-clock";
19		clock-frequency = <40000000>;
20		#clock-cells = <0>;
21		clock-output-names = "clkxtal";
22	};
23
24	cpus {
25		#address-cells = <1>;
26		#size-cells = <0>;
27		cpu0: cpu@0 {
28			device_type = "cpu";
29			compatible = "arm,cortex-a53";
30			enable-method = "psci";
31			reg = <0x0>;
32			#cooling-cells = <2>;
33		};
34
35		cpu1: cpu@1 {
36			device_type = "cpu";
37			compatible = "arm,cortex-a53";
38			enable-method = "psci";
39			reg = <0x1>;
40			#cooling-cells = <2>;
41		};
42
43		cpu2: cpu@2 {
44			device_type = "cpu";
45			compatible = "arm,cortex-a53";
46			enable-method = "psci";
47			reg = <0x2>;
48			#cooling-cells = <2>;
49		};
50
51		cpu3: cpu@3 {
52			device_type = "cpu";
53			enable-method = "psci";
54			compatible = "arm,cortex-a53";
55			reg = <0x3>;
56			#cooling-cells = <2>;
57		};
58	};
59
60	psci {
61		compatible = "arm,psci-0.2";
62		method = "smc";
63	};
64
65	reserved-memory {
66		#address-cells = <2>;
67		#size-cells = <2>;
68		ranges;
69		/* 192 KiB reserved for ARM Trusted Firmware (BL31) */
70		secmon_reserved: secmon@43000000 {
71			reg = <0 0x43000000 0 0x30000>;
72			no-map;
73		};
74
75		wmcpu_emi: wmcpu-reserved@4fc00000 {
76			no-map;
77			reg = <0 0x4fc00000 0 0x00100000>;
78		};
79
80		wo_emi0: wo-emi@4fd00000 {
81			reg = <0 0x4fd00000 0 0x40000>;
82			no-map;
83		};
84
85		wo_emi1: wo-emi@4fd40000 {
86			reg = <0 0x4fd40000 0 0x40000>;
87			no-map;
88		};
89
90		wo_ilm0: wo-ilm@151e0000 {
91			reg = <0 0x151e0000 0 0x8000>;
92			no-map;
93		};
94
95		wo_ilm1: wo-ilm@151f0000 {
96			reg = <0 0x151f0000 0 0x8000>;
97			no-map;
98		};
99
100		wo_data: wo-data@4fd80000 {
101			reg = <0 0x4fd80000 0 0x240000>;
102			no-map;
103		};
104
105		wo_dlm0: wo-dlm@151e8000 {
106			reg = <0 0x151e8000 0 0x2000>;
107			no-map;
108		};
109
110		wo_dlm1: wo-dlm@151f8000 {
111			reg = <0 0x151f8000 0 0x2000>;
112			no-map;
113		};
114
115		wo_boot: wo-boot@15194000 {
116			reg = <0 0x15194000 0 0x1000>;
117			no-map;
118		};
119
120	};
121
122	timer {
123		compatible = "arm,armv8-timer";
124		interrupt-parent = <&gic>;
125		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
126			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
127			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
128			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
129	};
130
131	soc {
132		#address-cells = <2>;
133		#size-cells = <2>;
134		compatible = "simple-bus";
135		ranges;
136
137		gic: interrupt-controller@c000000 {
138			compatible = "arm,gic-v3";
139			#interrupt-cells = <3>;
140			interrupt-parent = <&gic>;
141			interrupt-controller;
142			reg = <0 0x0c000000 0 0x10000>,  /* GICD */
143			      <0 0x0c080000 0 0x80000>,  /* GICR */
144			      <0 0x0c400000 0 0x2000>,   /* GICC */
145			      <0 0x0c410000 0 0x1000>,   /* GICH */
146			      <0 0x0c420000 0 0x2000>;   /* GICV */
147			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
148		};
149
150		infracfg: infracfg@10001000 {
151			compatible = "mediatek,mt7986-infracfg", "syscon";
152			reg = <0 0x10001000 0 0x1000>;
153			#clock-cells = <1>;
154		};
155
156		topckgen: topckgen@1001b000 {
157			compatible = "mediatek,mt7986-topckgen", "syscon";
158			reg = <0 0x1001B000 0 0x1000>;
159			#clock-cells = <1>;
160		};
161
162		watchdog: watchdog@1001c000 {
163			compatible = "mediatek,mt7986-wdt",
164				     "mediatek,mt6589-wdt";
165			reg = <0 0x1001c000 0 0x1000>;
166			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
167			#reset-cells = <1>;
168			status = "disabled";
169		};
170
171		apmixedsys: apmixedsys@1001e000 {
172			compatible = "mediatek,mt7986-apmixedsys";
173			reg = <0 0x1001E000 0 0x1000>;
174			#clock-cells = <1>;
175		};
176
177		pio: pinctrl@1001f000 {
178			compatible = "mediatek,mt7986a-pinctrl";
179			reg = <0 0x1001f000 0 0x1000>,
180			      <0 0x11c30000 0 0x1000>,
181			      <0 0x11c40000 0 0x1000>,
182			      <0 0x11e20000 0 0x1000>,
183			      <0 0x11e30000 0 0x1000>,
184			      <0 0x11f00000 0 0x1000>,
185			      <0 0x11f10000 0 0x1000>,
186			      <0 0x1000b000 0 0x1000>;
187			reg-names = "gpio", "iocfg_rt", "iocfg_rb", "iocfg_lt",
188				    "iocfg_lb", "iocfg_tr", "iocfg_tl", "eint";
189			gpio-controller;
190			#gpio-cells = <2>;
191			gpio-ranges = <&pio 0 0 100>;
192			interrupt-controller;
193			interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
194			interrupt-parent = <&gic>;
195			#interrupt-cells = <2>;
196		};
197
198		sgmiisys0: syscon@10060000 {
199			compatible = "mediatek,mt7986-sgmiisys_0",
200				     "syscon";
201			reg = <0 0x10060000 0 0x1000>;
202			#clock-cells = <1>;
203		};
204
205		sgmiisys1: syscon@10070000 {
206			compatible = "mediatek,mt7986-sgmiisys_1",
207				     "syscon";
208			reg = <0 0x10070000 0 0x1000>;
209			#clock-cells = <1>;
210		};
211
212		trng: trng@1020f000 {
213			compatible = "mediatek,mt7986-rng",
214				     "mediatek,mt7623-rng";
215			reg = <0 0x1020f000 0 0x100>;
216			clocks = <&infracfg CLK_INFRA_TRNG_CK>;
217			clock-names = "rng";
218			status = "disabled";
219		};
220
221		uart0: serial@11002000 {
222			compatible = "mediatek,mt7986-uart",
223				     "mediatek,mt6577-uart";
224			reg = <0 0x11002000 0 0x400>;
225			interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
226			clocks = <&infracfg CLK_INFRA_UART0_SEL>,
227				 <&infracfg CLK_INFRA_UART0_CK>;
228			clock-names = "baud", "bus";
229			assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
230					  <&infracfg CLK_INFRA_UART0_SEL>;
231			assigned-clock-parents = <&topckgen CLK_TOP_XTAL>,
232						 <&topckgen CLK_TOP_UART_SEL>;
233			status = "disabled";
234		};
235
236		uart1: serial@11003000 {
237			compatible = "mediatek,mt7986-uart",
238				     "mediatek,mt6577-uart";
239			reg = <0 0x11003000 0 0x400>;
240			interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
241			clocks = <&infracfg CLK_INFRA_UART1_SEL>,
242				 <&infracfg CLK_INFRA_UART1_CK>;
243			clock-names = "baud", "bus";
244			assigned-clocks = <&infracfg CLK_INFRA_UART1_SEL>;
245			assigned-clock-parents = <&topckgen CLK_TOP_F26M_SEL>;
246			status = "disabled";
247		};
248
249		uart2: serial@11004000 {
250			compatible = "mediatek,mt7986-uart",
251				     "mediatek,mt6577-uart";
252			reg = <0 0x11004000 0 0x400>;
253			interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
254			clocks = <&infracfg CLK_INFRA_UART2_SEL>,
255				 <&infracfg CLK_INFRA_UART2_CK>;
256			clock-names = "baud", "bus";
257			assigned-clocks = <&infracfg CLK_INFRA_UART2_SEL>;
258			assigned-clock-parents = <&topckgen CLK_TOP_F26M_SEL>;
259			status = "disabled";
260		};
261
262		ethsys: syscon@15000000 {
263			 #address-cells = <1>;
264			 #size-cells = <1>;
265			 compatible = "mediatek,mt7986-ethsys",
266				      "syscon";
267			 reg = <0 0x15000000 0 0x1000>;
268			 #clock-cells = <1>;
269			 #reset-cells = <1>;
270		};
271
272		wed_pcie: wed-pcie@10003000 {
273			compatible = "mediatek,mt7986-wed-pcie",
274				     "syscon";
275			reg = <0 0x10003000 0 0x10>;
276		};
277
278		wed0: wed@15010000 {
279			compatible = "mediatek,mt7986-wed",
280				     "syscon";
281			reg = <0 0x15010000 0 0x1000>;
282			interrupt-parent = <&gic>;
283			interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
284			memory-region = <&wo_emi0>, <&wo_ilm0>, <&wo_dlm0>,
285					<&wo_data>, <&wo_boot>;
286			memory-region-names = "wo-emi", "wo-ilm", "wo-dlm",
287					      "wo-data", "wo-boot";
288			mediatek,wo-ccif = <&wo_ccif0>;
289		};
290
291		wed1: wed@15011000 {
292			compatible = "mediatek,mt7986-wed",
293				     "syscon";
294			reg = <0 0x15011000 0 0x1000>;
295			interrupt-parent = <&gic>;
296			interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
297			memory-region = <&wo_emi1>, <&wo_ilm1>, <&wo_dlm1>,
298					<&wo_data>, <&wo_boot>;
299			memory-region-names = "wo-emi", "wo-ilm", "wo-dlm",
300					      "wo-data", "wo-boot";
301			mediatek,wo-ccif = <&wo_ccif1>;
302		};
303
304		wo_ccif0: syscon@151a5000 {
305			compatible = "mediatek,mt7986-wo-ccif", "syscon";
306			reg = <0 0x151a5000 0 0x1000>;
307			interrupt-parent = <&gic>;
308			interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
309		};
310
311		wo_ccif1: syscon@151ad000 {
312			compatible = "mediatek,mt7986-wo-ccif", "syscon";
313			reg = <0 0x151ad000 0 0x1000>;
314			interrupt-parent = <&gic>;
315			interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
316		};
317
318		eth: ethernet@15100000 {
319			compatible = "mediatek,mt7986-eth";
320			reg = <0 0x15100000 0 0x80000>;
321			interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
322				     <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
323				     <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
324				     <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
325			clocks = <&ethsys CLK_ETH_FE_EN>,
326				 <&ethsys CLK_ETH_GP2_EN>,
327				 <&ethsys CLK_ETH_GP1_EN>,
328				 <&ethsys CLK_ETH_WOCPU1_EN>,
329				 <&ethsys CLK_ETH_WOCPU0_EN>,
330				 <&sgmiisys0 CLK_SGMII0_TX250M_EN>,
331				 <&sgmiisys0 CLK_SGMII0_RX250M_EN>,
332				 <&sgmiisys0 CLK_SGMII0_CDR_REF>,
333				 <&sgmiisys0 CLK_SGMII0_CDR_FB>,
334				 <&sgmiisys1 CLK_SGMII1_TX250M_EN>,
335				 <&sgmiisys1 CLK_SGMII1_RX250M_EN>,
336				 <&sgmiisys1 CLK_SGMII1_CDR_REF>,
337				 <&sgmiisys1 CLK_SGMII1_CDR_FB>,
338				 <&topckgen CLK_TOP_NETSYS_SEL>,
339				 <&topckgen CLK_TOP_NETSYS_500M_SEL>;
340			clock-names = "fe", "gp2", "gp1", "wocpu1", "wocpu0",
341				      "sgmii_tx250m", "sgmii_rx250m",
342				      "sgmii_cdr_ref", "sgmii_cdr_fb",
343				      "sgmii2_tx250m", "sgmii2_rx250m",
344				      "sgmii2_cdr_ref", "sgmii2_cdr_fb",
345				      "netsys0", "netsys1";
346			assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>,
347					  <&topckgen CLK_TOP_SGM_325M_SEL>;
348			assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>,
349						 <&apmixedsys CLK_APMIXED_SGMPLL>;
350			mediatek,ethsys = <&ethsys>;
351			mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>;
352			mediatek,wed-pcie = <&wed_pcie>;
353			mediatek,wed = <&wed0>, <&wed1>;
354			#reset-cells = <1>;
355			#address-cells = <1>;
356			#size-cells = <0>;
357			status = "disabled";
358		};
359
360		wifi: wifi@18000000 {
361			compatible = "mediatek,mt7986-wmac";
362			resets = <&watchdog MT7986_TOPRGU_CONSYS_SW_RST>;
363			reset-names = "consys";
364			clocks = <&topckgen CLK_TOP_CONN_MCUSYS_SEL>,
365				 <&topckgen CLK_TOP_AP2CNN_HOST_SEL>;
366			clock-names = "mcu", "ap2conn";
367			reg = <0 0x18000000 0 0x1000000>,
368			      <0 0x10003000 0 0x1000>,
369			      <0 0x11d10000 0 0x1000>;
370			interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
371				     <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
372				     <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
373				     <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
374			memory-region = <&wmcpu_emi>;
375		};
376	};
377
378};
379