hi3670.dtsi (e18813021a11c4f7c7fd21deb69589db8a8f9f8c) hi3670.dtsi (dd54bb8a0a970188cda8839845920aff2e3da8a4)
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * dts file for Hisilicon Hi3670 SoC
4 *
5 * Copyright (C) 2016, Hisilicon Ltd.
6 * Copyright (C) 2018, Linaro Ltd.
7 */
8

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182 };
183
184 media2_crg: media2_crgctrl@e8900000 {
185 compatible = "hisilicon,hi3670-media2-crg","syscon";
186 reg = <0x0 0xe8900000 0x0 0x1000>;
187 #clock-cells = <1>;
188 };
189
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * dts file for Hisilicon Hi3670 SoC
4 *
5 * Copyright (C) 2016, Hisilicon Ltd.
6 * Copyright (C) 2018, Linaro Ltd.
7 */
8

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182 };
183
184 media2_crg: media2_crgctrl@e8900000 {
185 compatible = "hisilicon,hi3670-media2-crg","syscon";
186 reg = <0x0 0xe8900000 0x0 0x1000>;
187 #clock-cells = <1>;
188 };
189
190 uart0: serial@fdf02000 {
191 compatible = "arm,pl011", "arm,primecell";
192 reg = <0x0 0xfdf02000 0x0 0x1000>;
193 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
194 clocks = <&crg_ctrl HI3670_CLK_GATE_UART0>,
195 <&crg_ctrl HI3670_PCLK>;
196 clock-names = "uartclk", "apb_pclk";
197 pinctrl-names = "default";
198 pinctrl-0 = <&uart0_pmx_func &uart0_cfg_func>;
199 status = "disabled";
200 };
201
202 uart1: serial@fdf00000 {
203 compatible = "arm,pl011", "arm,primecell";
204 reg = <0x0 0xfdf00000 0x0 0x1000>;
205 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
206 clocks = <&crg_ctrl HI3670_CLK_GATE_UART1>,
207 <&crg_ctrl HI3670_PCLK>;
208 clock-names = "uartclk", "apb_pclk";
209 pinctrl-names = "default";
210 status = "disabled";
211 };
212
213 uart2: serial@fdf03000 {
214 compatible = "arm,pl011", "arm,primecell";
215 reg = <0x0 0xfdf03000 0x0 0x1000>;
216 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
217 clocks = <&crg_ctrl HI3670_CLK_GATE_UART2>,
218 <&crg_ctrl HI3670_PCLK>;
219 clock-names = "uartclk", "apb_pclk";
220 pinctrl-names = "default";
221 pinctrl-0 = <&uart2_pmx_func &uart2_cfg_func>;
222 status = "disabled";
223 };
224
225 uart3: serial@ffd74000 {
226 compatible = "arm,pl011", "arm,primecell";
227 reg = <0x0 0xffd74000 0x0 0x1000>;
228 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
229 clocks = <&crg_ctrl HI3670_CLK_GATE_UART3>,
230 <&crg_ctrl HI3670_PCLK>;
231 clock-names = "uartclk", "apb_pclk";
232 pinctrl-names = "default";
233 pinctrl-0 = <&uart3_pmx_func &uart3_cfg_func>;
234 status = "disabled";
235 };
236
237 uart4: serial@fdf01000 {
238 compatible = "arm,pl011", "arm,primecell";
239 reg = <0x0 0xfdf01000 0x0 0x1000>;
240 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
241 clocks = <&crg_ctrl HI3670_CLK_GATE_UART4>,
242 <&crg_ctrl HI3670_PCLK>;
243 clock-names = "uartclk", "apb_pclk";
244 pinctrl-names = "default";
245 pinctrl-0 = <&uart4_pmx_func &uart4_cfg_func>;
246 status = "disabled";
247 };
248
249 uart5: serial@fdf05000 {
250 compatible = "arm,pl011", "arm,primecell";
251 reg = <0x0 0xfdf05000 0x0 0x1000>;
252 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
253 clocks = <&crg_ctrl HI3670_CLK_GATE_UART5>,
254 <&crg_ctrl HI3670_PCLK>;
255 clock-names = "uartclk", "apb_pclk";
256 pinctrl-names = "default";
257 status = "disabled";
258 };
259
190 uart6: serial@fff32000 {
191 compatible = "arm,pl011", "arm,primecell";
192 reg = <0x0 0xfff32000 0x0 0x1000>;
193 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
194 clocks = <&crg_ctrl HI3670_CLK_UART6>,
195 <&crg_ctrl HI3670_PCLK>;
196 clock-names = "uartclk", "apb_pclk";
260 uart6: serial@fff32000 {
261 compatible = "arm,pl011", "arm,primecell";
262 reg = <0x0 0xfff32000 0x0 0x1000>;
263 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
264 clocks = <&crg_ctrl HI3670_CLK_UART6>,
265 <&crg_ctrl HI3670_PCLK>;
266 clock-names = "uartclk", "apb_pclk";
267 pinctrl-names = "default";
268 pinctrl-0 = <&uart6_pmx_func &uart6_cfg_func>;
197 status = "disabled";
198 };
199
200 gpio0: gpio@e8a0b000 {
201 compatible = "arm,pl061", "arm,primecell";
202 reg = <0x0 0xe8a0b000 0x0 0x1000>;
203 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
204 gpio-controller;

--- 375 unchanged lines hidden --- 		269 status = "disabled";
270 };
271
272 gpio0: gpio@e8a0b000 {
273 compatible = "arm,pl061", "arm,primecell";
274 reg = <0x0 0xe8a0b000 0x0 0x1000>;
275 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
276 gpio-controller;

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