1// SPDX-License-Identifier: GPL-2.0 2/* 3 * dts file for Hisilicon Hi3670 SoC 4 * 5 * Copyright (C) 2016, Hisilicon Ltd. 6 * Copyright (C) 2018, Linaro Ltd. 7 */ 8 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/clock/hi3670-clock.h> 11 12/ { 13 compatible = "hisilicon,hi3670"; 14 interrupt-parent = <&gic>; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 psci { 19 compatible = "arm,psci-0.2"; 20 method = "smc"; 21 }; 22 23 cpus { 24 #address-cells = <2>; 25 #size-cells = <0>; 26 27 cpu-map { 28 cluster0 { 29 core0 { 30 cpu = <&cpu0>; 31 }; 32 core1 { 33 cpu = <&cpu1>; 34 }; 35 core2 { 36 cpu = <&cpu2>; 37 }; 38 core3 { 39 cpu = <&cpu3>; 40 }; 41 }; 42 cluster1 { 43 core0 { 44 cpu = <&cpu4>; 45 }; 46 core1 { 47 cpu = <&cpu5>; 48 }; 49 core2 { 50 cpu = <&cpu6>; 51 }; 52 core3 { 53 cpu = <&cpu7>; 54 }; 55 }; 56 }; 57 58 cpu0: cpu@0 { 59 compatible = "arm,cortex-a53", "arm,armv8"; 60 device_type = "cpu"; 61 reg = <0x0 0x0>; 62 enable-method = "psci"; 63 }; 64 65 cpu1: cpu@1 { 66 compatible = "arm,cortex-a53", "arm,armv8"; 67 device_type = "cpu"; 68 reg = <0x0 0x1>; 69 enable-method = "psci"; 70 }; 71 72 cpu2: cpu@2 { 73 compatible = "arm,cortex-a53", "arm,armv8"; 74 device_type = "cpu"; 75 reg = <0x0 0x2>; 76 enable-method = "psci"; 77 }; 78 79 cpu3: cpu@3 { 80 compatible = "arm,cortex-a53", "arm,armv8"; 81 device_type = "cpu"; 82 reg = <0x0 0x3>; 83 enable-method = "psci"; 84 }; 85 86 cpu4: cpu@100 { 87 compatible = "arm,cortex-a73", "arm,armv8"; 88 device_type = "cpu"; 89 reg = <0x0 0x100>; 90 enable-method = "psci"; 91 }; 92 93 cpu5: cpu@101 { 94 compatible = "arm,cortex-a73", "arm,armv8"; 95 device_type = "cpu"; 96 reg = <0x0 0x101>; 97 enable-method = "psci"; 98 }; 99 100 cpu6: cpu@102 { 101 compatible = "arm,cortex-a73", "arm,armv8"; 102 device_type = "cpu"; 103 reg = <0x0 0x102>; 104 enable-method = "psci"; 105 }; 106 107 cpu7: cpu@103 { 108 compatible = "arm,cortex-a73", "arm,armv8"; 109 device_type = "cpu"; 110 reg = <0x0 0x103>; 111 enable-method = "psci"; 112 }; 113 }; 114 115 gic: interrupt-controller@e82b0000 { 116 compatible = "arm,gic-400"; 117 reg = <0x0 0xe82b1000 0 0x1000>, /* GICD */ 118 <0x0 0xe82b2000 0 0x2000>, /* GICC */ 119 <0x0 0xe82b4000 0 0x2000>, /* GICH */ 120 <0x0 0xe82b6000 0 0x2000>; /* GICV */ 121 #interrupt-cells = <3>; 122 #address-cells = <0>; 123 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | 124 IRQ_TYPE_LEVEL_HIGH)>; 125 interrupt-controller; 126 }; 127 128 timer { 129 compatible = "arm,armv8-timer"; 130 interrupt-parent = <&gic>; 131 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | 132 IRQ_TYPE_LEVEL_LOW)>, 133 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | 134 IRQ_TYPE_LEVEL_LOW)>, 135 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | 136 IRQ_TYPE_LEVEL_LOW)>, 137 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | 138 IRQ_TYPE_LEVEL_LOW)>; 139 clock-frequency = <1920000>; 140 }; 141 142 soc { 143 compatible = "simple-bus"; 144 #address-cells = <2>; 145 #size-cells = <2>; 146 ranges; 147 148 crg_ctrl: crg_ctrl@fff35000 { 149 compatible = "hisilicon,hi3670-crgctrl", "syscon"; 150 reg = <0x0 0xfff35000 0x0 0x1000>; 151 #clock-cells = <1>; 152 }; 153 154 pctrl: pctrl@e8a09000 { 155 compatible = "hisilicon,hi3670-pctrl", "syscon"; 156 reg = <0x0 0xe8a09000 0x0 0x1000>; 157 #clock-cells = <1>; 158 }; 159 160 pmuctrl: crg_ctrl@fff34000 { 161 compatible = "hisilicon,hi3670-pmuctrl", "syscon"; 162 reg = <0x0 0xfff34000 0x0 0x1000>; 163 #clock-cells = <1>; 164 }; 165 166 sctrl: sctrl@fff0a000 { 167 compatible = "hisilicon,hi3670-sctrl", "syscon"; 168 reg = <0x0 0xfff0a000 0x0 0x1000>; 169 #clock-cells = <1>; 170 }; 171 172 iomcu: iomcu@ffd7e000 { 173 compatible = "hisilicon,hi3670-iomcu", "syscon"; 174 reg = <0x0 0xffd7e000 0x0 0x1000>; 175 #clock-cells = <1>; 176 }; 177 178 media1_crg: media1_crgctrl@e87ff000 { 179 compatible = "hisilicon,hi3670-media1-crg", "syscon"; 180 reg = <0x0 0xe87ff000 0x0 0x1000>; 181 #clock-cells = <1>; 182 }; 183 184 media2_crg: media2_crgctrl@e8900000 { 185 compatible = "hisilicon,hi3670-media2-crg","syscon"; 186 reg = <0x0 0xe8900000 0x0 0x1000>; 187 #clock-cells = <1>; 188 }; 189 190 uart6: serial@fff32000 { 191 compatible = "arm,pl011", "arm,primecell"; 192 reg = <0x0 0xfff32000 0x0 0x1000>; 193 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 194 clocks = <&crg_ctrl HI3670_CLK_UART6>, 195 <&crg_ctrl HI3670_PCLK>; 196 clock-names = "uartclk", "apb_pclk"; 197 status = "disabled"; 198 }; 199 200 gpio0: gpio@e8a0b000 { 201 compatible = "arm,pl061", "arm,primecell"; 202 reg = <0x0 0xe8a0b000 0x0 0x1000>; 203 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 204 gpio-controller; 205 #gpio-cells = <2>; 206 gpio-ranges = <&pmx0 1 0 1 &pmx0 3 1 5>; 207 interrupt-controller; 208 #interrupt-cells = <2>; 209 clocks = <&crg_ctrl HI3670_PCLK_GPIO0>; 210 clock-names = "apb_pclk"; 211 }; 212 213 gpio1: gpio@e8a0c000 { 214 compatible = "arm,pl061", "arm,primecell"; 215 reg = <0x0 0xe8a0c000 0x0 0x1000>; 216 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 217 gpio-controller; 218 #gpio-cells = <2>; 219 interrupt-controller; 220 #interrupt-cells = <2>; 221 clocks = <&crg_ctrl HI3670_PCLK_GPIO1>; 222 clock-names = "apb_pclk"; 223 }; 224 225 gpio2: gpio@e8a0d000 { 226 compatible = "arm,pl061", "arm,primecell"; 227 reg = <0x0 0xe8a0d000 0x0 0x1000>; 228 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 229 gpio-controller; 230 #gpio-cells = <2>; 231 gpio-ranges = <&pmx0 1 6 7>; 232 interrupt-controller; 233 #interrupt-cells = <2>; 234 clocks = <&crg_ctrl HI3670_PCLK_GPIO2>; 235 clock-names = "apb_pclk"; 236 }; 237 238 gpio3: gpio@e8a0e000 { 239 compatible = "arm,pl061", "arm,primecell"; 240 reg = <0x0 0xe8a0e000 0x0 0x1000>; 241 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 242 gpio-controller; 243 #gpio-cells = <2>; 244 gpio-ranges = <&pmx0 0 13 4 &pmx0 7 17 1>; 245 interrupt-controller; 246 #interrupt-cells = <2>; 247 clocks = <&crg_ctrl HI3670_PCLK_GPIO3>; 248 clock-names = "apb_pclk"; 249 }; 250 251 gpio4: gpio@e8a0f000 { 252 compatible = "arm,pl061", "arm,primecell"; 253 reg = <0x0 0xe8a0f000 0x0 0x1000>; 254 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 255 gpio-controller; 256 #gpio-cells = <2>; 257 gpio-ranges = <&pmx0 0 18 8>; 258 interrupt-controller; 259 #interrupt-cells = <2>; 260 clocks = <&crg_ctrl HI3670_PCLK_GPIO4>; 261 clock-names = "apb_pclk"; 262 }; 263 264 gpio5: gpio@e8a10000 { 265 compatible = "arm,pl061", "arm,primecell"; 266 reg = <0x0 0xe8a10000 0x0 0x1000>; 267 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 268 gpio-controller; 269 #gpio-cells = <2>; 270 gpio-ranges = <&pmx0 0 26 8>; 271 interrupt-controller; 272 #interrupt-cells = <2>; 273 clocks = <&crg_ctrl HI3670_PCLK_GPIO5>; 274 clock-names = "apb_pclk"; 275 }; 276 277 gpio6: gpio@e8a11000 { 278 compatible = "arm,pl061", "arm,primecell"; 279 reg = <0x0 0xe8a11000 0x0 0x1000>; 280 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 281 gpio-controller; 282 #gpio-cells = <2>; 283 gpio-ranges = <&pmx0 1 34 7>; 284 interrupt-controller; 285 #interrupt-cells = <2>; 286 clocks = <&crg_ctrl HI3670_PCLK_GPIO6>; 287 clock-names = "apb_pclk"; 288 }; 289 290 gpio7: gpio@e8a12000 { 291 compatible = "arm,pl061", "arm,primecell"; 292 reg = <0x0 0xe8a12000 0x0 0x1000>; 293 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 294 gpio-controller; 295 #gpio-cells = <2>; 296 gpio-ranges = <&pmx0 0 41 8>; 297 interrupt-controller; 298 #interrupt-cells = <2>; 299 clocks = <&crg_ctrl HI3670_PCLK_GPIO7>; 300 clock-names = "apb_pclk"; 301 }; 302 303 gpio8: gpio@e8a13000 { 304 compatible = "arm,pl061", "arm,primecell"; 305 reg = <0x0 0xe8a13000 0x0 0x1000>; 306 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 307 gpio-controller; 308 #gpio-cells = <2>; 309 gpio-ranges = <&pmx0 0 49 8>; 310 interrupt-controller; 311 #interrupt-cells = <2>; 312 clocks = <&crg_ctrl HI3670_PCLK_GPIO8>; 313 clock-names = "apb_pclk"; 314 }; 315 316 gpio9: gpio@e8a14000 { 317 compatible = "arm,pl061", "arm,primecell"; 318 reg = <0x0 0xe8a14000 0x0 0x1000>; 319 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 320 gpio-controller; 321 #gpio-cells = <2>; 322 gpio-ranges = <&pmx0 0 57 8>; 323 interrupt-controller; 324 #interrupt-cells = <2>; 325 clocks = <&crg_ctrl HI3670_PCLK_GPIO9>; 326 clock-names = "apb_pclk"; 327 }; 328 329 gpio10: gpio@e8a15000 { 330 compatible = "arm,pl061", "arm,primecell"; 331 reg = <0x0 0xe8a15000 0x0 0x1000>; 332 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 333 gpio-controller; 334 #gpio-cells = <2>; 335 gpio-ranges = <&pmx0 0 65 8>; 336 interrupt-controller; 337 #interrupt-cells = <2>; 338 clocks = <&crg_ctrl HI3670_PCLK_GPIO10>; 339 clock-names = "apb_pclk"; 340 }; 341 342 gpio11: gpio@e8a16000 { 343 compatible = "arm,pl061", "arm,primecell"; 344 reg = <0x0 0xe8a16000 0x0 0x1000>; 345 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 346 gpio-controller; 347 #gpio-cells = <2>; 348 gpio-ranges = <&pmx0 0 73 8>; 349 interrupt-controller; 350 #interrupt-cells = <2>; 351 clocks = <&crg_ctrl HI3670_PCLK_GPIO11>; 352 clock-names = "apb_pclk"; 353 }; 354 355 gpio12: gpio@e8a17000 { 356 compatible = "arm,pl061", "arm,primecell"; 357 reg = <0x0 0xe8a17000 0x0 0x1000>; 358 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 359 gpio-controller; 360 #gpio-cells = <2>; 361 gpio-ranges = <&pmx0 0 81 1>; 362 interrupt-controller; 363 #interrupt-cells = <2>; 364 clocks = <&crg_ctrl HI3670_PCLK_GPIO12>; 365 clock-names = "apb_pclk"; 366 }; 367 368 gpio13: gpio@e8a18000 { 369 compatible = "arm,pl061", "arm,primecell"; 370 reg = <0x0 0xe8a18000 0x0 0x1000>; 371 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 372 gpio-controller; 373 #gpio-cells = <2>; 374 interrupt-controller; 375 #interrupt-cells = <2>; 376 clocks = <&crg_ctrl HI3670_PCLK_GPIO13>; 377 clock-names = "apb_pclk"; 378 }; 379 380 gpio14: gpio@e8a19000 { 381 compatible = "arm,pl061", "arm,primecell"; 382 reg = <0x0 0xe8a19000 0x0 0x1000>; 383 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 384 gpio-controller; 385 #gpio-cells = <2>; 386 interrupt-controller; 387 #interrupt-cells = <2>; 388 clocks = <&crg_ctrl HI3670_PCLK_GPIO14>; 389 clock-names = "apb_pclk"; 390 }; 391 392 gpio15: gpio@e8a1a000 { 393 compatible = "arm,pl061", "arm,primecell"; 394 reg = <0x0 0xe8a1a000 0x0 0x1000>; 395 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 396 gpio-controller; 397 #gpio-cells = <2>; 398 interrupt-controller; 399 #interrupt-cells = <2>; 400 clocks = <&crg_ctrl HI3670_PCLK_GPIO15>; 401 clock-names = "apb_pclk"; 402 }; 403 404 gpio16: gpio@e8a1b000 { 405 compatible = "arm,pl061", "arm,primecell"; 406 reg = <0x0 0xe8a1b000 0x0 0x1000>; 407 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 408 gpio-controller; 409 #gpio-cells = <2>; 410 gpio-ranges = <&pmx5 0 0 8>; 411 interrupt-controller; 412 #interrupt-cells = <2>; 413 clocks = <&crg_ctrl HI3670_PCLK_GPIO16>; 414 clock-names = "apb_pclk"; 415 }; 416 417 gpio17: gpio@e8a1c000 { 418 compatible = "arm,pl061", "arm,primecell"; 419 reg = <0x0 0xe8a1c000 0x0 0x1000>; 420 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 421 gpio-controller; 422 #gpio-cells = <2>; 423 gpio-ranges = <&pmx5 0 8 2>; 424 interrupt-controller; 425 #interrupt-cells = <2>; 426 clocks = <&crg_ctrl HI3670_PCLK_GPIO17>; 427 clock-names = "apb_pclk"; 428 }; 429 430 gpio18: gpio@fff28000 { 431 compatible = "arm,pl061", "arm,primecell"; 432 reg = <0x0 0xfff28000 0x0 0x1000>; 433 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 434 gpio-controller; 435 #gpio-cells = <2>; 436 gpio-ranges = <&pmx1 4 42 4>; 437 interrupt-controller; 438 #interrupt-cells = <2>; 439 clocks = <&sctrl HI3670_PCLK_GPIO18>; 440 clock-names = "apb_pclk"; 441 }; 442 443 gpio19: gpio@fff29000 { 444 compatible = "arm,pl061", "arm,primecell"; 445 reg = <0x0 0xfff29000 0x0 0x1000>; 446 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 447 gpio-controller; 448 #gpio-cells = <2>; 449 gpio-ranges = <&pmx1 0 61 2>; 450 interrupt-controller; 451 #interrupt-cells = <2>; 452 clocks = <&sctrl HI3670_PCLK_GPIO19>; 453 clock-names = "apb_pclk"; 454 }; 455 456 gpio20: gpio@e8a1f000 { 457 compatible = "arm,pl061", "arm,primecell"; 458 reg = <0x0 0xe8a1f000 0x0 0x1000>; 459 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 460 gpio-controller; 461 #gpio-cells = <2>; 462 gpio-ranges = <&pmx7 0 0 8>; 463 interrupt-controller; 464 #interrupt-cells = <2>; 465 clocks = <&crg_ctrl HI3670_PCLK_GPIO20>; 466 clock-names = "apb_pclk"; 467 }; 468 469 gpio21: gpio@e8a20000 { 470 compatible = "arm,pl061", "arm,primecell"; 471 reg = <0x0 0xe8a20000 0x0 0x1000>; 472 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 473 gpio-controller; 474 #gpio-cells = <2>; 475 gpio-ranges = <&pmx7 0 8 4>; 476 interrupt-controller; 477 #interrupt-cells = <2>; 478 clocks = <&crg_ctrl HI3670_PCLK_GPIO21>; 479 clock-names = "apb_pclk"; 480 }; 481 482 gpio22: gpio@fff0b000 { 483 compatible = "arm,pl061", "arm,primecell"; 484 reg = <0x0 0xfff0b000 0x0 0x1000>; 485 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 486 gpio-controller; 487 #gpio-cells = <2>; 488 /* GPIO176 */ 489 gpio-ranges = <&pmx1 2 0 6>; 490 interrupt-controller; 491 #interrupt-cells = <2>; 492 clocks = <&sctrl HI3670_PCLK_AO_GPIO0>; 493 clock-names = "apb_pclk"; 494 }; 495 496 gpio23: gpio@fff0c000 { 497 compatible = "arm,pl061", "arm,primecell"; 498 reg = <0x0 0xfff0c000 0x0 0x1000>; 499 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 500 gpio-controller; 501 #gpio-cells = <2>; 502 /* GPIO184 */ 503 gpio-ranges = <&pmx1 0 6 8>; 504 interrupt-controller; 505 #interrupt-cells = <2>; 506 clocks = <&sctrl HI3670_PCLK_AO_GPIO1>; 507 clock-names = "apb_pclk"; 508 }; 509 510 gpio24: gpio@fff0d000 { 511 compatible = "arm,pl061", "arm,primecell"; 512 reg = <0x0 0xfff0d000 0x0 0x1000>; 513 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 514 gpio-controller; 515 #gpio-cells = <2>; 516 /* GPIO192 */ 517 gpio-ranges = <&pmx1 0 14 8>; 518 interrupt-controller; 519 #interrupt-cells = <2>; 520 clocks = <&sctrl HI3670_PCLK_AO_GPIO2>; 521 clock-names = "apb_pclk"; 522 }; 523 524 gpio25: gpio@fff0e000 { 525 compatible = "arm,pl061", "arm,primecell"; 526 reg = <0x0 0xfff0e000 0x0 0x1000>; 527 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 528 gpio-controller; 529 #gpio-cells = <2>; 530 /* GPIO200 */ 531 gpio-ranges = <&pmx1 0 22 8>; 532 interrupt-controller; 533 #interrupt-cells = <2>; 534 clocks = <&sctrl HI3670_PCLK_AO_GPIO3>; 535 clock-names = "apb_pclk"; 536 }; 537 538 gpio26: gpio@fff0f000 { 539 compatible = "arm,pl061", "arm,primecell"; 540 reg = <0x0 0xfff0f000 0x0 0x1000>; 541 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 542 gpio-controller; 543 #gpio-cells = <2>; 544 /* GPIO208 */ 545 gpio-ranges = <&pmx1 0 30 1>; 546 interrupt-controller; 547 #interrupt-cells = <2>; 548 clocks = <&sctrl HI3670_PCLK_AO_GPIO4>; 549 clock-names = "apb_pclk"; 550 }; 551 552 gpio27: gpio@fff10000 { 553 compatible = "arm,pl061", "arm,primecell"; 554 reg = <0x0 0xfff10000 0x0 0x1000>; 555 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 556 gpio-controller; 557 #gpio-cells = <2>; 558 /* GPIO216 */ 559 gpio-ranges = <&pmx1 4 31 4>; 560 interrupt-controller; 561 #interrupt-cells = <2>; 562 clocks = <&sctrl HI3670_PCLK_AO_GPIO5>; 563 clock-names = "apb_pclk"; 564 }; 565 566 gpio28: gpio@fff1d000 { 567 compatible = "arm,pl061", "arm,primecell"; 568 reg = <0x0 0xfff1d000 0x0 0x1000>; 569 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 570 gpio-controller; 571 #gpio-cells = <2>; 572 gpio-ranges = <&pmx1 1 35 7>; 573 interrupt-controller; 574 #interrupt-cells = <2>; 575 clocks = <&sctrl HI3670_PCLK_AO_GPIO6>; 576 clock-names = "apb_pclk"; 577 }; 578 }; 579}; 580