| proc-v7.S (25985edcedea6396277003854657b5f3cb31a628) | proc-v7.S (29ea23ff905d07d8559bac69cca46f4bbf20038c) |
|---|---|
| 1/* 2 * linux/arch/arm/mm/proc-v7.S 3 * 4 * Copyright (C) 2001 Deep Blue Solutions Ltd. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. --- 197 unchanged lines hidden (view full) --- 206 * NOS = PRRR[24+n] = 1 - not outer shareable 207 */ 208.equ PRRR, 0xff0a81a8 209.equ NMRR, 0x40e040e0 210 211/* Suspend/resume support: derived from arch/arm/mach-s5pv210/sleep.S */ 212.globl cpu_v7_suspend_size 213.equ cpu_v7_suspend_size, 4 * 8 | 1/* 2 * linux/arch/arm/mm/proc-v7.S 3 * 4 * Copyright (C) 2001 Deep Blue Solutions Ltd. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. --- 197 unchanged lines hidden (view full) --- 206 * NOS = PRRR[24+n] = 1 - not outer shareable 207 */ 208.equ PRRR, 0xff0a81a8 209.equ NMRR, 0x40e040e0 210 211/* Suspend/resume support: derived from arch/arm/mach-s5pv210/sleep.S */ 212.globl cpu_v7_suspend_size 213.equ cpu_v7_suspend_size, 4 * 8 |
| 214#ifdef CONFIG_PM | 214#ifdef CONFIG_PM_SLEEP |
| 215ENTRY(cpu_v7_do_suspend) 216 stmfd sp!, {r4 - r11, lr} 217 mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID 218 mrc p15, 0, r5, c13, c0, 1 @ Context ID 219 mrc p15, 0, r6, c3, c0, 0 @ Domain ID 220 mrc p15, 0, r7, c2, c0, 0 @ TTB 0 221 mrc p15, 0, r8, c2, c0, 1 @ TTB 1 222 mrc p15, 0, r9, c1, c0, 0 @ Control register --- 9 unchanged lines hidden (view full) --- 232 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache 233 ldmia r0, {r4 - r11} 234 mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID 235 mcr p15, 0, r5, c13, c0, 1 @ Context ID 236 mcr p15, 0, r6, c3, c0, 0 @ Domain ID 237 mcr p15, 0, r7, c2, c0, 0 @ TTB 0 238 mcr p15, 0, r8, c2, c0, 1 @ TTB 1 239 mcr p15, 0, ip, c2, c0, 2 @ TTB control register | 215ENTRY(cpu_v7_do_suspend) 216 stmfd sp!, {r4 - r11, lr} 217 mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID 218 mrc p15, 0, r5, c13, c0, 1 @ Context ID 219 mrc p15, 0, r6, c3, c0, 0 @ Domain ID 220 mrc p15, 0, r7, c2, c0, 0 @ TTB 0 221 mrc p15, 0, r8, c2, c0, 1 @ TTB 1 222 mrc p15, 0, r9, c1, c0, 0 @ Control register --- 9 unchanged lines hidden (view full) --- 232 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache 233 ldmia r0, {r4 - r11} 234 mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID 235 mcr p15, 0, r5, c13, c0, 1 @ Context ID 236 mcr p15, 0, r6, c3, c0, 0 @ Domain ID 237 mcr p15, 0, r7, c2, c0, 0 @ TTB 0 238 mcr p15, 0, r8, c2, c0, 1 @ TTB 1 239 mcr p15, 0, ip, c2, c0, 2 @ TTB control register |
| 240 mcr p15, 0, r10, c1, c0, 1 @ Auxiliary control register | 240 mcr p15, 0, r10, c1, c0, 1 @ Auxillary control register |
| 241 mcr p15, 0, r11, c1, c0, 2 @ Co-processor access control 242 ldr r4, =PRRR @ PRRR 243 ldr r5, =NMRR @ NMRR 244 mcr p15, 0, r4, c10, c2, 0 @ write PRRR 245 mcr p15, 0, r5, c10, c2, 1 @ write NMRR 246 isb 247 mov r0, r9 @ control register 248 mov r2, r7, lsr #14 @ get TTB0 base --- 250 unchanged lines hidden --- | 241 mcr p15, 0, r11, c1, c0, 2 @ Co-processor access control 242 ldr r4, =PRRR @ PRRR 243 ldr r5, =NMRR @ NMRR 244 mcr p15, 0, r4, c10, c2, 0 @ write PRRR 245 mcr p15, 0, r5, c10, c2, 1 @ write NMRR 246 isb 247 mov r0, r9 @ control register 248 mov r2, r7, lsr #14 @ get TTB0 base --- 250 unchanged lines hidden --- |