1/* 2 * linux/arch/arm/mm/proc-v7.S 3 * 4 * Copyright (C) 2001 Deep Blue Solutions Ltd. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 * This is the "shell" of the ARMv7 processor support. 11 */ 12#include <linux/init.h> 13#include <linux/linkage.h> 14#include <asm/assembler.h> 15#include <asm/asm-offsets.h> 16#include <asm/hwcap.h> 17#include <asm/pgtable-hwdef.h> 18#include <asm/pgtable.h> 19 20#include "proc-macros.S" 21 22#define TTB_S (1 << 1) 23#define TTB_RGN_NC (0 << 3) 24#define TTB_RGN_OC_WBWA (1 << 3) 25#define TTB_RGN_OC_WT (2 << 3) 26#define TTB_RGN_OC_WB (3 << 3) 27#define TTB_NOS (1 << 5) 28#define TTB_IRGN_NC ((0 << 0) | (0 << 6)) 29#define TTB_IRGN_WBWA ((0 << 0) | (1 << 6)) 30#define TTB_IRGN_WT ((1 << 0) | (0 << 6)) 31#define TTB_IRGN_WB ((1 << 0) | (1 << 6)) 32 33/* PTWs cacheable, inner WB not shareable, outer WB not shareable */ 34#define TTB_FLAGS_UP TTB_IRGN_WB|TTB_RGN_OC_WB 35#define PMD_FLAGS_UP PMD_SECT_WB 36 37/* PTWs cacheable, inner WBWA shareable, outer WBWA not shareable */ 38#define TTB_FLAGS_SMP TTB_IRGN_WBWA|TTB_S|TTB_NOS|TTB_RGN_OC_WBWA 39#define PMD_FLAGS_SMP PMD_SECT_WBWA|PMD_SECT_S 40 41ENTRY(cpu_v7_proc_init) 42 mov pc, lr 43ENDPROC(cpu_v7_proc_init) 44 45ENTRY(cpu_v7_proc_fin) 46 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 47 bic r0, r0, #0x1000 @ ...i............ 48 bic r0, r0, #0x0006 @ .............ca. 49 mcr p15, 0, r0, c1, c0, 0 @ disable caches 50 mov pc, lr 51ENDPROC(cpu_v7_proc_fin) 52 53/* 54 * cpu_v7_reset(loc) 55 * 56 * Perform a soft reset of the system. Put the CPU into the 57 * same state as it would be if it had been reset, and branch 58 * to what would be the reset vector. 59 * 60 * - loc - location to jump to for soft reset 61 */ 62 .align 5 63ENTRY(cpu_v7_reset) 64 mov pc, r0 65ENDPROC(cpu_v7_reset) 66 67/* 68 * cpu_v7_do_idle() 69 * 70 * Idle the processor (eg, wait for interrupt). 71 * 72 * IRQs are already disabled. 73 */ 74ENTRY(cpu_v7_do_idle) 75 dsb @ WFI may enter a low-power mode 76 wfi 77 mov pc, lr 78ENDPROC(cpu_v7_do_idle) 79 80ENTRY(cpu_v7_dcache_clean_area) 81#ifndef TLB_CAN_READ_FROM_L1_CACHE 82 dcache_line_size r2, r3 831: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 84 add r0, r0, r2 85 subs r1, r1, r2 86 bhi 1b 87 dsb 88#endif 89 mov pc, lr 90ENDPROC(cpu_v7_dcache_clean_area) 91 92/* 93 * cpu_v7_switch_mm(pgd_phys, tsk) 94 * 95 * Set the translation table base pointer to be pgd_phys 96 * 97 * - pgd_phys - physical address of new TTB 98 * 99 * It is assumed that: 100 * - we are not using split page tables 101 */ 102ENTRY(cpu_v7_switch_mm) 103#ifdef CONFIG_MMU 104 mov r2, #0 105 ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id 106 ALT_SMP(orr r0, r0, #TTB_FLAGS_SMP) 107 ALT_UP(orr r0, r0, #TTB_FLAGS_UP) 108#ifdef CONFIG_ARM_ERRATA_430973 109 mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB 110#endif 111#ifdef CONFIG_ARM_ERRATA_754322 112 dsb 113#endif 114 mcr p15, 0, r2, c13, c0, 1 @ set reserved context ID 115 isb 1161: mcr p15, 0, r0, c2, c0, 0 @ set TTB 0 117 isb 118#ifdef CONFIG_ARM_ERRATA_754322 119 dsb 120#endif 121 mcr p15, 0, r1, c13, c0, 1 @ set context ID 122 isb 123#endif 124 mov pc, lr 125ENDPROC(cpu_v7_switch_mm) 126 127/* 128 * cpu_v7_set_pte_ext(ptep, pte) 129 * 130 * Set a level 2 translation table entry. 131 * 132 * - ptep - pointer to level 2 translation table entry 133 * (hardware version is stored at +2048 bytes) 134 * - pte - PTE value to store 135 * - ext - value for extended PTE bits 136 */ 137ENTRY(cpu_v7_set_pte_ext) 138#ifdef CONFIG_MMU 139 str r1, [r0] @ linux version 140 141 bic r3, r1, #0x000003f0 142 bic r3, r3, #PTE_TYPE_MASK 143 orr r3, r3, r2 144 orr r3, r3, #PTE_EXT_AP0 | 2 145 146 tst r1, #1 << 4 147 orrne r3, r3, #PTE_EXT_TEX(1) 148 149 eor r1, r1, #L_PTE_DIRTY 150 tst r1, #L_PTE_RDONLY | L_PTE_DIRTY 151 orrne r3, r3, #PTE_EXT_APX 152 153 tst r1, #L_PTE_USER 154 orrne r3, r3, #PTE_EXT_AP1 155#ifdef CONFIG_CPU_USE_DOMAINS 156 @ allow kernel read/write access to read-only user pages 157 tstne r3, #PTE_EXT_APX 158 bicne r3, r3, #PTE_EXT_APX | PTE_EXT_AP0 159#endif 160 161 tst r1, #L_PTE_XN 162 orrne r3, r3, #PTE_EXT_XN 163 164 tst r1, #L_PTE_YOUNG 165 tstne r1, #L_PTE_PRESENT 166 moveq r3, #0 167 168 ARM( str r3, [r0, #2048]! ) 169 THUMB( add r0, r0, #2048 ) 170 THUMB( str r3, [r0] ) 171 mcr p15, 0, r0, c7, c10, 1 @ flush_pte 172#endif 173 mov pc, lr 174ENDPROC(cpu_v7_set_pte_ext) 175 176cpu_v7_name: 177 .ascii "ARMv7 Processor" 178 .align 179 180 /* 181 * Memory region attributes with SCTLR.TRE=1 182 * 183 * n = TEX[0],C,B 184 * TR = PRRR[2n+1:2n] - memory type 185 * IR = NMRR[2n+1:2n] - inner cacheable property 186 * OR = NMRR[2n+17:2n+16] - outer cacheable property 187 * 188 * n TR IR OR 189 * UNCACHED 000 00 190 * BUFFERABLE 001 10 00 00 191 * WRITETHROUGH 010 10 10 10 192 * WRITEBACK 011 10 11 11 193 * reserved 110 194 * WRITEALLOC 111 10 01 01 195 * DEV_SHARED 100 01 196 * DEV_NONSHARED 100 01 197 * DEV_WC 001 10 198 * DEV_CACHED 011 10 199 * 200 * Other attributes: 201 * 202 * DS0 = PRRR[16] = 0 - device shareable property 203 * DS1 = PRRR[17] = 1 - device shareable property 204 * NS0 = PRRR[18] = 0 - normal shareable property 205 * NS1 = PRRR[19] = 1 - normal shareable property 206 * NOS = PRRR[24+n] = 1 - not outer shareable 207 */ 208.equ PRRR, 0xff0a81a8 209.equ NMRR, 0x40e040e0 210 211/* Suspend/resume support: derived from arch/arm/mach-s5pv210/sleep.S */ 212.globl cpu_v7_suspend_size 213.equ cpu_v7_suspend_size, 4 * 8 214#ifdef CONFIG_PM_SLEEP 215ENTRY(cpu_v7_do_suspend) 216 stmfd sp!, {r4 - r11, lr} 217 mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID 218 mrc p15, 0, r5, c13, c0, 1 @ Context ID 219 mrc p15, 0, r6, c3, c0, 0 @ Domain ID 220 mrc p15, 0, r7, c2, c0, 0 @ TTB 0 221 mrc p15, 0, r8, c2, c0, 1 @ TTB 1 222 mrc p15, 0, r9, c1, c0, 0 @ Control register 223 mrc p15, 0, r10, c1, c0, 1 @ Auxiliary control register 224 mrc p15, 0, r11, c1, c0, 2 @ Co-processor access control 225 stmia r0, {r4 - r11} 226 ldmfd sp!, {r4 - r11, pc} 227ENDPROC(cpu_v7_do_suspend) 228 229ENTRY(cpu_v7_do_resume) 230 mov ip, #0 231 mcr p15, 0, ip, c8, c7, 0 @ invalidate TLBs 232 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache 233 ldmia r0, {r4 - r11} 234 mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID 235 mcr p15, 0, r5, c13, c0, 1 @ Context ID 236 mcr p15, 0, r6, c3, c0, 0 @ Domain ID 237 mcr p15, 0, r7, c2, c0, 0 @ TTB 0 238 mcr p15, 0, r8, c2, c0, 1 @ TTB 1 239 mcr p15, 0, ip, c2, c0, 2 @ TTB control register 240 mcr p15, 0, r10, c1, c0, 1 @ Auxillary control register 241 mcr p15, 0, r11, c1, c0, 2 @ Co-processor access control 242 ldr r4, =PRRR @ PRRR 243 ldr r5, =NMRR @ NMRR 244 mcr p15, 0, r4, c10, c2, 0 @ write PRRR 245 mcr p15, 0, r5, c10, c2, 1 @ write NMRR 246 isb 247 mov r0, r9 @ control register 248 mov r2, r7, lsr #14 @ get TTB0 base 249 mov r2, r2, lsl #14 250 ldr r3, cpu_resume_l1_flags 251 b cpu_resume_mmu 252ENDPROC(cpu_v7_do_resume) 253cpu_resume_l1_flags: 254 ALT_SMP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_FLAGS_SMP) 255 ALT_UP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_FLAGS_UP) 256#else 257#define cpu_v7_do_suspend 0 258#define cpu_v7_do_resume 0 259#endif 260 261 __CPUINIT 262 263/* 264 * __v7_setup 265 * 266 * Initialise TLB, Caches, and MMU state ready to switch the MMU 267 * on. Return in r0 the new CP15 C1 control register setting. 268 * 269 * We automatically detect if we have a Harvard cache, and use the 270 * Harvard cache control instructions insead of the unified cache 271 * control instructions. 272 * 273 * This should be able to cover all ARMv7 cores. 274 * 275 * It is assumed that: 276 * - cache type register is implemented 277 */ 278__v7_ca9mp_setup: 279#ifdef CONFIG_SMP 280 ALT_SMP(mrc p15, 0, r0, c1, c0, 1) 281 ALT_UP(mov r0, #(1 << 6)) @ fake it for UP 282 tst r0, #(1 << 6) @ SMP/nAMP mode enabled? 283 orreq r0, r0, #(1 << 6) | (1 << 0) @ Enable SMP/nAMP mode and 284 mcreq p15, 0, r0, c1, c0, 1 @ TLB ops broadcasting 285#endif 286__v7_setup: 287 adr r12, __v7_setup_stack @ the local stack 288 stmia r12, {r0-r5, r7, r9, r11, lr} 289 bl v7_flush_dcache_all 290 ldmia r12, {r0-r5, r7, r9, r11, lr} 291 292 mrc p15, 0, r0, c0, c0, 0 @ read main ID register 293 and r10, r0, #0xff000000 @ ARM? 294 teq r10, #0x41000000 295 bne 3f 296 and r5, r0, #0x00f00000 @ variant 297 and r6, r0, #0x0000000f @ revision 298 orr r6, r6, r5, lsr #20-4 @ combine variant and revision 299 ubfx r0, r0, #4, #12 @ primary part number 300 301 /* Cortex-A8 Errata */ 302 ldr r10, =0x00000c08 @ Cortex-A8 primary part number 303 teq r0, r10 304 bne 2f 305#ifdef CONFIG_ARM_ERRATA_430973 306 teq r5, #0x00100000 @ only present in r1p* 307 mrceq p15, 0, r10, c1, c0, 1 @ read aux control register 308 orreq r10, r10, #(1 << 6) @ set IBE to 1 309 mcreq p15, 0, r10, c1, c0, 1 @ write aux control register 310#endif 311#ifdef CONFIG_ARM_ERRATA_458693 312 teq r6, #0x20 @ only present in r2p0 313 mrceq p15, 0, r10, c1, c0, 1 @ read aux control register 314 orreq r10, r10, #(1 << 5) @ set L1NEON to 1 315 orreq r10, r10, #(1 << 9) @ set PLDNOP to 1 316 mcreq p15, 0, r10, c1, c0, 1 @ write aux control register 317#endif 318#ifdef CONFIG_ARM_ERRATA_460075 319 teq r6, #0x20 @ only present in r2p0 320 mrceq p15, 1, r10, c9, c0, 2 @ read L2 cache aux ctrl register 321 tsteq r10, #1 << 22 322 orreq r10, r10, #(1 << 22) @ set the Write Allocate disable bit 323 mcreq p15, 1, r10, c9, c0, 2 @ write the L2 cache aux ctrl register 324#endif 325 b 3f 326 327 /* Cortex-A9 Errata */ 3282: ldr r10, =0x00000c09 @ Cortex-A9 primary part number 329 teq r0, r10 330 bne 3f 331#ifdef CONFIG_ARM_ERRATA_742230 332 cmp r6, #0x22 @ only present up to r2p2 333 mrcle p15, 0, r10, c15, c0, 1 @ read diagnostic register 334 orrle r10, r10, #1 << 4 @ set bit #4 335 mcrle p15, 0, r10, c15, c0, 1 @ write diagnostic register 336#endif 337#ifdef CONFIG_ARM_ERRATA_742231 338 teq r6, #0x20 @ present in r2p0 339 teqne r6, #0x21 @ present in r2p1 340 teqne r6, #0x22 @ present in r2p2 341 mrceq p15, 0, r10, c15, c0, 1 @ read diagnostic register 342 orreq r10, r10, #1 << 12 @ set bit #12 343 orreq r10, r10, #1 << 22 @ set bit #22 344 mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register 345#endif 346#ifdef CONFIG_ARM_ERRATA_743622 347 teq r6, #0x20 @ present in r2p0 348 teqne r6, #0x21 @ present in r2p1 349 teqne r6, #0x22 @ present in r2p2 350 mrceq p15, 0, r10, c15, c0, 1 @ read diagnostic register 351 orreq r10, r10, #1 << 6 @ set bit #6 352 mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register 353#endif 354#ifdef CONFIG_ARM_ERRATA_751472 355 cmp r6, #0x30 @ present prior to r3p0 356 mrclt p15, 0, r10, c15, c0, 1 @ read diagnostic register 357 orrlt r10, r10, #1 << 11 @ set bit #11 358 mcrlt p15, 0, r10, c15, c0, 1 @ write diagnostic register 359#endif 360 3613: mov r10, #0 362#ifdef HARVARD_CACHE 363 mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate 364#endif 365 dsb 366#ifdef CONFIG_MMU 367 mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs 368 mcr p15, 0, r10, c2, c0, 2 @ TTB control register 369 ALT_SMP(orr r4, r4, #TTB_FLAGS_SMP) 370 ALT_UP(orr r4, r4, #TTB_FLAGS_UP) 371 mcr p15, 0, r4, c2, c0, 1 @ load TTB1 372 ldr r5, =PRRR @ PRRR 373 ldr r6, =NMRR @ NMRR 374 mcr p15, 0, r5, c10, c2, 0 @ write PRRR 375 mcr p15, 0, r6, c10, c2, 1 @ write NMRR 376#endif 377 adr r5, v7_crval 378 ldmia r5, {r5, r6} 379#ifdef CONFIG_CPU_ENDIAN_BE8 380 orr r6, r6, #1 << 25 @ big-endian page tables 381#endif 382#ifdef CONFIG_SWP_EMULATE 383 orr r5, r5, #(1 << 10) @ set SW bit in "clear" 384 bic r6, r6, #(1 << 10) @ clear it in "mmuset" 385#endif 386 mrc p15, 0, r0, c1, c0, 0 @ read control register 387 bic r0, r0, r5 @ clear bits them 388 orr r0, r0, r6 @ set them 389 THUMB( orr r0, r0, #1 << 30 ) @ Thumb exceptions 390 mov pc, lr @ return to head.S:__ret 391ENDPROC(__v7_setup) 392 393 /* AT 394 * TFR EV X F I D LR S 395 * .EEE ..EE PUI. .T.T 4RVI ZWRS BLDP WCAM 396 * rxxx rrxx xxx0 0101 xxxx xxxx x111 xxxx < forced 397 * 1 0 110 0011 1100 .111 1101 < we want 398 */ 399 .type v7_crval, #object 400v7_crval: 401 crval clear=0x0120c302, mmuset=0x10c03c7d, ucset=0x00c01c7c 402 403__v7_setup_stack: 404 .space 4 * 11 @ 11 registers 405 406 __INITDATA 407 408 .type v7_processor_functions, #object 409ENTRY(v7_processor_functions) 410 .word v7_early_abort 411 .word v7_pabort 412 .word cpu_v7_proc_init 413 .word cpu_v7_proc_fin 414 .word cpu_v7_reset 415 .word cpu_v7_do_idle 416 .word cpu_v7_dcache_clean_area 417 .word cpu_v7_switch_mm 418 .word cpu_v7_set_pte_ext 419 .word 0 420 .word 0 421 .word 0 422 .size v7_processor_functions, . - v7_processor_functions 423 424 .section ".rodata" 425 426 .type cpu_arch_name, #object 427cpu_arch_name: 428 .asciz "armv7" 429 .size cpu_arch_name, . - cpu_arch_name 430 431 .type cpu_elf_name, #object 432cpu_elf_name: 433 .asciz "v7" 434 .size cpu_elf_name, . - cpu_elf_name 435 .align 436 437 .section ".proc.info.init", #alloc, #execinstr 438 439 .type __v7_ca9mp_proc_info, #object 440__v7_ca9mp_proc_info: 441 .long 0x410fc090 @ Required ID value 442 .long 0xff0ffff0 @ Mask for ID 443 ALT_SMP(.long \ 444 PMD_TYPE_SECT | \ 445 PMD_SECT_AP_WRITE | \ 446 PMD_SECT_AP_READ | \ 447 PMD_FLAGS_SMP) 448 ALT_UP(.long \ 449 PMD_TYPE_SECT | \ 450 PMD_SECT_AP_WRITE | \ 451 PMD_SECT_AP_READ | \ 452 PMD_FLAGS_UP) 453 .long PMD_TYPE_SECT | \ 454 PMD_SECT_XN | \ 455 PMD_SECT_AP_WRITE | \ 456 PMD_SECT_AP_READ 457 W(b) __v7_ca9mp_setup 458 .long cpu_arch_name 459 .long cpu_elf_name 460 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_TLS 461 .long cpu_v7_name 462 .long v7_processor_functions 463 .long v7wbi_tlb_fns 464 .long v6_user_fns 465 .long v7_cache_fns 466 .size __v7_ca9mp_proc_info, . - __v7_ca9mp_proc_info 467 468 /* 469 * Match any ARMv7 processor core. 470 */ 471 .type __v7_proc_info, #object 472__v7_proc_info: 473 .long 0x000f0000 @ Required ID value 474 .long 0x000f0000 @ Mask for ID 475 ALT_SMP(.long \ 476 PMD_TYPE_SECT | \ 477 PMD_SECT_AP_WRITE | \ 478 PMD_SECT_AP_READ | \ 479 PMD_FLAGS_SMP) 480 ALT_UP(.long \ 481 PMD_TYPE_SECT | \ 482 PMD_SECT_AP_WRITE | \ 483 PMD_SECT_AP_READ | \ 484 PMD_FLAGS_UP) 485 .long PMD_TYPE_SECT | \ 486 PMD_SECT_XN | \ 487 PMD_SECT_AP_WRITE | \ 488 PMD_SECT_AP_READ 489 W(b) __v7_setup 490 .long cpu_arch_name 491 .long cpu_elf_name 492 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_TLS 493 .long cpu_v7_name 494 .long v7_processor_functions 495 .long v7wbi_tlb_fns 496 .long v6_user_fns 497 .long v7_cache_fns 498 .size __v7_proc_info, . - __v7_proc_info 499