proc-v7.S (0d41da2e31e81f5c8aaabe17f769de4304b2d4c8) proc-v7.S (15e0d9e37c7fe9711b60f47221c394d45553ad8c)
1/*
2 * linux/arch/arm/mm/proc-v7.S
3 *
4 * Copyright (C) 2001 Deep Blue Solutions Ltd.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.

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61 *
62 * This code must be executed using a flat identity mapping with
63 * caches disabled.
64 */
65 .align 5
66ENTRY(cpu_v7_reset)
67 mrc p15, 0, r1, c1, c0, 0 @ ctrl register
68 bic r1, r1, #0x1 @ ...............m
1/*
2 * linux/arch/arm/mm/proc-v7.S
3 *
4 * Copyright (C) 2001 Deep Blue Solutions Ltd.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.

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61 *
62 * This code must be executed using a flat identity mapping with
63 * caches disabled.
64 */
65 .align 5
66ENTRY(cpu_v7_reset)
67 mrc p15, 0, r1, c1, c0, 0 @ ctrl register
68 bic r1, r1, #0x1 @ ...............m
69 THUMB( bic r1, r1, #1 << 30 ) @ SCTLR.TE (Thumb exceptions)
70 mcr p15, 0, r1, c1, c0, 0 @ disable MMU
71 isb
72 mov pc, r0
73ENDPROC(cpu_v7_reset)
74
75/*
76 * cpu_v7_do_idle()
77 *

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213 * NOS = PRRR[24+n] = 1 - not outer shareable
214 */
215.equ PRRR, 0xff0a81a8
216.equ NMRR, 0x40e040e0
217
218/* Suspend/resume support: derived from arch/arm/mach-s5pv210/sleep.S */
219.globl cpu_v7_suspend_size
220.equ cpu_v7_suspend_size, 4 * 9
69 mcr p15, 0, r1, c1, c0, 0 @ disable MMU
70 isb
71 mov pc, r0
72ENDPROC(cpu_v7_reset)
73
74/*
75 * cpu_v7_do_idle()
76 *

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212 * NOS = PRRR[24+n] = 1 - not outer shareable
213 */
214.equ PRRR, 0xff0a81a8
215.equ NMRR, 0x40e040e0
216
217/* Suspend/resume support: derived from arch/arm/mach-s5pv210/sleep.S */
218.globl cpu_v7_suspend_size
219.equ cpu_v7_suspend_size, 4 * 9
221#ifdef CONFIG_PM_SLEEP
220#ifdef CONFIG_ARM_CPU_SUSPEND
222ENTRY(cpu_v7_do_suspend)
223 stmfd sp!, {r4 - r11, lr}
224 mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID
225 mrc p15, 0, r5, c13, c0, 1 @ Context ID
226 mrc p15, 0, r6, c13, c0, 3 @ User r/o thread ID
227 stmia r0!, {r4 - r6}
228 mrc p15, 0, r6, c3, c0, 0 @ Domain ID
229 mrc p15, 0, r7, c2, c0, 0 @ TTB 0

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243 mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID
244 mcr p15, 0, r5, c13, c0, 1 @ Context ID
245 mcr p15, 0, r6, c13, c0, 3 @ User r/o thread ID
246 ldmia r0, {r6 - r11}
247 mcr p15, 0, r6, c3, c0, 0 @ Domain ID
248 mcr p15, 0, r7, c2, c0, 0 @ TTB 0
249 mcr p15, 0, r8, c2, c0, 1 @ TTB 1
250 mcr p15, 0, ip, c2, c0, 2 @ TTB control register
221ENTRY(cpu_v7_do_suspend)
222 stmfd sp!, {r4 - r11, lr}
223 mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID
224 mrc p15, 0, r5, c13, c0, 1 @ Context ID
225 mrc p15, 0, r6, c13, c0, 3 @ User r/o thread ID
226 stmia r0!, {r4 - r6}
227 mrc p15, 0, r6, c3, c0, 0 @ Domain ID
228 mrc p15, 0, r7, c2, c0, 0 @ TTB 0

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242 mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID
243 mcr p15, 0, r5, c13, c0, 1 @ Context ID
244 mcr p15, 0, r6, c13, c0, 3 @ User r/o thread ID
245 ldmia r0, {r6 - r11}
246 mcr p15, 0, r6, c3, c0, 0 @ Domain ID
247 mcr p15, 0, r7, c2, c0, 0 @ TTB 0
248 mcr p15, 0, r8, c2, c0, 1 @ TTB 1
249 mcr p15, 0, ip, c2, c0, 2 @ TTB control register
251 mrc p15, 0, r4, c1, c0, 1 @ Read Auxiliary control register
252 teq r4, r10 @ Is it already set?
253 mcrne p15, 0, r10, c1, c0, 1 @ No, so write it
250 mcr p15, 0, r10, c1, c0, 1 @ Auxiliary control register
254 mcr p15, 0, r11, c1, c0, 2 @ Co-processor access control
255 ldr r4, =PRRR @ PRRR
256 ldr r5, =NMRR @ NMRR
257 mcr p15, 0, r4, c10, c2, 0 @ write PRRR
258 mcr p15, 0, r5, c10, c2, 1 @ write NMRR
259 isb
251 mcr p15, 0, r11, c1, c0, 2 @ Co-processor access control
252 ldr r4, =PRRR @ PRRR
253 ldr r5, =NMRR @ NMRR
254 mcr p15, 0, r4, c10, c2, 0 @ write PRRR
255 mcr p15, 0, r5, c10, c2, 1 @ write NMRR
256 isb
260 dsb
261 mov r0, r9 @ control register
262 mov r2, r7, lsr #14 @ get TTB0 base
263 mov r2, r2, lsl #14
264 ldr r3, cpu_resume_l1_flags
265 b cpu_resume_mmu
266ENDPROC(cpu_v7_do_resume)
267cpu_resume_l1_flags:
268 ALT_SMP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_FLAGS_SMP)

--- 231 unchanged lines hidden --- 		257 mov r0, r9 @ control register
258 mov r2, r7, lsr #14 @ get TTB0 base
259 mov r2, r2, lsl #14
260 ldr r3, cpu_resume_l1_flags
261 b cpu_resume_mmu
262ENDPROC(cpu_v7_do_resume)
263cpu_resume_l1_flags:
264 ALT_SMP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_FLAGS_SMP)

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