1/* 2 * linux/arch/arm/mm/proc-v7.S 3 * 4 * Copyright (C) 2001 Deep Blue Solutions Ltd. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 * This is the "shell" of the ARMv7 processor support. 11 */ 12#include <linux/init.h> 13#include <linux/linkage.h> 14#include <asm/assembler.h> 15#include <asm/asm-offsets.h> 16#include <asm/hwcap.h> 17#include <asm/pgtable-hwdef.h> 18#include <asm/pgtable.h> 19 20#include "proc-macros.S" 21 22#define TTB_S (1 << 1) 23#define TTB_RGN_NC (0 << 3) 24#define TTB_RGN_OC_WBWA (1 << 3) 25#define TTB_RGN_OC_WT (2 << 3) 26#define TTB_RGN_OC_WB (3 << 3) 27#define TTB_NOS (1 << 5) 28#define TTB_IRGN_NC ((0 << 0) | (0 << 6)) 29#define TTB_IRGN_WBWA ((0 << 0) | (1 << 6)) 30#define TTB_IRGN_WT ((1 << 0) | (0 << 6)) 31#define TTB_IRGN_WB ((1 << 0) | (1 << 6)) 32 33/* PTWs cacheable, inner WB not shareable, outer WB not shareable */ 34#define TTB_FLAGS_UP TTB_IRGN_WB|TTB_RGN_OC_WB 35#define PMD_FLAGS_UP PMD_SECT_WB 36 37/* PTWs cacheable, inner WBWA shareable, outer WBWA not shareable */ 38#define TTB_FLAGS_SMP TTB_IRGN_WBWA|TTB_S|TTB_NOS|TTB_RGN_OC_WBWA 39#define PMD_FLAGS_SMP PMD_SECT_WBWA|PMD_SECT_S 40 41ENTRY(cpu_v7_proc_init) 42 mov pc, lr 43ENDPROC(cpu_v7_proc_init) 44 45ENTRY(cpu_v7_proc_fin) 46 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 47 bic r0, r0, #0x1000 @ ...i............ 48 bic r0, r0, #0x0006 @ .............ca. 49 mcr p15, 0, r0, c1, c0, 0 @ disable caches 50 mov pc, lr 51ENDPROC(cpu_v7_proc_fin) 52 53/* 54 * cpu_v7_reset(loc) 55 * 56 * Perform a soft reset of the system. Put the CPU into the 57 * same state as it would be if it had been reset, and branch 58 * to what would be the reset vector. 59 * 60 * - loc - location to jump to for soft reset 61 * 62 * This code must be executed using a flat identity mapping with 63 * caches disabled. 64 */ 65 .align 5 66ENTRY(cpu_v7_reset) 67 mrc p15, 0, r1, c1, c0, 0 @ ctrl register 68 bic r1, r1, #0x1 @ ...............m 69 mcr p15, 0, r1, c1, c0, 0 @ disable MMU 70 isb 71 mov pc, r0 72ENDPROC(cpu_v7_reset) 73 74/* 75 * cpu_v7_do_idle() 76 * 77 * Idle the processor (eg, wait for interrupt). 78 * 79 * IRQs are already disabled. 80 */ 81ENTRY(cpu_v7_do_idle) 82 dsb @ WFI may enter a low-power mode 83 wfi 84 mov pc, lr 85ENDPROC(cpu_v7_do_idle) 86 87ENTRY(cpu_v7_dcache_clean_area) 88#ifndef TLB_CAN_READ_FROM_L1_CACHE 89 dcache_line_size r2, r3 901: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 91 add r0, r0, r2 92 subs r1, r1, r2 93 bhi 1b 94 dsb 95#endif 96 mov pc, lr 97ENDPROC(cpu_v7_dcache_clean_area) 98 99/* 100 * cpu_v7_switch_mm(pgd_phys, tsk) 101 * 102 * Set the translation table base pointer to be pgd_phys 103 * 104 * - pgd_phys - physical address of new TTB 105 * 106 * It is assumed that: 107 * - we are not using split page tables 108 */ 109ENTRY(cpu_v7_switch_mm) 110#ifdef CONFIG_MMU 111 mov r2, #0 112 ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id 113 ALT_SMP(orr r0, r0, #TTB_FLAGS_SMP) 114 ALT_UP(orr r0, r0, #TTB_FLAGS_UP) 115#ifdef CONFIG_ARM_ERRATA_430973 116 mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB 117#endif 118#ifdef CONFIG_ARM_ERRATA_754322 119 dsb 120#endif 121 mcr p15, 0, r2, c13, c0, 1 @ set reserved context ID 122 isb 1231: mcr p15, 0, r0, c2, c0, 0 @ set TTB 0 124 isb 125#ifdef CONFIG_ARM_ERRATA_754322 126 dsb 127#endif 128 mcr p15, 0, r1, c13, c0, 1 @ set context ID 129 isb 130#endif 131 mov pc, lr 132ENDPROC(cpu_v7_switch_mm) 133 134/* 135 * cpu_v7_set_pte_ext(ptep, pte) 136 * 137 * Set a level 2 translation table entry. 138 * 139 * - ptep - pointer to level 2 translation table entry 140 * (hardware version is stored at +2048 bytes) 141 * - pte - PTE value to store 142 * - ext - value for extended PTE bits 143 */ 144ENTRY(cpu_v7_set_pte_ext) 145#ifdef CONFIG_MMU 146 str r1, [r0] @ linux version 147 148 bic r3, r1, #0x000003f0 149 bic r3, r3, #PTE_TYPE_MASK 150 orr r3, r3, r2 151 orr r3, r3, #PTE_EXT_AP0 | 2 152 153 tst r1, #1 << 4 154 orrne r3, r3, #PTE_EXT_TEX(1) 155 156 eor r1, r1, #L_PTE_DIRTY 157 tst r1, #L_PTE_RDONLY | L_PTE_DIRTY 158 orrne r3, r3, #PTE_EXT_APX 159 160 tst r1, #L_PTE_USER 161 orrne r3, r3, #PTE_EXT_AP1 162#ifdef CONFIG_CPU_USE_DOMAINS 163 @ allow kernel read/write access to read-only user pages 164 tstne r3, #PTE_EXT_APX 165 bicne r3, r3, #PTE_EXT_APX | PTE_EXT_AP0 166#endif 167 168 tst r1, #L_PTE_XN 169 orrne r3, r3, #PTE_EXT_XN 170 171 tst r1, #L_PTE_YOUNG 172 tstne r1, #L_PTE_PRESENT 173 moveq r3, #0 174 175 ARM( str r3, [r0, #2048]! ) 176 THUMB( add r0, r0, #2048 ) 177 THUMB( str r3, [r0] ) 178 mcr p15, 0, r0, c7, c10, 1 @ flush_pte 179#endif 180 mov pc, lr 181ENDPROC(cpu_v7_set_pte_ext) 182 183 string cpu_v7_name, "ARMv7 Processor" 184 .align 185 186 /* 187 * Memory region attributes with SCTLR.TRE=1 188 * 189 * n = TEX[0],C,B 190 * TR = PRRR[2n+1:2n] - memory type 191 * IR = NMRR[2n+1:2n] - inner cacheable property 192 * OR = NMRR[2n+17:2n+16] - outer cacheable property 193 * 194 * n TR IR OR 195 * UNCACHED 000 00 196 * BUFFERABLE 001 10 00 00 197 * WRITETHROUGH 010 10 10 10 198 * WRITEBACK 011 10 11 11 199 * reserved 110 200 * WRITEALLOC 111 10 01 01 201 * DEV_SHARED 100 01 202 * DEV_NONSHARED 100 01 203 * DEV_WC 001 10 204 * DEV_CACHED 011 10 205 * 206 * Other attributes: 207 * 208 * DS0 = PRRR[16] = 0 - device shareable property 209 * DS1 = PRRR[17] = 1 - device shareable property 210 * NS0 = PRRR[18] = 0 - normal shareable property 211 * NS1 = PRRR[19] = 1 - normal shareable property 212 * NOS = PRRR[24+n] = 1 - not outer shareable 213 */ 214.equ PRRR, 0xff0a81a8 215.equ NMRR, 0x40e040e0 216 217/* Suspend/resume support: derived from arch/arm/mach-s5pv210/sleep.S */ 218.globl cpu_v7_suspend_size 219.equ cpu_v7_suspend_size, 4 * 9 220#ifdef CONFIG_ARM_CPU_SUSPEND 221ENTRY(cpu_v7_do_suspend) 222 stmfd sp!, {r4 - r11, lr} 223 mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID 224 mrc p15, 0, r5, c13, c0, 1 @ Context ID 225 mrc p15, 0, r6, c13, c0, 3 @ User r/o thread ID 226 stmia r0!, {r4 - r6} 227 mrc p15, 0, r6, c3, c0, 0 @ Domain ID 228 mrc p15, 0, r7, c2, c0, 0 @ TTB 0 229 mrc p15, 0, r8, c2, c0, 1 @ TTB 1 230 mrc p15, 0, r9, c1, c0, 0 @ Control register 231 mrc p15, 0, r10, c1, c0, 1 @ Auxiliary control register 232 mrc p15, 0, r11, c1, c0, 2 @ Co-processor access control 233 stmia r0, {r6 - r11} 234 ldmfd sp!, {r4 - r11, pc} 235ENDPROC(cpu_v7_do_suspend) 236 237ENTRY(cpu_v7_do_resume) 238 mov ip, #0 239 mcr p15, 0, ip, c8, c7, 0 @ invalidate TLBs 240 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache 241 ldmia r0!, {r4 - r6} 242 mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID 243 mcr p15, 0, r5, c13, c0, 1 @ Context ID 244 mcr p15, 0, r6, c13, c0, 3 @ User r/o thread ID 245 ldmia r0, {r6 - r11} 246 mcr p15, 0, r6, c3, c0, 0 @ Domain ID 247 mcr p15, 0, r7, c2, c0, 0 @ TTB 0 248 mcr p15, 0, r8, c2, c0, 1 @ TTB 1 249 mcr p15, 0, ip, c2, c0, 2 @ TTB control register 250 mcr p15, 0, r10, c1, c0, 1 @ Auxiliary control register 251 mcr p15, 0, r11, c1, c0, 2 @ Co-processor access control 252 ldr r4, =PRRR @ PRRR 253 ldr r5, =NMRR @ NMRR 254 mcr p15, 0, r4, c10, c2, 0 @ write PRRR 255 mcr p15, 0, r5, c10, c2, 1 @ write NMRR 256 isb 257 mov r0, r9 @ control register 258 mov r2, r7, lsr #14 @ get TTB0 base 259 mov r2, r2, lsl #14 260 ldr r3, cpu_resume_l1_flags 261 b cpu_resume_mmu 262ENDPROC(cpu_v7_do_resume) 263cpu_resume_l1_flags: 264 ALT_SMP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_FLAGS_SMP) 265 ALT_UP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_FLAGS_UP) 266#endif 267 268 __CPUINIT 269 270/* 271 * __v7_setup 272 * 273 * Initialise TLB, Caches, and MMU state ready to switch the MMU 274 * on. Return in r0 the new CP15 C1 control register setting. 275 * 276 * We automatically detect if we have a Harvard cache, and use the 277 * Harvard cache control instructions insead of the unified cache 278 * control instructions. 279 * 280 * This should be able to cover all ARMv7 cores. 281 * 282 * It is assumed that: 283 * - cache type register is implemented 284 */ 285__v7_ca5mp_setup: 286__v7_ca9mp_setup: 287 mov r10, #(1 << 0) @ TLB ops broadcasting 288 b 1f 289__v7_ca15mp_setup: 290 mov r10, #0 2911: 292#ifdef CONFIG_SMP 293 ALT_SMP(mrc p15, 0, r0, c1, c0, 1) 294 ALT_UP(mov r0, #(1 << 6)) @ fake it for UP 295 tst r0, #(1 << 6) @ SMP/nAMP mode enabled? 296 orreq r0, r0, #(1 << 6) @ Enable SMP/nAMP mode 297 orreq r0, r0, r10 @ Enable CPU-specific SMP bits 298 mcreq p15, 0, r0, c1, c0, 1 299#endif 300__v7_setup: 301 adr r12, __v7_setup_stack @ the local stack 302 stmia r12, {r0-r5, r7, r9, r11, lr} 303 bl v7_flush_dcache_all 304 ldmia r12, {r0-r5, r7, r9, r11, lr} 305 306 mrc p15, 0, r0, c0, c0, 0 @ read main ID register 307 and r10, r0, #0xff000000 @ ARM? 308 teq r10, #0x41000000 309 bne 3f 310 and r5, r0, #0x00f00000 @ variant 311 and r6, r0, #0x0000000f @ revision 312 orr r6, r6, r5, lsr #20-4 @ combine variant and revision 313 ubfx r0, r0, #4, #12 @ primary part number 314 315 /* Cortex-A8 Errata */ 316 ldr r10, =0x00000c08 @ Cortex-A8 primary part number 317 teq r0, r10 318 bne 2f 319#ifdef CONFIG_ARM_ERRATA_430973 320 teq r5, #0x00100000 @ only present in r1p* 321 mrceq p15, 0, r10, c1, c0, 1 @ read aux control register 322 orreq r10, r10, #(1 << 6) @ set IBE to 1 323 mcreq p15, 0, r10, c1, c0, 1 @ write aux control register 324#endif 325#ifdef CONFIG_ARM_ERRATA_458693 326 teq r6, #0x20 @ only present in r2p0 327 mrceq p15, 0, r10, c1, c0, 1 @ read aux control register 328 orreq r10, r10, #(1 << 5) @ set L1NEON to 1 329 orreq r10, r10, #(1 << 9) @ set PLDNOP to 1 330 mcreq p15, 0, r10, c1, c0, 1 @ write aux control register 331#endif 332#ifdef CONFIG_ARM_ERRATA_460075 333 teq r6, #0x20 @ only present in r2p0 334 mrceq p15, 1, r10, c9, c0, 2 @ read L2 cache aux ctrl register 335 tsteq r10, #1 << 22 336 orreq r10, r10, #(1 << 22) @ set the Write Allocate disable bit 337 mcreq p15, 1, r10, c9, c0, 2 @ write the L2 cache aux ctrl register 338#endif 339 b 3f 340 341 /* Cortex-A9 Errata */ 3422: ldr r10, =0x00000c09 @ Cortex-A9 primary part number 343 teq r0, r10 344 bne 3f 345#ifdef CONFIG_ARM_ERRATA_742230 346 cmp r6, #0x22 @ only present up to r2p2 347 mrcle p15, 0, r10, c15, c0, 1 @ read diagnostic register 348 orrle r10, r10, #1 << 4 @ set bit #4 349 mcrle p15, 0, r10, c15, c0, 1 @ write diagnostic register 350#endif 351#ifdef CONFIG_ARM_ERRATA_742231 352 teq r6, #0x20 @ present in r2p0 353 teqne r6, #0x21 @ present in r2p1 354 teqne r6, #0x22 @ present in r2p2 355 mrceq p15, 0, r10, c15, c0, 1 @ read diagnostic register 356 orreq r10, r10, #1 << 12 @ set bit #12 357 orreq r10, r10, #1 << 22 @ set bit #22 358 mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register 359#endif 360#ifdef CONFIG_ARM_ERRATA_743622 361 teq r6, #0x20 @ present in r2p0 362 teqne r6, #0x21 @ present in r2p1 363 teqne r6, #0x22 @ present in r2p2 364 mrceq p15, 0, r10, c15, c0, 1 @ read diagnostic register 365 orreq r10, r10, #1 << 6 @ set bit #6 366 mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register 367#endif 368#ifdef CONFIG_ARM_ERRATA_751472 369 cmp r6, #0x30 @ present prior to r3p0 370 mrclt p15, 0, r10, c15, c0, 1 @ read diagnostic register 371 orrlt r10, r10, #1 << 11 @ set bit #11 372 mcrlt p15, 0, r10, c15, c0, 1 @ write diagnostic register 373#endif 374 3753: mov r10, #0 376#ifdef HARVARD_CACHE 377 mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate 378#endif 379 dsb 380#ifdef CONFIG_MMU 381 mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs 382 mcr p15, 0, r10, c2, c0, 2 @ TTB control register 383 ALT_SMP(orr r4, r4, #TTB_FLAGS_SMP) 384 ALT_UP(orr r4, r4, #TTB_FLAGS_UP) 385 ALT_SMP(orr r8, r8, #TTB_FLAGS_SMP) 386 ALT_UP(orr r8, r8, #TTB_FLAGS_UP) 387 mcr p15, 0, r8, c2, c0, 1 @ load TTB1 388 ldr r5, =PRRR @ PRRR 389 ldr r6, =NMRR @ NMRR 390 mcr p15, 0, r5, c10, c2, 0 @ write PRRR 391 mcr p15, 0, r6, c10, c2, 1 @ write NMRR 392#endif 393 adr r5, v7_crval 394 ldmia r5, {r5, r6} 395#ifdef CONFIG_CPU_ENDIAN_BE8 396 orr r6, r6, #1 << 25 @ big-endian page tables 397#endif 398#ifdef CONFIG_SWP_EMULATE 399 orr r5, r5, #(1 << 10) @ set SW bit in "clear" 400 bic r6, r6, #(1 << 10) @ clear it in "mmuset" 401#endif 402 mrc p15, 0, r0, c1, c0, 0 @ read control register 403 bic r0, r0, r5 @ clear bits them 404 orr r0, r0, r6 @ set them 405 THUMB( orr r0, r0, #1 << 30 ) @ Thumb exceptions 406 mov pc, lr @ return to head.S:__ret 407ENDPROC(__v7_setup) 408 409 /* AT 410 * TFR EV X F I D LR S 411 * .EEE ..EE PUI. .T.T 4RVI ZWRS BLDP WCAM 412 * rxxx rrxx xxx0 0101 xxxx xxxx x111 xxxx < forced 413 * 1 0 110 0011 1100 .111 1101 < we want 414 */ 415 .type v7_crval, #object 416v7_crval: 417 crval clear=0x0120c302, mmuset=0x10c03c7d, ucset=0x00c01c7c 418 419__v7_setup_stack: 420 .space 4 * 11 @ 11 registers 421 422 __INITDATA 423 424 @ define struct processor (see <asm/proc-fns.h> and proc-macros.S) 425 define_processor_functions v7, dabort=v7_early_abort, pabort=v7_pabort, suspend=1 426 427 .section ".rodata" 428 429 string cpu_arch_name, "armv7" 430 string cpu_elf_name, "v7" 431 .align 432 433 .section ".proc.info.init", #alloc, #execinstr 434 435 /* 436 * Standard v7 proc info content 437 */ 438.macro __v7_proc initfunc, mm_mmuflags = 0, io_mmuflags = 0, hwcaps = 0 439 ALT_SMP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \ 440 PMD_FLAGS_SMP | \mm_mmuflags) 441 ALT_UP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \ 442 PMD_FLAGS_UP | \mm_mmuflags) 443 .long PMD_TYPE_SECT | PMD_SECT_XN | PMD_SECT_AP_WRITE | \ 444 PMD_SECT_AP_READ | \io_mmuflags 445 W(b) \initfunc 446 .long cpu_arch_name 447 .long cpu_elf_name 448 .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB | HWCAP_FAST_MULT | \ 449 HWCAP_EDSP | HWCAP_TLS | \hwcaps 450 .long cpu_v7_name 451 .long v7_processor_functions 452 .long v7wbi_tlb_fns 453 .long v6_user_fns 454 .long v7_cache_fns 455.endm 456 457 /* 458 * ARM Ltd. Cortex A5 processor. 459 */ 460 .type __v7_ca5mp_proc_info, #object 461__v7_ca5mp_proc_info: 462 .long 0x410fc050 463 .long 0xff0ffff0 464 __v7_proc __v7_ca5mp_setup 465 .size __v7_ca5mp_proc_info, . - __v7_ca5mp_proc_info 466 467 /* 468 * ARM Ltd. Cortex A9 processor. 469 */ 470 .type __v7_ca9mp_proc_info, #object 471__v7_ca9mp_proc_info: 472 .long 0x410fc090 473 .long 0xff0ffff0 474 __v7_proc __v7_ca9mp_setup 475 .size __v7_ca9mp_proc_info, . - __v7_ca9mp_proc_info 476 477 /* 478 * ARM Ltd. Cortex A15 processor. 479 */ 480 .type __v7_ca15mp_proc_info, #object 481__v7_ca15mp_proc_info: 482 .long 0x410fc0f0 483 .long 0xff0ffff0 484 __v7_proc __v7_ca15mp_setup, hwcaps = HWCAP_IDIV 485 .size __v7_ca15mp_proc_info, . - __v7_ca15mp_proc_info 486 487 /* 488 * Match any ARMv7 processor core. 489 */ 490 .type __v7_proc_info, #object 491__v7_proc_info: 492 .long 0x000f0000 @ Required ID value 493 .long 0x000f0000 @ Mask for ID 494 __v7_proc __v7_setup 495 .size __v7_proc_info, . - __v7_proc_info 496