| Kconfig (12e04ffcd93b25dfd726d46338c2ee7d23de556e) | Kconfig (4477ca45fb368880bf77b10ed3b24b03f0cc82da) |
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| 1comment "Processor Type" 2 3# Select CPU types depending on the architecture selected. This selects 4# which CPUs we support in the kernel image, and the compiler instruction 5# optimiser behaviour. 6 7# ARM7TDMI 8config CPU_ARM7TDMI --- 29 unchanged lines hidden (view full) --- 38 Otherwise, say N. 39 40# ARM740T 41config CPU_ARM740T 42 bool "Support ARM740T processor" if ARCH_INTEGRATOR 43 depends on !MMU 44 select CPU_32v4T 45 select CPU_ABRT_LV4T | 1comment "Processor Type" 2 3# Select CPU types depending on the architecture selected. This selects 4# which CPUs we support in the kernel image, and the compiler instruction 5# optimiser behaviour. 6 7# ARM7TDMI 8config CPU_ARM7TDMI --- 29 unchanged lines hidden (view full) --- 38 Otherwise, say N. 39 40# ARM740T 41config CPU_ARM740T 42 bool "Support ARM740T processor" if ARCH_INTEGRATOR 43 depends on !MMU 44 select CPU_32v4T 45 select CPU_ABRT_LV4T |
| 46 select CPU_CACHE_V4 | 46 select CPU_CACHE_V3 # although the core is v4t |
| 47 select CPU_CP15_MPU 48 select CPU_PABRT_LEGACY 49 help 50 A 32-bit RISC processor with 8KB cache or 4KB variants, 51 write buffer and MPU(Protection Unit) built around 52 an ARM7TDMI core. 53 54 Say Y if you want support for the ARM740T processor. --- 337 unchanged lines hidden (view full) --- 392 select CPU_CACHE_V7 393 select CPU_CACHE_VIPT 394 select CPU_COPY_V6 if MMU 395 select CPU_CP15_MMU 396 select CPU_HAS_ASID if MMU 397 select CPU_PABRT_V7 398 select CPU_TLB_V7 if MMU 399 | 47 select CPU_CP15_MPU 48 select CPU_PABRT_LEGACY 49 help 50 A 32-bit RISC processor with 8KB cache or 4KB variants, 51 write buffer and MPU(Protection Unit) built around 52 an ARM7TDMI core. 53 54 Say Y if you want support for the ARM740T processor. --- 337 unchanged lines hidden (view full) --- 392 select CPU_CACHE_V7 393 select CPU_CACHE_VIPT 394 select CPU_COPY_V6 if MMU 395 select CPU_CP15_MMU 396 select CPU_HAS_ASID if MMU 397 select CPU_PABRT_V7 398 select CPU_TLB_V7 if MMU 399 |
| 400# ARMv7M 401config CPU_V7M 402 bool 403 select CPU_32v7M 404 select CPU_ABRT_NOMMU 405 select CPU_CACHE_NOP 406 select CPU_PABRT_LEGACY 407 select CPU_THUMBONLY 408 |
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| 400config CPU_THUMBONLY 401 bool 402 # There are no CPUs available with MMU that don't implement an ARM ISA: 403 depends on !MMU 404 help 405 Select this if your CPU doesn't support the 32 bit ARM instructions. 406 407# Figure out what processor architecture version we should be using. --- 28 unchanged lines hidden (view full) --- 436 select TLS_REG_EMUL if !CPU_32v6K && !MMU 437 438config CPU_32v6K 439 bool 440 441config CPU_32v7 442 bool 443 | 409config CPU_THUMBONLY 410 bool 411 # There are no CPUs available with MMU that don't implement an ARM ISA: 412 depends on !MMU 413 help 414 Select this if your CPU doesn't support the 32 bit ARM instructions. 415 416# Figure out what processor architecture version we should be using. --- 28 unchanged lines hidden (view full) --- 445 select TLS_REG_EMUL if !CPU_32v6K && !MMU 446 447config CPU_32v6K 448 bool 449 450config CPU_32v7 451 bool 452 |
| 453config CPU_32v7M 454 bool 455 |
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| 444# The abort model 445config CPU_ABRT_NOMMU 446 bool 447 448config CPU_ABRT_EV4 449 bool 450 451config CPU_ABRT_EV4T --- 19 unchanged lines hidden (view full) --- 471 472config CPU_PABRT_V6 473 bool 474 475config CPU_PABRT_V7 476 bool 477 478# The cache model | 456# The abort model 457config CPU_ABRT_NOMMU 458 bool 459 460config CPU_ABRT_EV4 461 bool 462 463config CPU_ABRT_EV4T --- 19 unchanged lines hidden (view full) --- 483 484config CPU_PABRT_V6 485 bool 486 487config CPU_PABRT_V7 488 bool 489 490# The cache model |
| 491config CPU_CACHE_V3 492 bool 493 |
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| 479config CPU_CACHE_V4 480 bool 481 482config CPU_CACHE_V4WT 483 bool 484 485config CPU_CACHE_V4WB 486 bool 487 488config CPU_CACHE_V6 489 bool 490 491config CPU_CACHE_V7 492 bool 493 | 494config CPU_CACHE_V4 495 bool 496 497config CPU_CACHE_V4WT 498 bool 499 500config CPU_CACHE_V4WB 501 bool 502 503config CPU_CACHE_V6 504 bool 505 506config CPU_CACHE_V7 507 bool 508 |
| 509config CPU_CACHE_NOP 510 bool 511 |
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| 494config CPU_CACHE_VIVT 495 bool 496 497config CPU_CACHE_VIPT 498 bool 499 500config CPU_CACHE_FA 501 bool --- 106 unchanged lines hidden (view full) --- 608config ARCH_PHYS_ADDR_T_64BIT 609 def_bool ARM_LPAE 610 611config ARCH_DMA_ADDR_T_64BIT 612 bool 613 614config ARM_THUMB 615 bool "Support Thumb user binaries" if !CPU_THUMBONLY | 512config CPU_CACHE_VIVT 513 bool 514 515config CPU_CACHE_VIPT 516 bool 517 518config CPU_CACHE_FA 519 bool --- 106 unchanged lines hidden (view full) --- 626config ARCH_PHYS_ADDR_T_64BIT 627 def_bool ARM_LPAE 628 629config ARCH_DMA_ADDR_T_64BIT 630 bool 631 632config ARM_THUMB 633 bool "Support Thumb user binaries" if !CPU_THUMBONLY |
| 616 depends on CPU_ARM720T || CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_V6 || CPU_V6K || CPU_V7 || CPU_FEROCEON | 634 depends on CPU_ARM720T || CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || \ 635 CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || \ 636 CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \ 637 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_V6 || CPU_V6K || \ 638 CPU_V7 || CPU_FEROCEON || CPU_V7M |
| 617 default y 618 help 619 Say Y if you want to include kernel support for running user space 620 Thumb binaries. 621 622 The Thumb instruction set is a compressed form of the standard ARM 623 instruction set resulting in smaller binaries at the expense of 624 slightly less efficient code. --- 273 unchanged lines hidden --- | 639 default y 640 help 641 Say Y if you want to include kernel support for running user space 642 Thumb binaries. 643 644 The Thumb instruction set is a compressed form of the standard ARM 645 instruction set resulting in smaller binaries at the expense of 646 slightly less efficient code. --- 273 unchanged lines hidden --- |