1comment "Processor Type" 2 3# Select CPU types depending on the architecture selected. This selects 4# which CPUs we support in the kernel image, and the compiler instruction 5# optimiser behaviour. 6 7# ARM7TDMI 8config CPU_ARM7TDMI 9 bool "Support ARM7TDMI processor" 10 depends on !MMU 11 select CPU_32v4T 12 select CPU_ABRT_LV4T 13 select CPU_CACHE_V4 14 select CPU_PABRT_LEGACY 15 help 16 A 32-bit RISC microprocessor based on the ARM7 processor core 17 which has no memory control unit and cache. 18 19 Say Y if you want support for the ARM7TDMI processor. 20 Otherwise, say N. 21 22# ARM720T 23config CPU_ARM720T 24 bool "Support ARM720T processor" if ARCH_INTEGRATOR 25 select CPU_32v4T 26 select CPU_ABRT_LV4T 27 select CPU_CACHE_V4 28 select CPU_CACHE_VIVT 29 select CPU_COPY_V4WT if MMU 30 select CPU_CP15_MMU 31 select CPU_PABRT_LEGACY 32 select CPU_TLB_V4WT if MMU 33 help 34 A 32-bit RISC processor with 8kByte Cache, Write Buffer and 35 MMU built around an ARM7TDMI core. 36 37 Say Y if you want support for the ARM720T processor. 38 Otherwise, say N. 39 40# ARM740T 41config CPU_ARM740T 42 bool "Support ARM740T processor" if ARCH_INTEGRATOR 43 depends on !MMU 44 select CPU_32v4T 45 select CPU_ABRT_LV4T 46 select CPU_CACHE_V3 # although the core is v4t 47 select CPU_CP15_MPU 48 select CPU_PABRT_LEGACY 49 help 50 A 32-bit RISC processor with 8KB cache or 4KB variants, 51 write buffer and MPU(Protection Unit) built around 52 an ARM7TDMI core. 53 54 Say Y if you want support for the ARM740T processor. 55 Otherwise, say N. 56 57# ARM9TDMI 58config CPU_ARM9TDMI 59 bool "Support ARM9TDMI processor" 60 depends on !MMU 61 select CPU_32v4T 62 select CPU_ABRT_NOMMU 63 select CPU_CACHE_V4 64 select CPU_PABRT_LEGACY 65 help 66 A 32-bit RISC microprocessor based on the ARM9 processor core 67 which has no memory control unit and cache. 68 69 Say Y if you want support for the ARM9TDMI processor. 70 Otherwise, say N. 71 72# ARM920T 73config CPU_ARM920T 74 bool "Support ARM920T processor" if ARCH_INTEGRATOR 75 select CPU_32v4T 76 select CPU_ABRT_EV4T 77 select CPU_CACHE_V4WT 78 select CPU_CACHE_VIVT 79 select CPU_COPY_V4WB if MMU 80 select CPU_CP15_MMU 81 select CPU_PABRT_LEGACY 82 select CPU_TLB_V4WBI if MMU 83 help 84 The ARM920T is licensed to be produced by numerous vendors, 85 and is used in the Cirrus EP93xx and the Samsung S3C2410. 86 87 Say Y if you want support for the ARM920T processor. 88 Otherwise, say N. 89 90# ARM922T 91config CPU_ARM922T 92 bool "Support ARM922T processor" if ARCH_INTEGRATOR 93 select CPU_32v4T 94 select CPU_ABRT_EV4T 95 select CPU_CACHE_V4WT 96 select CPU_CACHE_VIVT 97 select CPU_COPY_V4WB if MMU 98 select CPU_CP15_MMU 99 select CPU_PABRT_LEGACY 100 select CPU_TLB_V4WBI if MMU 101 help 102 The ARM922T is a version of the ARM920T, but with smaller 103 instruction and data caches. It is used in Altera's 104 Excalibur XA device family and Micrel's KS8695 Centaur. 105 106 Say Y if you want support for the ARM922T processor. 107 Otherwise, say N. 108 109# ARM925T 110config CPU_ARM925T 111 bool "Support ARM925T processor" if ARCH_OMAP1 112 select CPU_32v4T 113 select CPU_ABRT_EV4T 114 select CPU_CACHE_V4WT 115 select CPU_CACHE_VIVT 116 select CPU_COPY_V4WB if MMU 117 select CPU_CP15_MMU 118 select CPU_PABRT_LEGACY 119 select CPU_TLB_V4WBI if MMU 120 help 121 The ARM925T is a mix between the ARM920T and ARM926T, but with 122 different instruction and data caches. It is used in TI's OMAP 123 device family. 124 125 Say Y if you want support for the ARM925T processor. 126 Otherwise, say N. 127 128# ARM926T 129config CPU_ARM926T 130 bool "Support ARM926T processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB 131 select CPU_32v5 132 select CPU_ABRT_EV5TJ 133 select CPU_CACHE_VIVT 134 select CPU_COPY_V4WB if MMU 135 select CPU_CP15_MMU 136 select CPU_PABRT_LEGACY 137 select CPU_TLB_V4WBI if MMU 138 help 139 This is a variant of the ARM920. It has slightly different 140 instruction sequences for cache and TLB operations. Curiously, 141 there is no documentation on it at the ARM corporate website. 142 143 Say Y if you want support for the ARM926T processor. 144 Otherwise, say N. 145 146# FA526 147config CPU_FA526 148 bool 149 select CPU_32v4 150 select CPU_ABRT_EV4 151 select CPU_CACHE_FA 152 select CPU_CACHE_VIVT 153 select CPU_COPY_FA if MMU 154 select CPU_CP15_MMU 155 select CPU_PABRT_LEGACY 156 select CPU_TLB_FA if MMU 157 help 158 The FA526 is a version of the ARMv4 compatible processor with 159 Branch Target Buffer, Unified TLB and cache line size 16. 160 161 Say Y if you want support for the FA526 processor. 162 Otherwise, say N. 163 164# ARM940T 165config CPU_ARM940T 166 bool "Support ARM940T processor" if ARCH_INTEGRATOR 167 depends on !MMU 168 select CPU_32v4T 169 select CPU_ABRT_NOMMU 170 select CPU_CACHE_VIVT 171 select CPU_CP15_MPU 172 select CPU_PABRT_LEGACY 173 help 174 ARM940T is a member of the ARM9TDMI family of general- 175 purpose microprocessors with MPU and separate 4KB 176 instruction and 4KB data cases, each with a 4-word line 177 length. 178 179 Say Y if you want support for the ARM940T processor. 180 Otherwise, say N. 181 182# ARM946E-S 183config CPU_ARM946E 184 bool "Support ARM946E-S processor" if ARCH_INTEGRATOR 185 depends on !MMU 186 select CPU_32v5 187 select CPU_ABRT_NOMMU 188 select CPU_CACHE_VIVT 189 select CPU_CP15_MPU 190 select CPU_PABRT_LEGACY 191 help 192 ARM946E-S is a member of the ARM9E-S family of high- 193 performance, 32-bit system-on-chip processor solutions. 194 The TCM and ARMv5TE 32-bit instruction set is supported. 195 196 Say Y if you want support for the ARM946E-S processor. 197 Otherwise, say N. 198 199# ARM1020 - needs validating 200config CPU_ARM1020 201 bool "Support ARM1020T (rev 0) processor" if ARCH_INTEGRATOR 202 select CPU_32v5 203 select CPU_ABRT_EV4T 204 select CPU_CACHE_V4WT 205 select CPU_CACHE_VIVT 206 select CPU_COPY_V4WB if MMU 207 select CPU_CP15_MMU 208 select CPU_PABRT_LEGACY 209 select CPU_TLB_V4WBI if MMU 210 help 211 The ARM1020 is the 32K cached version of the ARM10 processor, 212 with an addition of a floating-point unit. 213 214 Say Y if you want support for the ARM1020 processor. 215 Otherwise, say N. 216 217# ARM1020E - needs validating 218config CPU_ARM1020E 219 bool "Support ARM1020E processor" if ARCH_INTEGRATOR 220 depends on n 221 select CPU_32v5 222 select CPU_ABRT_EV4T 223 select CPU_CACHE_V4WT 224 select CPU_CACHE_VIVT 225 select CPU_COPY_V4WB if MMU 226 select CPU_CP15_MMU 227 select CPU_PABRT_LEGACY 228 select CPU_TLB_V4WBI if MMU 229 230# ARM1022E 231config CPU_ARM1022 232 bool "Support ARM1022E processor" if ARCH_INTEGRATOR 233 select CPU_32v5 234 select CPU_ABRT_EV4T 235 select CPU_CACHE_VIVT 236 select CPU_COPY_V4WB if MMU # can probably do better 237 select CPU_CP15_MMU 238 select CPU_PABRT_LEGACY 239 select CPU_TLB_V4WBI if MMU 240 help 241 The ARM1022E is an implementation of the ARMv5TE architecture 242 based upon the ARM10 integer core with a 16KiB L1 Harvard cache, 243 embedded trace macrocell, and a floating-point unit. 244 245 Say Y if you want support for the ARM1022E processor. 246 Otherwise, say N. 247 248# ARM1026EJ-S 249config CPU_ARM1026 250 bool "Support ARM1026EJ-S processor" if ARCH_INTEGRATOR 251 select CPU_32v5 252 select CPU_ABRT_EV5T # But need Jazelle, but EV5TJ ignores bit 10 253 select CPU_CACHE_VIVT 254 select CPU_COPY_V4WB if MMU # can probably do better 255 select CPU_CP15_MMU 256 select CPU_PABRT_LEGACY 257 select CPU_TLB_V4WBI if MMU 258 help 259 The ARM1026EJ-S is an implementation of the ARMv5TEJ architecture 260 based upon the ARM10 integer core. 261 262 Say Y if you want support for the ARM1026EJ-S processor. 263 Otherwise, say N. 264 265# SA110 266config CPU_SA110 267 bool "Support StrongARM(R) SA-110 processor" if ARCH_RPC 268 select CPU_32v3 if ARCH_RPC 269 select CPU_32v4 if !ARCH_RPC 270 select CPU_ABRT_EV4 271 select CPU_CACHE_V4WB 272 select CPU_CACHE_VIVT 273 select CPU_COPY_V4WB if MMU 274 select CPU_CP15_MMU 275 select CPU_PABRT_LEGACY 276 select CPU_TLB_V4WB if MMU 277 help 278 The Intel StrongARM(R) SA-110 is a 32-bit microprocessor and 279 is available at five speeds ranging from 100 MHz to 233 MHz. 280 More information is available at 281 <http://developer.intel.com/design/strong/sa110.htm>. 282 283 Say Y if you want support for the SA-110 processor. 284 Otherwise, say N. 285 286# SA1100 287config CPU_SA1100 288 bool 289 select CPU_32v4 290 select CPU_ABRT_EV4 291 select CPU_CACHE_V4WB 292 select CPU_CACHE_VIVT 293 select CPU_CP15_MMU 294 select CPU_PABRT_LEGACY 295 select CPU_TLB_V4WB if MMU 296 297# XScale 298config CPU_XSCALE 299 bool 300 select CPU_32v5 301 select CPU_ABRT_EV5T 302 select CPU_CACHE_VIVT 303 select CPU_CP15_MMU 304 select CPU_PABRT_LEGACY 305 select CPU_TLB_V4WBI if MMU 306 307# XScale Core Version 3 308config CPU_XSC3 309 bool 310 select CPU_32v5 311 select CPU_ABRT_EV5T 312 select CPU_CACHE_VIVT 313 select CPU_CP15_MMU 314 select CPU_PABRT_LEGACY 315 select CPU_TLB_V4WBI if MMU 316 select IO_36 317 318# Marvell PJ1 (Mohawk) 319config CPU_MOHAWK 320 bool 321 select CPU_32v5 322 select CPU_ABRT_EV5T 323 select CPU_CACHE_VIVT 324 select CPU_COPY_V4WB if MMU 325 select CPU_CP15_MMU 326 select CPU_PABRT_LEGACY 327 select CPU_TLB_V4WBI if MMU 328 329# Feroceon 330config CPU_FEROCEON 331 bool 332 select CPU_32v5 333 select CPU_ABRT_EV5T 334 select CPU_CACHE_VIVT 335 select CPU_COPY_FEROCEON if MMU 336 select CPU_CP15_MMU 337 select CPU_PABRT_LEGACY 338 select CPU_TLB_FEROCEON if MMU 339 340config CPU_FEROCEON_OLD_ID 341 bool "Accept early Feroceon cores with an ARM926 ID" 342 depends on CPU_FEROCEON && !CPU_ARM926T 343 default y 344 help 345 This enables the usage of some old Feroceon cores 346 for which the CPU ID is equal to the ARM926 ID. 347 Relevant for Feroceon-1850 and early Feroceon-2850. 348 349# Marvell PJ4 350config CPU_PJ4 351 bool 352 select ARM_THUMBEE 353 select CPU_V7 354 355config CPU_PJ4B 356 bool 357 select CPU_V7 358 359# ARMv6 360config CPU_V6 361 bool "Support ARM V6 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX 362 select CPU_32v6 363 select CPU_ABRT_EV6 364 select CPU_CACHE_V6 365 select CPU_CACHE_VIPT 366 select CPU_COPY_V6 if MMU 367 select CPU_CP15_MMU 368 select CPU_HAS_ASID if MMU 369 select CPU_PABRT_V6 370 select CPU_TLB_V6 if MMU 371 372# ARMv6k 373config CPU_V6K 374 bool "Support ARM V6K processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX 375 select CPU_32v6 376 select CPU_32v6K 377 select CPU_ABRT_EV6 378 select CPU_CACHE_V6 379 select CPU_CACHE_VIPT 380 select CPU_COPY_V6 if MMU 381 select CPU_CP15_MMU 382 select CPU_HAS_ASID if MMU 383 select CPU_PABRT_V6 384 select CPU_TLB_V6 if MMU 385 386# ARMv7 387config CPU_V7 388 bool "Support ARM V7 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX 389 select CPU_32v6K 390 select CPU_32v7 391 select CPU_ABRT_EV7 392 select CPU_CACHE_V7 393 select CPU_CACHE_VIPT 394 select CPU_COPY_V6 if MMU 395 select CPU_CP15_MMU 396 select CPU_HAS_ASID if MMU 397 select CPU_PABRT_V7 398 select CPU_TLB_V7 if MMU 399 400# ARMv7M 401config CPU_V7M 402 bool 403 select CPU_32v7M 404 select CPU_ABRT_NOMMU 405 select CPU_CACHE_NOP 406 select CPU_PABRT_LEGACY 407 select CPU_THUMBONLY 408 409config CPU_THUMBONLY 410 bool 411 # There are no CPUs available with MMU that don't implement an ARM ISA: 412 depends on !MMU 413 help 414 Select this if your CPU doesn't support the 32 bit ARM instructions. 415 416# Figure out what processor architecture version we should be using. 417# This defines the compiler instruction set which depends on the machine type. 418config CPU_32v3 419 bool 420 select CPU_USE_DOMAINS if MMU 421 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP 422 select TLS_REG_EMUL if SMP || !MMU 423 424config CPU_32v4 425 bool 426 select CPU_USE_DOMAINS if MMU 427 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP 428 select TLS_REG_EMUL if SMP || !MMU 429 430config CPU_32v4T 431 bool 432 select CPU_USE_DOMAINS if MMU 433 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP 434 select TLS_REG_EMUL if SMP || !MMU 435 436config CPU_32v5 437 bool 438 select CPU_USE_DOMAINS if MMU 439 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP 440 select TLS_REG_EMUL if SMP || !MMU 441 442config CPU_32v6 443 bool 444 select CPU_USE_DOMAINS if CPU_V6 && MMU 445 select TLS_REG_EMUL if !CPU_32v6K && !MMU 446 447config CPU_32v6K 448 bool 449 450config CPU_32v7 451 bool 452 453config CPU_32v7M 454 bool 455 456# The abort model 457config CPU_ABRT_NOMMU 458 bool 459 460config CPU_ABRT_EV4 461 bool 462 463config CPU_ABRT_EV4T 464 bool 465 466config CPU_ABRT_LV4T 467 bool 468 469config CPU_ABRT_EV5T 470 bool 471 472config CPU_ABRT_EV5TJ 473 bool 474 475config CPU_ABRT_EV6 476 bool 477 478config CPU_ABRT_EV7 479 bool 480 481config CPU_PABRT_LEGACY 482 bool 483 484config CPU_PABRT_V6 485 bool 486 487config CPU_PABRT_V7 488 bool 489 490# The cache model 491config CPU_CACHE_V3 492 bool 493 494config CPU_CACHE_V4 495 bool 496 497config CPU_CACHE_V4WT 498 bool 499 500config CPU_CACHE_V4WB 501 bool 502 503config CPU_CACHE_V6 504 bool 505 506config CPU_CACHE_V7 507 bool 508 509config CPU_CACHE_NOP 510 bool 511 512config CPU_CACHE_VIVT 513 bool 514 515config CPU_CACHE_VIPT 516 bool 517 518config CPU_CACHE_FA 519 bool 520 521if MMU 522# The copy-page model 523config CPU_COPY_V4WT 524 bool 525 526config CPU_COPY_V4WB 527 bool 528 529config CPU_COPY_FEROCEON 530 bool 531 532config CPU_COPY_FA 533 bool 534 535config CPU_COPY_V6 536 bool 537 538# This selects the TLB model 539config CPU_TLB_V4WT 540 bool 541 help 542 ARM Architecture Version 4 TLB with writethrough cache. 543 544config CPU_TLB_V4WB 545 bool 546 help 547 ARM Architecture Version 4 TLB with writeback cache. 548 549config CPU_TLB_V4WBI 550 bool 551 help 552 ARM Architecture Version 4 TLB with writeback cache and invalidate 553 instruction cache entry. 554 555config CPU_TLB_FEROCEON 556 bool 557 help 558 Feroceon TLB (v4wbi with non-outer-cachable page table walks). 559 560config CPU_TLB_FA 561 bool 562 help 563 Faraday ARM FA526 architecture, unified TLB with writeback cache 564 and invalidate instruction cache entry. Branch target buffer is 565 also supported. 566 567config CPU_TLB_V6 568 bool 569 570config CPU_TLB_V7 571 bool 572 573config VERIFY_PERMISSION_FAULT 574 bool 575endif 576 577config CPU_HAS_ASID 578 bool 579 help 580 This indicates whether the CPU has the ASID register; used to 581 tag TLB and possibly cache entries. 582 583config CPU_CP15 584 bool 585 help 586 Processor has the CP15 register. 587 588config CPU_CP15_MMU 589 bool 590 select CPU_CP15 591 help 592 Processor has the CP15 register, which has MMU related registers. 593 594config CPU_CP15_MPU 595 bool 596 select CPU_CP15 597 help 598 Processor has the CP15 register, which has MPU related registers. 599 600config CPU_USE_DOMAINS 601 bool 602 help 603 This option enables or disables the use of domain switching 604 via the set_fs() function. 605 606# 607# CPU supports 36-bit I/O 608# 609config IO_36 610 bool 611 612comment "Processor Features" 613 614config ARM_LPAE 615 bool "Support for the Large Physical Address Extension" 616 depends on MMU && CPU_32v7 && !CPU_32v6 && !CPU_32v5 && \ 617 !CPU_32v4 && !CPU_32v3 618 help 619 Say Y if you have an ARMv7 processor supporting the LPAE page 620 table format and you would like to access memory beyond the 621 4GB limit. The resulting kernel image will not run on 622 processors without the LPA extension. 623 624 If unsure, say N. 625 626config ARCH_PHYS_ADDR_T_64BIT 627 def_bool ARM_LPAE 628 629config ARCH_DMA_ADDR_T_64BIT 630 bool 631 632config ARM_THUMB 633 bool "Support Thumb user binaries" if !CPU_THUMBONLY 634 depends on CPU_ARM720T || CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || \ 635 CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || \ 636 CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \ 637 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_V6 || CPU_V6K || \ 638 CPU_V7 || CPU_FEROCEON || CPU_V7M 639 default y 640 help 641 Say Y if you want to include kernel support for running user space 642 Thumb binaries. 643 644 The Thumb instruction set is a compressed form of the standard ARM 645 instruction set resulting in smaller binaries at the expense of 646 slightly less efficient code. 647 648 If you don't know what this all is, saying Y is a safe choice. 649 650config ARM_THUMBEE 651 bool "Enable ThumbEE CPU extension" 652 depends on CPU_V7 653 help 654 Say Y here if you have a CPU with the ThumbEE extension and code to 655 make use of it. Say N for code that can run on CPUs without ThumbEE. 656 657config ARM_VIRT_EXT 658 bool 659 depends on MMU 660 default y if CPU_V7 661 help 662 Enable the kernel to make use of the ARM Virtualization 663 Extensions to install hypervisors without run-time firmware 664 assistance. 665 666 A compliant bootloader is required in order to make maximum 667 use of this feature. Refer to Documentation/arm/Booting for 668 details. 669 670config SWP_EMULATE 671 bool "Emulate SWP/SWPB instructions" 672 depends on !CPU_USE_DOMAINS && CPU_V7 673 default y if SMP 674 select HAVE_PROC_CPU if PROC_FS 675 help 676 ARMv6 architecture deprecates use of the SWP/SWPB instructions. 677 ARMv7 multiprocessing extensions introduce the ability to disable 678 these instructions, triggering an undefined instruction exception 679 when executed. Say Y here to enable software emulation of these 680 instructions for userspace (not kernel) using LDREX/STREX. 681 Also creates /proc/cpu/swp_emulation for statistics. 682 683 In some older versions of glibc [<=2.8] SWP is used during futex 684 trylock() operations with the assumption that the code will not 685 be preempted. This invalid assumption may be more likely to fail 686 with SWP emulation enabled, leading to deadlock of the user 687 application. 688 689 NOTE: when accessing uncached shared regions, LDREX/STREX rely 690 on an external transaction monitoring block called a global 691 monitor to maintain update atomicity. If your system does not 692 implement a global monitor, this option can cause programs that 693 perform SWP operations to uncached memory to deadlock. 694 695 If unsure, say Y. 696 697config CPU_BIG_ENDIAN 698 bool "Build big-endian kernel" 699 depends on ARCH_SUPPORTS_BIG_ENDIAN 700 help 701 Say Y if you plan on running a kernel in big-endian mode. 702 Note that your board must be properly built and your board 703 port must properly enable any big-endian related features 704 of your chipset/board/processor. 705 706config CPU_ENDIAN_BE8 707 bool 708 depends on CPU_BIG_ENDIAN 709 default CPU_V6 || CPU_V6K || CPU_V7 710 help 711 Support for the BE-8 (big-endian) mode on ARMv6 and ARMv7 processors. 712 713config CPU_ENDIAN_BE32 714 bool 715 depends on CPU_BIG_ENDIAN 716 default !CPU_ENDIAN_BE8 717 help 718 Support for the BE-32 (big-endian) mode on pre-ARMv6 processors. 719 720config CPU_HIGH_VECTOR 721 depends on !MMU && CPU_CP15 && !CPU_ARM740T 722 bool "Select the High exception vector" 723 help 724 Say Y here to select high exception vector(0xFFFF0000~). 725 The exception vector can vary depending on the platform 726 design in nommu mode. If your platform needs to select 727 high exception vector, say Y. 728 Otherwise or if you are unsure, say N, and the low exception 729 vector (0x00000000~) will be used. 730 731config CPU_ICACHE_DISABLE 732 bool "Disable I-Cache (I-bit)" 733 depends on CPU_CP15 && !(CPU_ARM720T || CPU_ARM740T || CPU_XSCALE || CPU_XSC3) 734 help 735 Say Y here to disable the processor instruction cache. Unless 736 you have a reason not to or are unsure, say N. 737 738config CPU_DCACHE_DISABLE 739 bool "Disable D-Cache (C-bit)" 740 depends on CPU_CP15 741 help 742 Say Y here to disable the processor data cache. Unless 743 you have a reason not to or are unsure, say N. 744 745config CPU_DCACHE_SIZE 746 hex 747 depends on CPU_ARM740T || CPU_ARM946E 748 default 0x00001000 if CPU_ARM740T 749 default 0x00002000 # default size for ARM946E-S 750 help 751 Some cores are synthesizable to have various sized cache. For 752 ARM946E-S case, it can vary from 0KB to 1MB. 753 To support such cache operations, it is efficient to know the size 754 before compile time. 755 If your SoC is configured to have a different size, define the value 756 here with proper conditions. 757 758config CPU_DCACHE_WRITETHROUGH 759 bool "Force write through D-cache" 760 depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_FA526) && !CPU_DCACHE_DISABLE 761 default y if CPU_ARM925T 762 help 763 Say Y here to use the data cache in writethrough mode. Unless you 764 specifically require this or are unsure, say N. 765 766config CPU_CACHE_ROUND_ROBIN 767 bool "Round robin I and D cache replacement algorithm" 768 depends on (CPU_ARM926T || CPU_ARM946E || CPU_ARM1020) && (!CPU_ICACHE_DISABLE || !CPU_DCACHE_DISABLE) 769 help 770 Say Y here to use the predictable round-robin cache replacement 771 policy. Unless you specifically require this or are unsure, say N. 772 773config CPU_BPREDICT_DISABLE 774 bool "Disable branch prediction" 775 depends on CPU_ARM1020 || CPU_V6 || CPU_V6K || CPU_MOHAWK || CPU_XSC3 || CPU_V7 || CPU_FA526 776 help 777 Say Y here to disable branch prediction. If unsure, say N. 778 779config TLS_REG_EMUL 780 bool 781 help 782 An SMP system using a pre-ARMv6 processor (there are apparently 783 a few prototypes like that in existence) and therefore access to 784 that required register must be emulated. 785 786config NEEDS_SYSCALL_FOR_CMPXCHG 787 bool 788 help 789 SMP on a pre-ARMv6 processor? Well OK then. 790 Forget about fast user space cmpxchg support. 791 It is just not possible. 792 793config DMA_CACHE_RWFO 794 bool "Enable read/write for ownership DMA cache maintenance" 795 depends on CPU_V6K && SMP 796 default y 797 help 798 The Snoop Control Unit on ARM11MPCore does not detect the 799 cache maintenance operations and the dma_{map,unmap}_area() 800 functions may leave stale cache entries on other CPUs. By 801 enabling this option, Read or Write For Ownership in the ARMv6 802 DMA cache maintenance functions is performed. These LDR/STR 803 instructions change the cache line state to shared or modified 804 so that the cache operation has the desired effect. 805 806 Note that the workaround is only valid on processors that do 807 not perform speculative loads into the D-cache. For such 808 processors, if cache maintenance operations are not broadcast 809 in hardware, other workarounds are needed (e.g. cache 810 maintenance broadcasting in software via FIQ). 811 812config OUTER_CACHE 813 bool 814 815config OUTER_CACHE_SYNC 816 bool 817 help 818 The outer cache has a outer_cache_fns.sync function pointer 819 that can be used to drain the write buffer of the outer cache. 820 821config CACHE_FEROCEON_L2 822 bool "Enable the Feroceon L2 cache controller" 823 depends on ARCH_KIRKWOOD || ARCH_MV78XX0 824 default y 825 select OUTER_CACHE 826 help 827 This option enables the Feroceon L2 cache controller. 828 829config CACHE_FEROCEON_L2_WRITETHROUGH 830 bool "Force Feroceon L2 cache write through" 831 depends on CACHE_FEROCEON_L2 832 help 833 Say Y here to use the Feroceon L2 cache in writethrough mode. 834 Unless you specifically require this, say N for writeback mode. 835 836config MIGHT_HAVE_CACHE_L2X0 837 bool 838 help 839 This option should be selected by machines which have a L2x0 840 or PL310 cache controller, but where its use is optional. 841 842 The only effect of this option is to make CACHE_L2X0 and 843 related options available to the user for configuration. 844 845 Boards or SoCs which always require the cache controller 846 support to be present should select CACHE_L2X0 directly 847 instead of this option, thus preventing the user from 848 inadvertently configuring a broken kernel. 849 850config CACHE_L2X0 851 bool "Enable the L2x0 outer cache controller" if MIGHT_HAVE_CACHE_L2X0 852 default MIGHT_HAVE_CACHE_L2X0 853 select OUTER_CACHE 854 select OUTER_CACHE_SYNC 855 help 856 This option enables the L2x0 PrimeCell. 857 858config CACHE_PL310 859 bool 860 depends on CACHE_L2X0 861 default y if CPU_V7 && !(CPU_V6 || CPU_V6K) 862 help 863 This option enables optimisations for the PL310 cache 864 controller. 865 866config CACHE_TAUROS2 867 bool "Enable the Tauros2 L2 cache controller" 868 depends on (ARCH_DOVE || ARCH_MMP || CPU_PJ4) 869 default y 870 select OUTER_CACHE 871 help 872 This option enables the Tauros2 L2 cache controller (as 873 found on PJ1/PJ4). 874 875config CACHE_XSC3L2 876 bool "Enable the L2 cache on XScale3" 877 depends on CPU_XSC3 878 default y 879 select OUTER_CACHE 880 help 881 This option enables the L2 cache on XScale3. 882 883config ARM_L1_CACHE_SHIFT_6 884 bool 885 default y if CPU_V7 886 help 887 Setting ARM L1 cache line size to 64 Bytes. 888 889config ARM_L1_CACHE_SHIFT 890 int 891 default 6 if ARM_L1_CACHE_SHIFT_6 892 default 5 893 894config ARM_DMA_MEM_BUFFERABLE 895 bool "Use non-cacheable memory for DMA" if (CPU_V6 || CPU_V6K) && !CPU_V7 896 depends on !(MACH_REALVIEW_PB1176 || REALVIEW_EB_ARM11MP || \ 897 MACH_REALVIEW_PB11MP) 898 default y if CPU_V6 || CPU_V6K || CPU_V7 899 help 900 Historically, the kernel has used strongly ordered mappings to 901 provide DMA coherent memory. With the advent of ARMv7, mapping 902 memory with differing types results in unpredictable behaviour, 903 so on these CPUs, this option is forced on. 904 905 Multiple mappings with differing attributes is also unpredictable 906 on ARMv6 CPUs, but since they do not have aggressive speculative 907 prefetch, no harm appears to occur. 908 909 However, drivers may be missing the necessary barriers for ARMv6, 910 and therefore turning this on may result in unpredictable driver 911 behaviour. Therefore, we offer this as an option. 912 913 You are recommended say 'Y' here and debug any affected drivers. 914 915config ARCH_HAS_BARRIERS 916 bool 917 help 918 This option allows the use of custom mandatory barriers 919 included via the mach/barriers.h file. 920