pxa3xx.c (68d2cf25d39324c54b5e42de7915c623a0917abe) pxa3xx.c (2eaa03b5bebd1e80014f780d7bf27c3e66daefd6)
1/*
2 * linux/arch/arm/mach-pxa/pxa3xx.c
3 *
4 * code specific to pxa3xx aka Monahans
5 *
6 * Copyright (C) 2006 Marvell International Ltd.
7 *
8 * 2007-09-02: eric miao <eric.miao@marvell.com>

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15
16#include <linux/module.h>
17#include <linux/kernel.h>
18#include <linux/init.h>
19#include <linux/pm.h>
20#include <linux/platform_device.h>
21#include <linux/irq.h>
22#include <linux/io.h>
1/*
2 * linux/arch/arm/mach-pxa/pxa3xx.c
3 *
4 * code specific to pxa3xx aka Monahans
5 *
6 * Copyright (C) 2006 Marvell International Ltd.
7 *
8 * 2007-09-02: eric miao <eric.miao@marvell.com>

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15
16#include <linux/module.h>
17#include <linux/kernel.h>
18#include <linux/init.h>
19#include <linux/pm.h>
20#include <linux/platform_device.h>
21#include <linux/irq.h>
22#include <linux/io.h>
23#include <linux/sysdev.h>
23#include <linux/syscore_ops.h>
24#include <linux/i2c/pxa-i2c.h>
25
26#include <asm/mach/map.h>
27#include <mach/hardware.h>
28#include <mach/gpio.h>
29#include <mach/pxa3xx-regs.h>
30#include <mach/reset.h>
31#include <mach/ohci.h>

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422 &pxa27x_device_ssp1,
423 &pxa27x_device_ssp2,
424 &pxa27x_device_ssp3,
425 &pxa3xx_device_ssp4,
426 &pxa27x_device_pwm0,
427 &pxa27x_device_pwm1,
428};
429
24#include <linux/i2c/pxa-i2c.h>
25
26#include <asm/mach/map.h>
27#include <mach/hardware.h>
28#include <mach/gpio.h>
29#include <mach/pxa3xx-regs.h>
30#include <mach/reset.h>
31#include <mach/ohci.h>

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422 &pxa27x_device_ssp1,
423 &pxa27x_device_ssp2,
424 &pxa27x_device_ssp3,
425 &pxa3xx_device_ssp4,
426 &pxa27x_device_pwm0,
427 &pxa27x_device_pwm1,
428};
429
430static struct sys_device pxa3xx_sysdev[] = {
431 {
432 .cls = &pxa_irq_sysclass,
433 }, {
434 .cls = &pxa3xx_mfp_sysclass,
435 }, {
436 .cls = &pxa_gpio_sysclass,
437 }, {
438 .cls = &pxa3xx_clock_sysclass,
439 }
440};
441
442static int __init pxa3xx_init(void)
443{
430static int __init pxa3xx_init(void)
431{
444 int i, ret = 0;
432 int ret = 0;
445
446 if (cpu_is_pxa3xx()) {
447
448 reset_status = ARSR;
449
450 /*
451 * clear RDH bit every time after reset
452 *

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457
458 clkdev_add_table(pxa3xx_clkregs, ARRAY_SIZE(pxa3xx_clkregs));
459
460 if ((ret = pxa_init_dma(IRQ_DMA, 32)))
461 return ret;
462
463 pxa3xx_init_pm();
464
433
434 if (cpu_is_pxa3xx()) {
435
436 reset_status = ARSR;
437
438 /*
439 * clear RDH bit every time after reset
440 *

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445
446 clkdev_add_table(pxa3xx_clkregs, ARRAY_SIZE(pxa3xx_clkregs));
447
448 if ((ret = pxa_init_dma(IRQ_DMA, 32)))
449 return ret;
450
451 pxa3xx_init_pm();
452
465 for (i = 0; i < ARRAY_SIZE(pxa3xx_sysdev); i++) {
466 ret = sysdev_register(&pxa3xx_sysdev[i]);
467 if (ret)
468 pr_err("failed to register sysdev[%d]\n", i);
469 }
453 register_syscore_ops(&pxa_irq_syscore_ops);
454 register_syscore_ops(&pxa3xx_mfp_syscore_ops);
455 register_syscore_ops(&pxa_gpio_syscore_ops);
456 register_syscore_ops(&pxa3xx_clock_syscore_ops);
470
471 ret = platform_add_devices(devices, ARRAY_SIZE(devices));
472 }
473
474 return ret;
475}
476
477postcore_initcall(pxa3xx_init);
457
458 ret = platform_add_devices(devices, ARRAY_SIZE(devices));
459 }
460
461 return ret;
462}
463
464postcore_initcall(pxa3xx_init);