xref: /linux/arch/arm/mach-pxa/pxa3xx.c (revision 2eaa03b5bebd1e80014f780d7bf27c3e66daefd6) 
1 /*
2  * linux/arch/arm/mach-pxa/pxa3xx.c
3  *
4  * code specific to pxa3xx aka Monahans
5  *
6  * Copyright (C) 2006 Marvell International Ltd.
7  *
8  * 2007-09-02: eric miao <eric.miao@marvell.com>
9  *             initial version
10  *
11  * This program is free software; you can redistribute it and/or modify
12  * it under the terms of the GNU General Public License version 2 as
13  * published by the Free Software Foundation.
14  */
15 
16 #include <linux/module.h>
17 #include <linux/kernel.h>
18 #include <linux/init.h>
19 #include <linux/pm.h>
20 #include <linux/platform_device.h>
21 #include <linux/irq.h>
22 #include <linux/io.h>
23 #include <linux/syscore_ops.h>
24 #include <linux/i2c/pxa-i2c.h>
25 
26 #include <asm/mach/map.h>
27 #include <mach/hardware.h>
28 #include <mach/gpio.h>
29 #include <mach/pxa3xx-regs.h>
30 #include <mach/reset.h>
31 #include <mach/ohci.h>
32 #include <mach/pm.h>
33 #include <mach/dma.h>
34 #include <mach/regs-intc.h>
35 #include <mach/smemc.h>
36 
37 #include "generic.h"
38 #include "devices.h"
39 #include "clock.h"
40 
41 #define PECR_IE(n)	((1 << ((n) * 2)) << 28)
42 #define PECR_IS(n)	((1 << ((n) * 2)) << 29)
43 
44 static DEFINE_PXA3_CKEN(pxa3xx_ffuart, FFUART, 14857000, 1);
45 static DEFINE_PXA3_CKEN(pxa3xx_btuart, BTUART, 14857000, 1);
46 static DEFINE_PXA3_CKEN(pxa3xx_stuart, STUART, 14857000, 1);
47 static DEFINE_PXA3_CKEN(pxa3xx_i2c, I2C, 32842000, 0);
48 static DEFINE_PXA3_CKEN(pxa3xx_udc, UDC, 48000000, 5);
49 static DEFINE_PXA3_CKEN(pxa3xx_usbh, USBH, 48000000, 0);
50 static DEFINE_PXA3_CKEN(pxa3xx_u2d, USB2, 48000000, 0);
51 static DEFINE_PXA3_CKEN(pxa3xx_keypad, KEYPAD, 32768, 0);
52 static DEFINE_PXA3_CKEN(pxa3xx_ssp1, SSP1, 13000000, 0);
53 static DEFINE_PXA3_CKEN(pxa3xx_ssp2, SSP2, 13000000, 0);
54 static DEFINE_PXA3_CKEN(pxa3xx_ssp3, SSP3, 13000000, 0);
55 static DEFINE_PXA3_CKEN(pxa3xx_ssp4, SSP4, 13000000, 0);
56 static DEFINE_PXA3_CKEN(pxa3xx_pwm0, PWM0, 13000000, 0);
57 static DEFINE_PXA3_CKEN(pxa3xx_pwm1, PWM1, 13000000, 0);
58 static DEFINE_PXA3_CKEN(pxa3xx_mmc1, MMC1, 19500000, 0);
59 static DEFINE_PXA3_CKEN(pxa3xx_mmc2, MMC2, 19500000, 0);
60 
61 static DEFINE_CK(pxa3xx_lcd, LCD, &clk_pxa3xx_hsio_ops);
62 static DEFINE_CK(pxa3xx_smemc, SMC, &clk_pxa3xx_smemc_ops);
63 static DEFINE_CK(pxa3xx_camera, CAMERA, &clk_pxa3xx_hsio_ops);
64 static DEFINE_CK(pxa3xx_ac97, AC97, &clk_pxa3xx_ac97_ops);
65 static DEFINE_CLK(pxa3xx_pout, &clk_pxa3xx_pout_ops, 13000000, 70);
66 
67 static struct clk_lookup pxa3xx_clkregs[] = {
68 	INIT_CLKREG(&clk_pxa3xx_pout, NULL, "CLK_POUT"),
69 	/* Power I2C clock is always on */
70 	INIT_CLKREG(&clk_dummy, "pxa3xx-pwri2c.1", NULL),
71 	INIT_CLKREG(&clk_pxa3xx_lcd, "pxa2xx-fb", NULL),
72 	INIT_CLKREG(&clk_pxa3xx_camera, NULL, "CAMCLK"),
73 	INIT_CLKREG(&clk_pxa3xx_ac97, NULL, "AC97CLK"),
74 	INIT_CLKREG(&clk_pxa3xx_ffuart, "pxa2xx-uart.0", NULL),
75 	INIT_CLKREG(&clk_pxa3xx_btuart, "pxa2xx-uart.1", NULL),
76 	INIT_CLKREG(&clk_pxa3xx_stuart, "pxa2xx-uart.2", NULL),
77 	INIT_CLKREG(&clk_pxa3xx_stuart, "pxa2xx-ir", "UARTCLK"),
78 	INIT_CLKREG(&clk_pxa3xx_i2c, "pxa2xx-i2c.0", NULL),
79 	INIT_CLKREG(&clk_pxa3xx_udc, "pxa27x-udc", NULL),
80 	INIT_CLKREG(&clk_pxa3xx_usbh, "pxa27x-ohci", NULL),
81 	INIT_CLKREG(&clk_pxa3xx_u2d, "pxa3xx-u2d", NULL),
82 	INIT_CLKREG(&clk_pxa3xx_keypad, "pxa27x-keypad", NULL),
83 	INIT_CLKREG(&clk_pxa3xx_ssp1, "pxa27x-ssp.0", NULL),
84 	INIT_CLKREG(&clk_pxa3xx_ssp2, "pxa27x-ssp.1", NULL),
85 	INIT_CLKREG(&clk_pxa3xx_ssp3, "pxa27x-ssp.2", NULL),
86 	INIT_CLKREG(&clk_pxa3xx_ssp4, "pxa27x-ssp.3", NULL),
87 	INIT_CLKREG(&clk_pxa3xx_pwm0, "pxa27x-pwm.0", NULL),
88 	INIT_CLKREG(&clk_pxa3xx_pwm1, "pxa27x-pwm.1", NULL),
89 	INIT_CLKREG(&clk_pxa3xx_mmc1, "pxa2xx-mci.0", NULL),
90 	INIT_CLKREG(&clk_pxa3xx_mmc2, "pxa2xx-mci.1", NULL),
91 	INIT_CLKREG(&clk_pxa3xx_smemc, "pxa2xx-pcmcia", NULL),
92 };
93 
94 #ifdef CONFIG_PM
95 
96 #define ISRAM_START	0x5c000000
97 #define ISRAM_SIZE	SZ_256K
98 
99 static void __iomem *sram;
100 static unsigned long wakeup_src;
101 
102 /*
103  * Enter a standby mode (S0D1C2 or S0D2C2).  Upon wakeup, the dynamic
104  * memory controller has to be reinitialised, so we place some code
105  * in the SRAM to perform this function.
106  *
107  * We disable FIQs across the standby - otherwise, we might receive a
108  * FIQ while the SDRAM is unavailable.
109  */
110 static void pxa3xx_cpu_standby(unsigned int pwrmode)
111 {
112 	extern const char pm_enter_standby_start[], pm_enter_standby_end[];
113 	void (*fn)(unsigned int) = (void __force *)(sram + 0x8000);
114 
115 	memcpy_toio(sram + 0x8000, pm_enter_standby_start,
116 		    pm_enter_standby_end - pm_enter_standby_start);
117 
118 	AD2D0SR = ~0;
119 	AD2D1SR = ~0;
120 	AD2D0ER = wakeup_src;
121 	AD2D1ER = 0;
122 	ASCR = ASCR;
123 	ARSR = ARSR;
124 
125 	local_fiq_disable();
126 	fn(pwrmode);
127 	local_fiq_enable();
128 
129 	AD2D0ER = 0;
130 	AD2D1ER = 0;
131 }
132 
133 /*
134  * NOTE:  currently, the OBM (OEM Boot Module) binary comes along with
135  * PXA3xx development kits assumes that the resuming process continues
136  * with the address stored within the first 4 bytes of SDRAM. The PSPR
137  * register is used privately by BootROM and OBM, and _must_ be set to
138  * 0x5c014000 for the moment.
139  */
140 static void pxa3xx_cpu_pm_suspend(void)
141 {
142 	volatile unsigned long *p = (volatile void *)0xc0000000;
143 	unsigned long saved_data = *p;
144 
145 	extern void pxa3xx_cpu_suspend(long);
146 
147 	/* resuming from D2 requires the HSIO2/BOOT/TPM clocks enabled */
148 	CKENA |= (1 << CKEN_BOOT) | (1 << CKEN_TPM);
149 	CKENB |= 1 << (CKEN_HSIO2 & 0x1f);
150 
151 	/* clear and setup wakeup source */
152 	AD3SR = ~0;
153 	AD3ER = wakeup_src;
154 	ASCR = ASCR;
155 	ARSR = ARSR;
156 
157 	PCFR |= (1u << 13);			/* L1_DIS */
158 	PCFR &= ~((1u << 12) | (1u << 1));	/* L0_EN | SL_ROD */
159 
160 	PSPR = 0x5c014000;
161 
162 	/* overwrite with the resume address */
163 	*p = virt_to_phys(cpu_resume);
164 
165 	pxa3xx_cpu_suspend(PLAT_PHYS_OFFSET - PAGE_OFFSET);
166 
167 	*p = saved_data;
168 
169 	AD3ER = 0;
170 }
171 
172 static void pxa3xx_cpu_pm_enter(suspend_state_t state)
173 {
174 	/*
175 	 * Don't sleep if no wakeup sources are defined
176 	 */
177 	if (wakeup_src == 0) {
178 		printk(KERN_ERR "Not suspending: no wakeup sources\n");
179 		return;
180 	}
181 
182 	switch (state) {
183 	case PM_SUSPEND_STANDBY:
184 		pxa3xx_cpu_standby(PXA3xx_PM_S0D2C2);
185 		break;
186 
187 	case PM_SUSPEND_MEM:
188 		pxa3xx_cpu_pm_suspend();
189 		break;
190 	}
191 }
192 
193 static int pxa3xx_cpu_pm_valid(suspend_state_t state)
194 {
195 	return state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY;
196 }
197 
198 static struct pxa_cpu_pm_fns pxa3xx_cpu_pm_fns = {
199 	.valid		= pxa3xx_cpu_pm_valid,
200 	.enter		= pxa3xx_cpu_pm_enter,
201 };
202 
203 static void __init pxa3xx_init_pm(void)
204 {
205 	sram = ioremap(ISRAM_START, ISRAM_SIZE);
206 	if (!sram) {
207 		printk(KERN_ERR "Unable to map ISRAM: disabling standby/suspend\n");
208 		return;
209 	}
210 
211 	/*
212 	 * Since we copy wakeup code into the SRAM, we need to ensure
213 	 * that it is preserved over the low power modes.  Note: bit 8
214 	 * is undocumented in the developer manual, but must be set.
215 	 */
216 	AD1R |= ADXR_L2 | ADXR_R0;
217 	AD2R |= ADXR_L2 | ADXR_R0;
218 	AD3R |= ADXR_L2 | ADXR_R0;
219 
220 	/*
221 	 * Clear the resume enable registers.
222 	 */
223 	AD1D0ER = 0;
224 	AD2D0ER = 0;
225 	AD2D1ER = 0;
226 	AD3ER = 0;
227 
228 	pxa_cpu_pm_fns = &pxa3xx_cpu_pm_fns;
229 }
230 
231 static int pxa3xx_set_wake(struct irq_data *d, unsigned int on)
232 {
233 	unsigned long flags, mask = 0;
234 
235 	switch (d->irq) {
236 	case IRQ_SSP3:
237 		mask = ADXER_MFP_WSSP3;
238 		break;
239 	case IRQ_MSL:
240 		mask = ADXER_WMSL0;
241 		break;
242 	case IRQ_USBH2:
243 	case IRQ_USBH1:
244 		mask = ADXER_WUSBH;
245 		break;
246 	case IRQ_KEYPAD:
247 		mask = ADXER_WKP;
248 		break;
249 	case IRQ_AC97:
250 		mask = ADXER_MFP_WAC97;
251 		break;
252 	case IRQ_USIM:
253 		mask = ADXER_WUSIM0;
254 		break;
255 	case IRQ_SSP2:
256 		mask = ADXER_MFP_WSSP2;
257 		break;
258 	case IRQ_I2C:
259 		mask = ADXER_MFP_WI2C;
260 		break;
261 	case IRQ_STUART:
262 		mask = ADXER_MFP_WUART3;
263 		break;
264 	case IRQ_BTUART:
265 		mask = ADXER_MFP_WUART2;
266 		break;
267 	case IRQ_FFUART:
268 		mask = ADXER_MFP_WUART1;
269 		break;
270 	case IRQ_MMC:
271 		mask = ADXER_MFP_WMMC1;
272 		break;
273 	case IRQ_SSP:
274 		mask = ADXER_MFP_WSSP1;
275 		break;
276 	case IRQ_RTCAlrm:
277 		mask = ADXER_WRTC;
278 		break;
279 	case IRQ_SSP4:
280 		mask = ADXER_MFP_WSSP4;
281 		break;
282 	case IRQ_TSI:
283 		mask = ADXER_WTSI;
284 		break;
285 	case IRQ_USIM2:
286 		mask = ADXER_WUSIM1;
287 		break;
288 	case IRQ_MMC2:
289 		mask = ADXER_MFP_WMMC2;
290 		break;
291 	case IRQ_NAND:
292 		mask = ADXER_MFP_WFLASH;
293 		break;
294 	case IRQ_USB2:
295 		mask = ADXER_WUSB2;
296 		break;
297 	case IRQ_WAKEUP0:
298 		mask = ADXER_WEXTWAKE0;
299 		break;
300 	case IRQ_WAKEUP1:
301 		mask = ADXER_WEXTWAKE1;
302 		break;
303 	case IRQ_MMC3:
304 		mask = ADXER_MFP_GEN12;
305 		break;
306 	default:
307 		return -EINVAL;
308 	}
309 
310 	local_irq_save(flags);
311 	if (on)
312 		wakeup_src |= mask;
313 	else
314 		wakeup_src &= ~mask;
315 	local_irq_restore(flags);
316 
317 	return 0;
318 }
319 #else
320 static inline void pxa3xx_init_pm(void) {}
321 #define pxa3xx_set_wake	NULL
322 #endif
323 
324 static void pxa_ack_ext_wakeup(struct irq_data *d)
325 {
326 	PECR |= PECR_IS(d->irq - IRQ_WAKEUP0);
327 }
328 
329 static void pxa_mask_ext_wakeup(struct irq_data *d)
330 {
331 	ICMR2 &= ~(1 << ((d->irq - PXA_IRQ(0)) & 0x1f));
332 	PECR &= ~PECR_IE(d->irq - IRQ_WAKEUP0);
333 }
334 
335 static void pxa_unmask_ext_wakeup(struct irq_data *d)
336 {
337 	ICMR2 |= 1 << ((d->irq - PXA_IRQ(0)) & 0x1f);
338 	PECR |= PECR_IE(d->irq - IRQ_WAKEUP0);
339 }
340 
341 static int pxa_set_ext_wakeup_type(struct irq_data *d, unsigned int flow_type)
342 {
343 	if (flow_type & IRQ_TYPE_EDGE_RISING)
344 		PWER |= 1 << (d->irq - IRQ_WAKEUP0);
345 
346 	if (flow_type & IRQ_TYPE_EDGE_FALLING)
347 		PWER |= 1 << (d->irq - IRQ_WAKEUP0 + 2);
348 
349 	return 0;
350 }
351 
352 static struct irq_chip pxa_ext_wakeup_chip = {
353 	.name		= "WAKEUP",
354 	.irq_ack	= pxa_ack_ext_wakeup,
355 	.irq_mask	= pxa_mask_ext_wakeup,
356 	.irq_unmask	= pxa_unmask_ext_wakeup,
357 	.irq_set_type	= pxa_set_ext_wakeup_type,
358 };
359 
360 static void __init pxa_init_ext_wakeup_irq(set_wake_t fn)
361 {
362 	int irq;
363 
364 	for (irq = IRQ_WAKEUP0; irq <= IRQ_WAKEUP1; irq++) {
365 		irq_set_chip_and_handler(irq, &pxa_ext_wakeup_chip,
366 					 handle_edge_irq);
367 		set_irq_flags(irq, IRQF_VALID);
368 	}
369 
370 	pxa_ext_wakeup_chip.irq_set_wake = fn;
371 }
372 
373 void __init pxa3xx_init_irq(void)
374 {
375 	/* enable CP6 access */
376 	u32 value;
377 	__asm__ __volatile__("mrc p15, 0, %0, c15, c1, 0\n": "=r"(value));
378 	value |= (1 << 6);
379 	__asm__ __volatile__("mcr p15, 0, %0, c15, c1, 0\n": :"r"(value));
380 
381 	pxa_init_irq(56, pxa3xx_set_wake);
382 	pxa_init_ext_wakeup_irq(pxa3xx_set_wake);
383 	pxa_init_gpio(IRQ_GPIO_2_x, 2, 127, NULL);
384 }
385 
386 static struct map_desc pxa3xx_io_desc[] __initdata = {
387 	{	/* Mem Ctl */
388 		.virtual	= SMEMC_VIRT,
389 		.pfn		= __phys_to_pfn(PXA3XX_SMEMC_BASE),
390 		.length		= 0x00200000,
391 		.type		= MT_DEVICE
392 	}
393 };
394 
395 void __init pxa3xx_map_io(void)
396 {
397 	pxa_map_io();
398 	iotable_init(ARRAY_AND_SIZE(pxa3xx_io_desc));
399 	pxa3xx_get_clk_frequency_khz(1);
400 }
401 
402 /*
403  * device registration specific to PXA3xx.
404  */
405 
406 void __init pxa3xx_set_i2c_power_info(struct i2c_pxa_platform_data *info)
407 {
408 	pxa_register_device(&pxa3xx_device_i2c_power, info);
409 }
410 
411 static struct platform_device *devices[] __initdata = {
412 	&pxa27x_device_udc,
413 	&pxa_device_pmu,
414 	&pxa_device_i2s,
415 	&pxa_device_asoc_ssp1,
416 	&pxa_device_asoc_ssp2,
417 	&pxa_device_asoc_ssp3,
418 	&pxa_device_asoc_ssp4,
419 	&pxa_device_asoc_platform,
420 	&sa1100_device_rtc,
421 	&pxa_device_rtc,
422 	&pxa27x_device_ssp1,
423 	&pxa27x_device_ssp2,
424 	&pxa27x_device_ssp3,
425 	&pxa3xx_device_ssp4,
426 	&pxa27x_device_pwm0,
427 	&pxa27x_device_pwm1,
428 };
429 
430 static int __init pxa3xx_init(void)
431 {
432 	int ret = 0;
433 
434 	if (cpu_is_pxa3xx()) {
435 
436 		reset_status = ARSR;
437 
438 		/*
439 		 * clear RDH bit every time after reset
440 		 *
441 		 * Note: the last 3 bits DxS are write-1-to-clear so carefully
442 		 * preserve them here in case they will be referenced later
443 		 */
444 		ASCR &= ~(ASCR_RDH | ASCR_D1S | ASCR_D2S | ASCR_D3S);
445 
446 		clkdev_add_table(pxa3xx_clkregs, ARRAY_SIZE(pxa3xx_clkregs));
447 
448 		if ((ret = pxa_init_dma(IRQ_DMA, 32)))
449 			return ret;
450 
451 		pxa3xx_init_pm();
452 
453 		register_syscore_ops(&pxa_irq_syscore_ops);
454 		register_syscore_ops(&pxa3xx_mfp_syscore_ops);
455 		register_syscore_ops(&pxa_gpio_syscore_ops);
456 		register_syscore_ops(&pxa3xx_clock_syscore_ops);
457 
458 		ret = platform_add_devices(devices, ARRAY_SIZE(devices));
459 	}
460 
461 	return ret;
462 }
463 
464 postcore_initcall(pxa3xx_init);
465