common.c (cb54b53adae70701bdd77d848cea4b9b39b61cf9) common.c (4ca2c04085a1caa903e92a5fc0da25362150aac2)
1/*
2 * arch/arm/mach-orion5x/common.c
3 *
4 * Core functions for Marvell Orion 5x SoCs
5 *
6 * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
7 *
8 * This file is licensed under the terms of the GNU General Public

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169 IRQ_ORION5X_XOR0, IRQ_ORION5X_XOR1);
170}
171
172/*****************************************************************************
173 * Cryptographic Engines and Security Accelerator (CESA)
174 ****************************************************************************/
175static void __init orion5x_crypto_init(void)
176{
1/*
2 * arch/arm/mach-orion5x/common.c
3 *
4 * Core functions for Marvell Orion 5x SoCs
5 *
6 * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
7 *
8 * This file is licensed under the terms of the GNU General Public

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169 IRQ_ORION5X_XOR0, IRQ_ORION5X_XOR1);
170}
171
172/*****************************************************************************
173 * Cryptographic Engines and Security Accelerator (CESA)
174 ****************************************************************************/
175static void __init orion5x_crypto_init(void)
176{
177 mvebu_mbus_add_window("sram", ORION5X_SRAM_PHYS_BASE,
178 ORION5X_SRAM_SIZE);
177 mvebu_mbus_add_window_by_id(ORION_MBUS_SRAM_TARGET,
178 ORION_MBUS_SRAM_ATTR,
179 ORION5X_SRAM_PHYS_BASE,
180 ORION5X_SRAM_SIZE);
179 orion_crypto_init(ORION5X_CRYPTO_PHYS_BASE, ORION5X_SRAM_PHYS_BASE,
180 SZ_8K, IRQ_ORION5X_CESA);
181}
182
183/*****************************************************************************
184 * Watchdog
185 ****************************************************************************/
186void __init orion5x_wdt_init(void)

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217}
218
219void orion5x_setup_wins(void)
220{
221 /*
222 * The PCIe windows will no longer be statically allocated
223 * here once Orion5x is migrated to the pci-mvebu driver.
224 */
181 orion_crypto_init(ORION5X_CRYPTO_PHYS_BASE, ORION5X_SRAM_PHYS_BASE,
182 SZ_8K, IRQ_ORION5X_CESA);
183}
184
185/*****************************************************************************
186 * Watchdog
187 ****************************************************************************/
188void __init orion5x_wdt_init(void)

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219}
220
221void orion5x_setup_wins(void)
222{
223 /*
224 * The PCIe windows will no longer be statically allocated
225 * here once Orion5x is migrated to the pci-mvebu driver.
226 */
225 mvebu_mbus_add_window_remap_flags("pcie0.0", ORION5X_PCIE_IO_PHYS_BASE,
227 mvebu_mbus_add_window_remap_by_id(ORION_MBUS_PCIE_IO_TARGET,
228 ORION_MBUS_PCIE_IO_ATTR,
229 ORION5X_PCIE_IO_PHYS_BASE,
226 ORION5X_PCIE_IO_SIZE,
230 ORION5X_PCIE_IO_SIZE,
227 ORION5X_PCIE_IO_BUS_BASE,
228 MVEBU_MBUS_PCI_IO);
229 mvebu_mbus_add_window_remap_flags("pcie0.0", ORION5X_PCIE_MEM_PHYS_BASE,
230 ORION5X_PCIE_MEM_SIZE,
231 MVEBU_MBUS_NO_REMAP,
232 MVEBU_MBUS_PCI_MEM);
233 mvebu_mbus_add_window_remap_flags("pci0.0", ORION5X_PCI_IO_PHYS_BASE,
231 ORION5X_PCIE_IO_BUS_BASE);
232 mvebu_mbus_add_window_by_id(ORION_MBUS_PCIE_MEM_TARGET,
233 ORION_MBUS_PCIE_MEM_ATTR,
234 ORION5X_PCIE_MEM_PHYS_BASE,
235 ORION5X_PCIE_MEM_SIZE);
236 mvebu_mbus_add_window_remap_by_id(ORION_MBUS_PCI_IO_TARGET,
237 ORION_MBUS_PCI_IO_ATTR,
238 ORION5X_PCI_IO_PHYS_BASE,
234 ORION5X_PCI_IO_SIZE,
239 ORION5X_PCI_IO_SIZE,
235 ORION5X_PCI_IO_BUS_BASE,
236 MVEBU_MBUS_PCI_IO);
237 mvebu_mbus_add_window_remap_flags("pci0.0", ORION5X_PCI_MEM_PHYS_BASE,
238 ORION5X_PCI_MEM_SIZE,
239 MVEBU_MBUS_NO_REMAP,
240 MVEBU_MBUS_PCI_MEM);
240 ORION5X_PCI_IO_BUS_BASE);
241 mvebu_mbus_add_window_by_id(ORION_MBUS_PCI_MEM_TARGET,
242 ORION_MBUS_PCI_MEM_ATTR,
243 ORION5X_PCI_MEM_PHYS_BASE,
244 ORION5X_PCI_MEM_SIZE);
241}
242
243int orion5x_tclk;
244
245int __init orion5x_find_tclk(void)
246{
247 u32 dev, rev;
248

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246
247int orion5x_tclk;
248
249int __init orion5x_find_tclk(void)
250{
251 u32 dev, rev;
252

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