1 /* 2 * arch/arm/mach-orion5x/common.c 3 * 4 * Core functions for Marvell Orion 5x SoCs 5 * 6 * Maintainer: Tzachi Perelstein <tzachi@marvell.com> 7 * 8 * This file is licensed under the terms of the GNU General Public 9 * License version 2. This program is licensed "as is" without any 10 * warranty of any kind, whether express or implied. 11 */ 12 13 #include <linux/kernel.h> 14 #include <linux/init.h> 15 #include <linux/platform_device.h> 16 #include <linux/dma-mapping.h> 17 #include <linux/serial_8250.h> 18 #include <linux/mv643xx_i2c.h> 19 #include <linux/ata_platform.h> 20 #include <linux/delay.h> 21 #include <linux/clk-provider.h> 22 #include <linux/cpu.h> 23 #include <net/dsa.h> 24 #include <asm/page.h> 25 #include <asm/setup.h> 26 #include <asm/system_misc.h> 27 #include <asm/timex.h> 28 #include <asm/mach/arch.h> 29 #include <asm/mach/map.h> 30 #include <asm/mach/time.h> 31 #include <mach/bridge-regs.h> 32 #include <mach/hardware.h> 33 #include <mach/orion5x.h> 34 #include <linux/platform_data/mtd-orion_nand.h> 35 #include <linux/platform_data/usb-ehci-orion.h> 36 #include <plat/time.h> 37 #include <plat/common.h> 38 #include "common.h" 39 40 /***************************************************************************** 41 * I/O Address Mapping 42 ****************************************************************************/ 43 static struct map_desc orion5x_io_desc[] __initdata = { 44 { 45 .virtual = (unsigned long) ORION5X_REGS_VIRT_BASE, 46 .pfn = __phys_to_pfn(ORION5X_REGS_PHYS_BASE), 47 .length = ORION5X_REGS_SIZE, 48 .type = MT_DEVICE, 49 }, { 50 .virtual = (unsigned long) ORION5X_PCIE_WA_VIRT_BASE, 51 .pfn = __phys_to_pfn(ORION5X_PCIE_WA_PHYS_BASE), 52 .length = ORION5X_PCIE_WA_SIZE, 53 .type = MT_DEVICE, 54 }, 55 }; 56 57 void __init orion5x_map_io(void) 58 { 59 iotable_init(orion5x_io_desc, ARRAY_SIZE(orion5x_io_desc)); 60 } 61 62 63 /***************************************************************************** 64 * CLK tree 65 ****************************************************************************/ 66 static struct clk *tclk; 67 68 void __init clk_init(void) 69 { 70 tclk = clk_register_fixed_rate(NULL, "tclk", NULL, CLK_IS_ROOT, 71 orion5x_tclk); 72 73 orion_clkdev_init(tclk); 74 } 75 76 /***************************************************************************** 77 * EHCI0 78 ****************************************************************************/ 79 void __init orion5x_ehci0_init(void) 80 { 81 orion_ehci_init(ORION5X_USB0_PHYS_BASE, IRQ_ORION5X_USB0_CTRL, 82 EHCI_PHY_ORION); 83 } 84 85 86 /***************************************************************************** 87 * EHCI1 88 ****************************************************************************/ 89 void __init orion5x_ehci1_init(void) 90 { 91 orion_ehci_1_init(ORION5X_USB1_PHYS_BASE, IRQ_ORION5X_USB1_CTRL); 92 } 93 94 95 /***************************************************************************** 96 * GE00 97 ****************************************************************************/ 98 void __init orion5x_eth_init(struct mv643xx_eth_platform_data *eth_data) 99 { 100 orion_ge00_init(eth_data, 101 ORION5X_ETH_PHYS_BASE, IRQ_ORION5X_ETH_SUM, 102 IRQ_ORION5X_ETH_ERR, 103 MV643XX_TX_CSUM_DEFAULT_LIMIT); 104 } 105 106 107 /***************************************************************************** 108 * Ethernet switch 109 ****************************************************************************/ 110 void __init orion5x_eth_switch_init(struct dsa_platform_data *d, int irq) 111 { 112 orion_ge00_switch_init(d, irq); 113 } 114 115 116 /***************************************************************************** 117 * I2C 118 ****************************************************************************/ 119 void __init orion5x_i2c_init(void) 120 { 121 orion_i2c_init(I2C_PHYS_BASE, IRQ_ORION5X_I2C, 8); 122 123 } 124 125 126 /***************************************************************************** 127 * SATA 128 ****************************************************************************/ 129 void __init orion5x_sata_init(struct mv_sata_platform_data *sata_data) 130 { 131 orion_sata_init(sata_data, ORION5X_SATA_PHYS_BASE, IRQ_ORION5X_SATA); 132 } 133 134 135 /***************************************************************************** 136 * SPI 137 ****************************************************************************/ 138 void __init orion5x_spi_init() 139 { 140 orion_spi_init(SPI_PHYS_BASE); 141 } 142 143 144 /***************************************************************************** 145 * UART0 146 ****************************************************************************/ 147 void __init orion5x_uart0_init(void) 148 { 149 orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE, 150 IRQ_ORION5X_UART0, tclk); 151 } 152 153 /***************************************************************************** 154 * UART1 155 ****************************************************************************/ 156 void __init orion5x_uart1_init(void) 157 { 158 orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE, 159 IRQ_ORION5X_UART1, tclk); 160 } 161 162 /***************************************************************************** 163 * XOR engine 164 ****************************************************************************/ 165 void __init orion5x_xor_init(void) 166 { 167 orion_xor0_init(ORION5X_XOR_PHYS_BASE, 168 ORION5X_XOR_PHYS_BASE + 0x200, 169 IRQ_ORION5X_XOR0, IRQ_ORION5X_XOR1); 170 } 171 172 /***************************************************************************** 173 * Cryptographic Engines and Security Accelerator (CESA) 174 ****************************************************************************/ 175 static void __init orion5x_crypto_init(void) 176 { 177 mvebu_mbus_add_window_by_id(ORION_MBUS_SRAM_TARGET, 178 ORION_MBUS_SRAM_ATTR, 179 ORION5X_SRAM_PHYS_BASE, 180 ORION5X_SRAM_SIZE); 181 orion_crypto_init(ORION5X_CRYPTO_PHYS_BASE, ORION5X_SRAM_PHYS_BASE, 182 SZ_8K, IRQ_ORION5X_CESA); 183 } 184 185 /***************************************************************************** 186 * Watchdog 187 ****************************************************************************/ 188 void __init orion5x_wdt_init(void) 189 { 190 orion_wdt_init(); 191 } 192 193 194 /***************************************************************************** 195 * Time handling 196 ****************************************************************************/ 197 void __init orion5x_init_early(void) 198 { 199 u32 rev, dev; 200 const char *mbus_soc_name; 201 202 orion_time_set_base(TIMER_VIRT_BASE); 203 204 /* Initialize the MBUS driver */ 205 orion5x_pcie_id(&dev, &rev); 206 if (dev == MV88F5281_DEV_ID) 207 mbus_soc_name = "marvell,orion5x-88f5281-mbus"; 208 else if (dev == MV88F5182_DEV_ID) 209 mbus_soc_name = "marvell,orion5x-88f5182-mbus"; 210 else if (dev == MV88F5181_DEV_ID) 211 mbus_soc_name = "marvell,orion5x-88f5181-mbus"; 212 else if (dev == MV88F6183_DEV_ID) 213 mbus_soc_name = "marvell,orion5x-88f6183-mbus"; 214 else 215 mbus_soc_name = NULL; 216 mvebu_mbus_init(mbus_soc_name, ORION5X_BRIDGE_WINS_BASE, 217 ORION5X_BRIDGE_WINS_SZ, 218 ORION5X_DDR_WINS_BASE, ORION5X_DDR_WINS_SZ); 219 } 220 221 void orion5x_setup_wins(void) 222 { 223 /* 224 * The PCIe windows will no longer be statically allocated 225 * here once Orion5x is migrated to the pci-mvebu driver. 226 */ 227 mvebu_mbus_add_window_remap_by_id(ORION_MBUS_PCIE_IO_TARGET, 228 ORION_MBUS_PCIE_IO_ATTR, 229 ORION5X_PCIE_IO_PHYS_BASE, 230 ORION5X_PCIE_IO_SIZE, 231 ORION5X_PCIE_IO_BUS_BASE); 232 mvebu_mbus_add_window_by_id(ORION_MBUS_PCIE_MEM_TARGET, 233 ORION_MBUS_PCIE_MEM_ATTR, 234 ORION5X_PCIE_MEM_PHYS_BASE, 235 ORION5X_PCIE_MEM_SIZE); 236 mvebu_mbus_add_window_remap_by_id(ORION_MBUS_PCI_IO_TARGET, 237 ORION_MBUS_PCI_IO_ATTR, 238 ORION5X_PCI_IO_PHYS_BASE, 239 ORION5X_PCI_IO_SIZE, 240 ORION5X_PCI_IO_BUS_BASE); 241 mvebu_mbus_add_window_by_id(ORION_MBUS_PCI_MEM_TARGET, 242 ORION_MBUS_PCI_MEM_ATTR, 243 ORION5X_PCI_MEM_PHYS_BASE, 244 ORION5X_PCI_MEM_SIZE); 245 } 246 247 int orion5x_tclk; 248 249 int __init orion5x_find_tclk(void) 250 { 251 u32 dev, rev; 252 253 orion5x_pcie_id(&dev, &rev); 254 if (dev == MV88F6183_DEV_ID && 255 (readl(MPP_RESET_SAMPLE) & 0x00000200) == 0) 256 return 133333333; 257 258 return 166666667; 259 } 260 261 void __init orion5x_timer_init(void) 262 { 263 orion5x_tclk = orion5x_find_tclk(); 264 265 orion_time_init(ORION5X_BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR, 266 IRQ_ORION5X_BRIDGE, orion5x_tclk); 267 } 268 269 270 /***************************************************************************** 271 * General 272 ****************************************************************************/ 273 /* 274 * Identify device ID and rev from PCIe configuration header space '0'. 275 */ 276 void __init orion5x_id(u32 *dev, u32 *rev, char **dev_name) 277 { 278 orion5x_pcie_id(dev, rev); 279 280 if (*dev == MV88F5281_DEV_ID) { 281 if (*rev == MV88F5281_REV_D2) { 282 *dev_name = "MV88F5281-D2"; 283 } else if (*rev == MV88F5281_REV_D1) { 284 *dev_name = "MV88F5281-D1"; 285 } else if (*rev == MV88F5281_REV_D0) { 286 *dev_name = "MV88F5281-D0"; 287 } else { 288 *dev_name = "MV88F5281-Rev-Unsupported"; 289 } 290 } else if (*dev == MV88F5182_DEV_ID) { 291 if (*rev == MV88F5182_REV_A2) { 292 *dev_name = "MV88F5182-A2"; 293 } else { 294 *dev_name = "MV88F5182-Rev-Unsupported"; 295 } 296 } else if (*dev == MV88F5181_DEV_ID) { 297 if (*rev == MV88F5181_REV_B1) { 298 *dev_name = "MV88F5181-Rev-B1"; 299 } else if (*rev == MV88F5181L_REV_A1) { 300 *dev_name = "MV88F5181L-Rev-A1"; 301 } else { 302 *dev_name = "MV88F5181(L)-Rev-Unsupported"; 303 } 304 } else if (*dev == MV88F6183_DEV_ID) { 305 if (*rev == MV88F6183_REV_B0) { 306 *dev_name = "MV88F6183-Rev-B0"; 307 } else { 308 *dev_name = "MV88F6183-Rev-Unsupported"; 309 } 310 } else { 311 *dev_name = "Device-Unknown"; 312 } 313 } 314 315 void __init orion5x_init(void) 316 { 317 char *dev_name; 318 u32 dev, rev; 319 320 orion5x_id(&dev, &rev, &dev_name); 321 printk(KERN_INFO "Orion ID: %s. TCLK=%d.\n", dev_name, orion5x_tclk); 322 323 /* 324 * Setup Orion address map 325 */ 326 orion5x_setup_wins(); 327 328 /* Setup root of clk tree */ 329 clk_init(); 330 331 /* 332 * Don't issue "Wait for Interrupt" instruction if we are 333 * running on D0 5281 silicon. 334 */ 335 if (dev == MV88F5281_DEV_ID && rev == MV88F5281_REV_D0) { 336 printk(KERN_INFO "Orion: Applying 5281 D0 WFI workaround.\n"); 337 cpu_idle_poll_ctrl(true); 338 } 339 340 /* 341 * The 5082/5181l/5182/6082/6082l/6183 have crypto 342 * while 5180n/5181/5281 don't have crypto. 343 */ 344 if ((dev == MV88F5181_DEV_ID && rev >= MV88F5181L_REV_A0) || 345 dev == MV88F5182_DEV_ID || dev == MV88F6183_DEV_ID) 346 orion5x_crypto_init(); 347 348 /* 349 * Register watchdog driver 350 */ 351 orion5x_wdt_init(); 352 } 353 354 void orion5x_restart(enum reboot_mode mode, const char *cmd) 355 { 356 /* 357 * Enable and issue soft reset 358 */ 359 orion5x_setbits(RSTOUTn_MASK, (1 << 2)); 360 orion5x_setbits(CPU_SOFT_RESET, 1); 361 mdelay(200); 362 orion5x_clrbits(CPU_SOFT_RESET, 1); 363 } 364 365 /* 366 * Many orion-based systems have buggy bootloader implementations. 367 * This is a common fixup for bogus memory tags. 368 */ 369 void __init tag_fixup_mem32(struct tag *t, char **from, 370 struct meminfo *meminfo) 371 { 372 for (; t->hdr.size; t = tag_next(t)) 373 if (t->hdr.tag == ATAG_MEM && 374 (!t->u.mem.size || t->u.mem.size & ~PAGE_MASK || 375 t->u.mem.start & ~PAGE_MASK)) { 376 printk(KERN_WARNING 377 "Clearing invalid memory bank %dKB@0x%08x\n", 378 t->u.mem.size / 1024, t->u.mem.start); 379 t->hdr.tag = 0; 380 } 381 } 382