cpuidle44xx.c (8407884dd9164ec18ed2afc00f56b87e36c51fcf) cpuidle44xx.c (dd3ad97c5621aa853843dd5e6783ca787466158c)
1/*
2 * OMAP4 CPU idle Routines
3 *
4 * Copyright (C) 2011 Texas Instruments, Inc.
5 * Santosh Shilimkar <santosh.shilimkar@ti.com>
6 * Rajendra Nayak <rnayak@ti.com>
7 *
8 * This program is free software; you can redistribute it and/or modify

--- 7 unchanged lines hidden (view full) ---

16#include <linux/export.h>
17#include <linux/clockchips.h>
18
19#include <asm/proc-fns.h>
20
21#include "common.h"
22#include "pm.h"
23#include "prm.h"
1/*
2 * OMAP4 CPU idle Routines
3 *
4 * Copyright (C) 2011 Texas Instruments, Inc.
5 * Santosh Shilimkar <santosh.shilimkar@ti.com>
6 * Rajendra Nayak <rnayak@ti.com>
7 *
8 * This program is free software; you can redistribute it and/or modify

--- 7 unchanged lines hidden (view full) ---

16#include <linux/export.h>
17#include <linux/clockchips.h>
18
19#include <asm/proc-fns.h>
20
21#include "common.h"
22#include "pm.h"
23#include "prm.h"
24#include "clockdomain.h"
24
25
26#ifdef CONFIG_CPU_IDLE
27
25/* Machine specific information */
26struct omap4_idle_statedata {
27 u32 cpu_state;
28 u32 mpu_logic_state;
29 u32 mpu_state;
30};
31
32static struct omap4_idle_statedata omap4_idle_data[] = {

--- 9 unchanged lines hidden (view full) ---

42 },
43 {
44 .cpu_state = PWRDM_POWER_OFF,
45 .mpu_state = PWRDM_POWER_RET,
46 .mpu_logic_state = PWRDM_POWER_OFF,
47 },
48};
49
28/* Machine specific information */
29struct omap4_idle_statedata {
30 u32 cpu_state;
31 u32 mpu_logic_state;
32 u32 mpu_state;
33};
34
35static struct omap4_idle_statedata omap4_idle_data[] = {

--- 9 unchanged lines hidden (view full) ---

45 },
46 {
47 .cpu_state = PWRDM_POWER_OFF,
48 .mpu_state = PWRDM_POWER_RET,
49 .mpu_logic_state = PWRDM_POWER_OFF,
50 },
51};
52
50static struct powerdomain *mpu_pd, *cpu0_pd, *cpu1_pd;
53static struct powerdomain *mpu_pd, *cpu_pd[NR_CPUS];
54static struct clockdomain *cpu_clkdm[NR_CPUS];
51
52/**
55
56/**
53 * omap4_enter_idle - Programs OMAP4 to enter the specified state
57 * omap4_enter_idle_coupled_[simple/coupled] - OMAP4 cpuidle entry functions
54 * @dev: cpuidle device
55 * @drv: cpuidle driver
56 * @index: the index of state to be entered
57 *
58 * Called from the CPUidle framework to program the device to the
59 * specified low power state selected by the governor.
60 * Returns the amount of time spent in the low power state.
61 */
58 * @dev: cpuidle device
59 * @drv: cpuidle driver
60 * @index: the index of state to be entered
61 *
62 * Called from the CPUidle framework to program the device to the
63 * specified low power state selected by the governor.
64 * Returns the amount of time spent in the low power state.
65 */
62static int omap4_enter_idle(struct cpuidle_device *dev,
66static int omap4_enter_idle_simple(struct cpuidle_device *dev,
63 struct cpuidle_driver *drv,
64 int index)
65{
67 struct cpuidle_driver *drv,
68 int index)
69{
70 local_fiq_disable();
71 omap_do_wfi();
72 local_fiq_enable();
73
74 return index;
75}
76
77static int omap4_enter_idle_coupled(struct cpuidle_device *dev,
78 struct cpuidle_driver *drv,
79 int index)
80{
66 struct omap4_idle_statedata *cx = &omap4_idle_data[index];
81 struct omap4_idle_statedata *cx = &omap4_idle_data[index];
67 u32 cpu1_state;
68 int cpu_id = smp_processor_id();
69
70 local_fiq_disable();
71
72 /*
82 int cpu_id = smp_processor_id();
83
84 local_fiq_disable();
85
86 /*
73 * CPU0 has to stay ON (i.e in C1) until CPU1 is OFF state.
87 * CPU0 has to wait and stay ON until CPU1 is OFF state.
74 * This is necessary to honour hardware recommondation
75 * of triggeing all the possible low power modes once CPU1 is
76 * out of coherency and in OFF mode.
88 * This is necessary to honour hardware recommondation
89 * of triggeing all the possible low power modes once CPU1 is
90 * out of coherency and in OFF mode.
77 * Update dev->last_state so that governor stats reflects right
78 * data.
79 */
91 */
80 cpu1_state = pwrdm_read_pwrst(cpu1_pd);
81 if (cpu1_state != PWRDM_POWER_OFF) {
82 index = drv->safe_state_index;
83 cx = &omap4_idle_data[index];
92 if (dev->cpu == 0 && cpumask_test_cpu(1, cpu_online_mask)) {
93 while (pwrdm_read_pwrst(cpu_pd[1]) != PWRDM_POWER_OFF)
94 cpu_relax();
84 }
85
95 }
96
86 if (index > 0)
87 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu_id);
97 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu_id);
88
89 /*
90 * Call idle CPU PM enter notifier chain so that
91 * VFP and per CPU interrupt context is saved.
92 */
98
99 /*
100 * Call idle CPU PM enter notifier chain so that
101 * VFP and per CPU interrupt context is saved.
102 */
93 if (cx->cpu_state == PWRDM_POWER_OFF)
94 cpu_pm_enter();
103 cpu_pm_enter();
95
104
96 pwrdm_set_logic_retst(mpu_pd, cx->mpu_logic_state);
97 omap_set_pwrdm_state(mpu_pd, cx->mpu_state);
105 if (dev->cpu == 0) {
106 pwrdm_set_logic_retst(mpu_pd, cx->mpu_logic_state);
107 omap_set_pwrdm_state(mpu_pd, cx->mpu_state);
98
108
99 /*
100 * Call idle CPU cluster PM enter notifier chain
101 * to save GIC and wakeupgen context.
102 */
103 if ((cx->mpu_state == PWRDM_POWER_RET) &&
104 (cx->mpu_logic_state == PWRDM_POWER_OFF))
105 cpu_cluster_pm_enter();
109 /*
110 * Call idle CPU cluster PM enter notifier chain
111 * to save GIC and wakeupgen context.
112 */
113 if ((cx->mpu_state == PWRDM_POWER_RET) &&
114 (cx->mpu_logic_state == PWRDM_POWER_OFF))
115 cpu_cluster_pm_enter();
116 }
106
107 omap4_enter_lowpower(dev->cpu, cx->cpu_state);
108
117
118 omap4_enter_lowpower(dev->cpu, cx->cpu_state);
119
120 /* Wakeup CPU1 only if it is not offlined */
121 if (dev->cpu == 0 && cpumask_test_cpu(1, cpu_online_mask)) {
122 clkdm_wakeup(cpu_clkdm[1]);
123 clkdm_allow_idle(cpu_clkdm[1]);
124 }
125
109 /*
110 * Call idle CPU PM exit notifier chain to restore
126 /*
127 * Call idle CPU PM exit notifier chain to restore
111 * VFP and per CPU IRQ context. Only CPU0 state is
112 * considered since CPU1 is managed by CPU hotplug.
128 * VFP and per CPU IRQ context.
113 */
129 */
114 if (pwrdm_read_prev_pwrst(cpu0_pd) == PWRDM_POWER_OFF)
115 cpu_pm_exit();
130 cpu_pm_exit();
116
117 /*
118 * Call idle CPU cluster PM exit notifier chain
119 * to restore GIC and wakeupgen context.
120 */
121 if (omap4_mpuss_read_prev_context_state())
122 cpu_cluster_pm_exit();
123
131
132 /*
133 * Call idle CPU cluster PM exit notifier chain
134 * to restore GIC and wakeupgen context.
135 */
136 if (omap4_mpuss_read_prev_context_state())
137 cpu_cluster_pm_exit();
138
124 if (index > 0)
125 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu_id);
139 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu_id);
126
127 local_fiq_enable();
128
129 return index;
130}
131
132DEFINE_PER_CPU(struct cpuidle_device, omap4_idle_dev);
133
134struct cpuidle_driver omap4_idle_driver = {
135 .name = "omap4_idle",
136 .owner = THIS_MODULE,
137 .en_core_tk_irqen = 1,
138 .states = {
139 {
140 /* C1 - CPU0 ON + CPU1 ON + MPU ON */
141 .exit_latency = 2 + 2,
142 .target_residency = 5,
143 .flags = CPUIDLE_FLAG_TIME_VALID,
140
141 local_fiq_enable();
142
143 return index;
144}
145
146DEFINE_PER_CPU(struct cpuidle_device, omap4_idle_dev);
147
148struct cpuidle_driver omap4_idle_driver = {
149 .name = "omap4_idle",
150 .owner = THIS_MODULE,
151 .en_core_tk_irqen = 1,
152 .states = {
153 {
154 /* C1 - CPU0 ON + CPU1 ON + MPU ON */
155 .exit_latency = 2 + 2,
156 .target_residency = 5,
157 .flags = CPUIDLE_FLAG_TIME_VALID,
144 .enter = omap4_enter_idle,
158 .enter = omap4_enter_idle_simple,
145 .name = "C1",
146 .desc = "MPUSS ON"
147 },
148 {
149 /* C2 - CPU0 OFF + CPU1 OFF + MPU CSWR */
150 .exit_latency = 328 + 440,
151 .target_residency = 960,
159 .name = "C1",
160 .desc = "MPUSS ON"
161 },
162 {
163 /* C2 - CPU0 OFF + CPU1 OFF + MPU CSWR */
164 .exit_latency = 328 + 440,
165 .target_residency = 960,
152 .flags = CPUIDLE_FLAG_TIME_VALID,
153 .enter = omap4_enter_idle,
166 .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_COUPLED,
167 .enter = omap4_enter_idle_coupled,
154 .name = "C2",
155 .desc = "MPUSS CSWR",
156 },
157 {
158 /* C3 - CPU0 OFF + CPU1 OFF + MPU OSWR */
159 .exit_latency = 460 + 518,
160 .target_residency = 1100,
168 .name = "C2",
169 .desc = "MPUSS CSWR",
170 },
171 {
172 /* C3 - CPU0 OFF + CPU1 OFF + MPU OSWR */
173 .exit_latency = 460 + 518,
174 .target_residency = 1100,
161 .flags = CPUIDLE_FLAG_TIME_VALID,
162 .enter = omap4_enter_idle,
175 .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_COUPLED,
176 .enter = omap4_enter_idle_coupled,
163 .name = "C3",
164 .desc = "MPUSS OSWR",
165 },
166 },
167 .state_count = ARRAY_SIZE(omap4_idle_data),
168 .safe_state_index = 0,
169};
170

--- 4 unchanged lines hidden (view full) ---

175 * framework with the valid set of states.
176 */
177int __init omap4_idle_init(void)
178{
179 struct cpuidle_device *dev;
180 unsigned int cpu_id = 0;
181
182 mpu_pd = pwrdm_lookup("mpu_pwrdm");
177 .name = "C3",
178 .desc = "MPUSS OSWR",
179 },
180 },
181 .state_count = ARRAY_SIZE(omap4_idle_data),
182 .safe_state_index = 0,
183};
184

--- 4 unchanged lines hidden (view full) ---

189 * framework with the valid set of states.
190 */
191int __init omap4_idle_init(void)
192{
193 struct cpuidle_device *dev;
194 unsigned int cpu_id = 0;
195
196 mpu_pd = pwrdm_lookup("mpu_pwrdm");
183 cpu0_pd = pwrdm_lookup("cpu0_pwrdm");
184 cpu1_pd = pwrdm_lookup("cpu1_pwrdm");
185 if ((!mpu_pd) || (!cpu0_pd) || (!cpu1_pd))
197 cpu_pd[0] = pwrdm_lookup("cpu0_pwrdm");
198 cpu_pd[1] = pwrdm_lookup("cpu1_pwrdm");
199 if ((!mpu_pd) || (!cpu_pd[0]) || (!cpu_pd[1]))
186 return -ENODEV;
187
200 return -ENODEV;
201
188 dev = &per_cpu(omap4_idle_dev, cpu_id);
189 dev->cpu = cpu_id;
202 cpu_clkdm[0] = clkdm_lookup("mpu0_clkdm");
203 cpu_clkdm[1] = clkdm_lookup("mpu1_clkdm");
204 if (!cpu_clkdm[0] || !cpu_clkdm[1])
205 return -ENODEV;
190
206
191 cpuidle_register_driver(&omap4_idle_driver);
207 for_each_cpu(cpu_id, cpu_online_mask) {
208 dev = &per_cpu(omap4_idle_dev, cpu_id);
209 dev->cpu = cpu_id;
210 dev->coupled_cpus = *cpu_online_mask;
192
211
193 if (cpuidle_register_device(dev)) {
194 pr_err("%s: CPUidle register device failed\n", __func__);
195 return -EIO;
212 cpuidle_register_driver(&omap4_idle_driver);
213
214 if (cpuidle_register_device(dev)) {
215 pr_err("%s: CPUidle register failed\n", __func__);
216 return -EIO;
217 }
196 }
197
198 return 0;
199}
218 }
219
220 return 0;
221}
222#else
223int __init omap4_idle_init(void)
224{
225 return 0;
226}
227#endif /* CONFIG_CPU_IDLE */