1 /* 2 * OMAP4 CPU idle Routines 3 * 4 * Copyright (C) 2011 Texas Instruments, Inc. 5 * Santosh Shilimkar <santosh.shilimkar@ti.com> 6 * Rajendra Nayak <rnayak@ti.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 */ 12 13 #include <linux/sched.h> 14 #include <linux/cpuidle.h> 15 #include <linux/cpu_pm.h> 16 #include <linux/export.h> 17 #include <linux/clockchips.h> 18 19 #include <asm/proc-fns.h> 20 21 #include "common.h" 22 #include "pm.h" 23 #include "prm.h" 24 25 /* Machine specific information */ 26 struct omap4_idle_statedata { 27 u32 cpu_state; 28 u32 mpu_logic_state; 29 u32 mpu_state; 30 }; 31 32 static struct omap4_idle_statedata omap4_idle_data[] = { 33 { 34 .cpu_state = PWRDM_POWER_ON, 35 .mpu_state = PWRDM_POWER_ON, 36 .mpu_logic_state = PWRDM_POWER_RET, 37 }, 38 { 39 .cpu_state = PWRDM_POWER_OFF, 40 .mpu_state = PWRDM_POWER_RET, 41 .mpu_logic_state = PWRDM_POWER_RET, 42 }, 43 { 44 .cpu_state = PWRDM_POWER_OFF, 45 .mpu_state = PWRDM_POWER_RET, 46 .mpu_logic_state = PWRDM_POWER_OFF, 47 }, 48 }; 49 50 static struct powerdomain *mpu_pd, *cpu0_pd, *cpu1_pd; 51 52 /** 53 * omap4_enter_idle - Programs OMAP4 to enter the specified state 54 * @dev: cpuidle device 55 * @drv: cpuidle driver 56 * @index: the index of state to be entered 57 * 58 * Called from the CPUidle framework to program the device to the 59 * specified low power state selected by the governor. 60 * Returns the amount of time spent in the low power state. 61 */ 62 static int omap4_enter_idle(struct cpuidle_device *dev, 63 struct cpuidle_driver *drv, 64 int index) 65 { 66 struct omap4_idle_statedata *cx = &omap4_idle_data[index]; 67 u32 cpu1_state; 68 int cpu_id = smp_processor_id(); 69 70 local_fiq_disable(); 71 72 /* 73 * CPU0 has to stay ON (i.e in C1) until CPU1 is OFF state. 74 * This is necessary to honour hardware recommondation 75 * of triggeing all the possible low power modes once CPU1 is 76 * out of coherency and in OFF mode. 77 * Update dev->last_state so that governor stats reflects right 78 * data. 79 */ 80 cpu1_state = pwrdm_read_pwrst(cpu1_pd); 81 if (cpu1_state != PWRDM_POWER_OFF) { 82 index = drv->safe_state_index; 83 cx = &omap4_idle_data[index]; 84 } 85 86 if (index > 0) 87 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu_id); 88 89 /* 90 * Call idle CPU PM enter notifier chain so that 91 * VFP and per CPU interrupt context is saved. 92 */ 93 if (cx->cpu_state == PWRDM_POWER_OFF) 94 cpu_pm_enter(); 95 96 pwrdm_set_logic_retst(mpu_pd, cx->mpu_logic_state); 97 omap_set_pwrdm_state(mpu_pd, cx->mpu_state); 98 99 /* 100 * Call idle CPU cluster PM enter notifier chain 101 * to save GIC and wakeupgen context. 102 */ 103 if ((cx->mpu_state == PWRDM_POWER_RET) && 104 (cx->mpu_logic_state == PWRDM_POWER_OFF)) 105 cpu_cluster_pm_enter(); 106 107 omap4_enter_lowpower(dev->cpu, cx->cpu_state); 108 109 /* 110 * Call idle CPU PM exit notifier chain to restore 111 * VFP and per CPU IRQ context. Only CPU0 state is 112 * considered since CPU1 is managed by CPU hotplug. 113 */ 114 if (pwrdm_read_prev_pwrst(cpu0_pd) == PWRDM_POWER_OFF) 115 cpu_pm_exit(); 116 117 /* 118 * Call idle CPU cluster PM exit notifier chain 119 * to restore GIC and wakeupgen context. 120 */ 121 if (omap4_mpuss_read_prev_context_state()) 122 cpu_cluster_pm_exit(); 123 124 if (index > 0) 125 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu_id); 126 127 local_fiq_enable(); 128 129 return index; 130 } 131 132 DEFINE_PER_CPU(struct cpuidle_device, omap4_idle_dev); 133 134 struct cpuidle_driver omap4_idle_driver = { 135 .name = "omap4_idle", 136 .owner = THIS_MODULE, 137 .en_core_tk_irqen = 1, 138 .states = { 139 { 140 /* C1 - CPU0 ON + CPU1 ON + MPU ON */ 141 .exit_latency = 2 + 2, 142 .target_residency = 5, 143 .flags = CPUIDLE_FLAG_TIME_VALID, 144 .enter = omap4_enter_idle, 145 .name = "C1", 146 .desc = "MPUSS ON" 147 }, 148 { 149 /* C2 - CPU0 OFF + CPU1 OFF + MPU CSWR */ 150 .exit_latency = 328 + 440, 151 .target_residency = 960, 152 .flags = CPUIDLE_FLAG_TIME_VALID, 153 .enter = omap4_enter_idle, 154 .name = "C2", 155 .desc = "MPUSS CSWR", 156 }, 157 { 158 /* C3 - CPU0 OFF + CPU1 OFF + MPU OSWR */ 159 .exit_latency = 460 + 518, 160 .target_residency = 1100, 161 .flags = CPUIDLE_FLAG_TIME_VALID, 162 .enter = omap4_enter_idle, 163 .name = "C3", 164 .desc = "MPUSS OSWR", 165 }, 166 }, 167 .state_count = ARRAY_SIZE(omap4_idle_data), 168 .safe_state_index = 0, 169 }; 170 171 /** 172 * omap4_idle_init - Init routine for OMAP4 idle 173 * 174 * Registers the OMAP4 specific cpuidle driver to the cpuidle 175 * framework with the valid set of states. 176 */ 177 int __init omap4_idle_init(void) 178 { 179 struct cpuidle_device *dev; 180 unsigned int cpu_id = 0; 181 182 mpu_pd = pwrdm_lookup("mpu_pwrdm"); 183 cpu0_pd = pwrdm_lookup("cpu0_pwrdm"); 184 cpu1_pd = pwrdm_lookup("cpu1_pwrdm"); 185 if ((!mpu_pd) || (!cpu0_pd) || (!cpu1_pd)) 186 return -ENODEV; 187 188 dev = &per_cpu(omap4_idle_dev, cpu_id); 189 dev->cpu = cpu_id; 190 191 cpuidle_register_driver(&omap4_idle_driver); 192 193 if (cpuidle_register_device(dev)) { 194 pr_err("%s: CPUidle register device failed\n", __func__); 195 return -EIO; 196 } 197 198 return 0; 199 } 200