| Kconfig (f746929ffdc8a83c0e6092343d4475f6485e13d3) | Kconfig (3fa609755c11fbe8770ede4d895ebb86fb7b9f1e) |
|---|---|
| 1menu "TI OMAP/AM/DM/DRA Family" 2 depends on ARCH_MULTI_V6 || ARCH_MULTI_V7 3 4config ARCH_OMAP2 5 bool "TI OMAP2" 6 depends on ARCH_MULTI_V6 7 select ARCH_OMAP2PLUS 8 select CPU_V6 --- 15 unchanged lines hidden (view full) --- 24 select ARCH_OMAP2PLUS 25 select ARCH_NEEDS_CPU_IDLE_COUPLED if SMP 26 select ARM_CPU_SUSPEND if PM 27 select ARM_ERRATA_720789 28 select ARM_GIC 29 select HAVE_ARM_SCU if SMP 30 select HAVE_ARM_TWD if SMP 31 select OMAP_INTERCONNECT | 1menu "TI OMAP/AM/DM/DRA Family" 2 depends on ARCH_MULTI_V6 || ARCH_MULTI_V7 3 4config ARCH_OMAP2 5 bool "TI OMAP2" 6 depends on ARCH_MULTI_V6 7 select ARCH_OMAP2PLUS 8 select CPU_V6 --- 15 unchanged lines hidden (view full) --- 24 select ARCH_OMAP2PLUS 25 select ARCH_NEEDS_CPU_IDLE_COUPLED if SMP 26 select ARM_CPU_SUSPEND if PM 27 select ARM_ERRATA_720789 28 select ARM_GIC 29 select HAVE_ARM_SCU if SMP 30 select HAVE_ARM_TWD if SMP 31 select OMAP_INTERCONNECT |
| 32 select OMAP_INTERCONNECT_BARRIER |
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| 32 select PL310_ERRATA_588369 if CACHE_L2X0 33 select PL310_ERRATA_727915 if CACHE_L2X0 34 select PM_OPP if PM 35 select PM if CPU_IDLE 36 select ARM_ERRATA_754322 37 select ARM_ERRATA_775420 38 39config SOC_OMAP5 40 bool "TI OMAP5" 41 depends on ARCH_MULTI_V7 42 select ARCH_OMAP2PLUS 43 select ARM_CPU_SUSPEND if PM 44 select ARM_GIC 45 select HAVE_ARM_SCU if SMP 46 select HAVE_ARM_TWD if SMP 47 select HAVE_ARM_ARCH_TIMER 48 select ARM_ERRATA_798181 if SMP | 33 select PL310_ERRATA_588369 if CACHE_L2X0 34 select PL310_ERRATA_727915 if CACHE_L2X0 35 select PM_OPP if PM 36 select PM if CPU_IDLE 37 select ARM_ERRATA_754322 38 select ARM_ERRATA_775420 39 40config SOC_OMAP5 41 bool "TI OMAP5" 42 depends on ARCH_MULTI_V7 43 select ARCH_OMAP2PLUS 44 select ARM_CPU_SUSPEND if PM 45 select ARM_GIC 46 select HAVE_ARM_SCU if SMP 47 select HAVE_ARM_TWD if SMP 48 select HAVE_ARM_ARCH_TIMER 49 select ARM_ERRATA_798181 if SMP |
| 50 select OMAP_INTERCONNECT_BARRIER |
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| 49 50config SOC_AM33XX 51 bool "TI AM33XX" 52 depends on ARCH_MULTI_V7 53 select ARCH_OMAP2PLUS 54 select ARM_CPU_SUSPEND if PM 55 56config SOC_AM43XX --- 8 unchanged lines hidden (view full) --- 65 bool "TI DRA7XX" 66 depends on ARCH_MULTI_V7 67 select ARCH_OMAP2PLUS 68 select ARM_CPU_SUSPEND if PM 69 select ARM_GIC 70 select HAVE_ARM_ARCH_TIMER 71 select IRQ_CROSSBAR 72 select ARM_ERRATA_798181 if SMP | 51 52config SOC_AM33XX 53 bool "TI AM33XX" 54 depends on ARCH_MULTI_V7 55 select ARCH_OMAP2PLUS 56 select ARM_CPU_SUSPEND if PM 57 58config SOC_AM43XX --- 8 unchanged lines hidden (view full) --- 67 bool "TI DRA7XX" 68 depends on ARCH_MULTI_V7 69 select ARCH_OMAP2PLUS 70 select ARM_CPU_SUSPEND if PM 71 select ARM_GIC 72 select HAVE_ARM_ARCH_TIMER 73 select IRQ_CROSSBAR 74 select ARM_ERRATA_798181 if SMP |
| 75 select OMAP_INTERCONNECT_BARRIER |
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| 73 74config ARCH_OMAP2PLUS 75 bool 76 select ARCH_HAS_BANDGAP 77 select ARCH_HAS_HOLES_MEMORYMODEL 78 select ARCH_OMAP 79 select ARCH_REQUIRE_GPIOLIB 80 select CLKSRC_MMIO --- 5 unchanged lines hidden (view full) --- 86 select OMAP_GPMC 87 select PINCTRL 88 select SOC_BUS 89 select TI_PRIV_EDMA 90 select OMAP_IRQCHIP 91 help 92 Systems based on OMAP2, OMAP3, OMAP4 or OMAP5 93 | 76 77config ARCH_OMAP2PLUS 78 bool 79 select ARCH_HAS_BANDGAP 80 select ARCH_HAS_HOLES_MEMORYMODEL 81 select ARCH_OMAP 82 select ARCH_REQUIRE_GPIOLIB 83 select CLKSRC_MMIO --- 5 unchanged lines hidden (view full) --- 89 select OMAP_GPMC 90 select PINCTRL 91 select SOC_BUS 92 select TI_PRIV_EDMA 93 select OMAP_IRQCHIP 94 help 95 Systems based on OMAP2, OMAP3, OMAP4 or OMAP5 96 |
| 97config OMAP_INTERCONNECT_BARRIER 98 bool 99 select ARM_HEAVY_MB 100 |
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| 94 95if ARCH_OMAP2PLUS 96 97menu "TI OMAP2/3/4 Specific Features" 98 99config ARCH_OMAP2PLUS_TYPICAL 100 bool "Typical OMAP configuration" 101 default y --- 133 unchanged lines hidden (view full) --- 235 help 236 If you know that none of your system initiators will attempt to 237 access SDRAM during CORE DVFS, select Y here. This should boost 238 SDRAM performance at lower CORE OPPs. There are relatively few 239 users who will wish to say yes at this point - almost everyone will 240 wish to say no. Selecting yes without understanding what is 241 going on could result in system crashes; 242 | 101 102if ARCH_OMAP2PLUS 103 104menu "TI OMAP2/3/4 Specific Features" 105 106config ARCH_OMAP2PLUS_TYPICAL 107 bool "Typical OMAP configuration" 108 default y --- 133 unchanged lines hidden (view full) --- 242 help 243 If you know that none of your system initiators will attempt to 244 access SDRAM during CORE DVFS, select Y here. This should boost 245 SDRAM performance at lower CORE OPPs. There are relatively few 246 users who will wish to say yes at this point - almost everyone will 247 wish to say no. Selecting yes without understanding what is 248 going on could result in system crashes; 249 |
| 243config OMAP4_ERRATA_I688 244 bool "OMAP4 errata: Async Bridge Corruption" 245 depends on (ARCH_OMAP4 || SOC_OMAP5) && !ARCH_MULTIPLATFORM 246 select ARCH_HAS_BARRIERS 247 help 248 If a data is stalled inside asynchronous bridge because of back 249 pressure, it may be accepted multiple times, creating pointer 250 misalignment that will corrupt next transfers on that data path 251 until next reset of the system (No recovery procedure once the 252 issue is hit, the path remains consistently broken). Async bridge 253 can be found on path between MPU to EMIF and MPU to L3 interconnect. 254 This situation can happen only when the idle is initiated by a 255 Master Request Disconnection (which is trigged by software when 256 executing WFI on CPU). 257 The work-around for this errata needs all the initiators connected 258 through async bridge must ensure that data path is properly drained 259 before issuing WFI. This condition will be met if one Strongly ordered 260 access is performed to the target right before executing the WFI. 261 In MPU case, L3 T2ASYNC FIFO and DDR T2ASYNC FIFO needs to be drained. 262 IO barrier ensure that there is no synchronisation loss on initiators 263 operating on both interconnect port simultaneously. | |
| 264endmenu 265 266endif 267 268endmenu | 250endmenu 251 252endif 253 254endmenu |