1menu "TI OMAP/AM/DM/DRA Family" 2 depends on ARCH_MULTI_V6 || ARCH_MULTI_V7 3 4config ARCH_OMAP2 5 bool "TI OMAP2" 6 depends on ARCH_MULTI_V6 7 select ARCH_OMAP2PLUS 8 select CPU_V6 9 select SOC_HAS_OMAP2_SDRC 10 11config ARCH_OMAP3 12 bool "TI OMAP3" 13 depends on ARCH_MULTI_V7 14 select ARCH_OMAP2PLUS 15 select ARM_CPU_SUSPEND if PM 16 select OMAP_INTERCONNECT 17 select PM_OPP if PM 18 select PM if CPU_IDLE 19 select SOC_HAS_OMAP2_SDRC 20 21config ARCH_OMAP4 22 bool "TI OMAP4" 23 depends on ARCH_MULTI_V7 24 select ARCH_OMAP2PLUS 25 select ARCH_NEEDS_CPU_IDLE_COUPLED if SMP 26 select ARM_CPU_SUSPEND if PM 27 select ARM_ERRATA_720789 28 select ARM_GIC 29 select HAVE_ARM_SCU if SMP 30 select HAVE_ARM_TWD if SMP 31 select OMAP_INTERCONNECT 32 select PL310_ERRATA_588369 if CACHE_L2X0 33 select PL310_ERRATA_727915 if CACHE_L2X0 34 select PM_OPP if PM 35 select PM if CPU_IDLE 36 select ARM_ERRATA_754322 37 select ARM_ERRATA_775420 38 39config SOC_OMAP5 40 bool "TI OMAP5" 41 depends on ARCH_MULTI_V7 42 select ARCH_OMAP2PLUS 43 select ARM_CPU_SUSPEND if PM 44 select ARM_GIC 45 select HAVE_ARM_SCU if SMP 46 select HAVE_ARM_TWD if SMP 47 select HAVE_ARM_ARCH_TIMER 48 select ARM_ERRATA_798181 if SMP 49 50config SOC_AM33XX 51 bool "TI AM33XX" 52 depends on ARCH_MULTI_V7 53 select ARCH_OMAP2PLUS 54 select ARM_CPU_SUSPEND if PM 55 56config SOC_AM43XX 57 bool "TI AM43x" 58 depends on ARCH_MULTI_V7 59 select ARCH_OMAP2PLUS 60 select ARM_GIC 61 select MACH_OMAP_GENERIC 62 select MIGHT_HAVE_CACHE_L2X0 63 64config SOC_DRA7XX 65 bool "TI DRA7XX" 66 depends on ARCH_MULTI_V7 67 select ARCH_OMAP2PLUS 68 select ARM_CPU_SUSPEND if PM 69 select ARM_GIC 70 select HAVE_ARM_ARCH_TIMER 71 select IRQ_CROSSBAR 72 select ARM_ERRATA_798181 if SMP 73 74config ARCH_OMAP2PLUS 75 bool 76 select ARCH_HAS_BANDGAP 77 select ARCH_HAS_HOLES_MEMORYMODEL 78 select ARCH_OMAP 79 select ARCH_REQUIRE_GPIOLIB 80 select CLKSRC_MMIO 81 select GENERIC_IRQ_CHIP 82 select MACH_OMAP_GENERIC 83 select MEMORY 84 select MFD_SYSCON 85 select OMAP_DM_TIMER 86 select OMAP_GPMC 87 select PINCTRL 88 select SOC_BUS 89 select TI_PRIV_EDMA 90 select OMAP_IRQCHIP 91 help 92 Systems based on OMAP2, OMAP3, OMAP4 or OMAP5 93 94 95if ARCH_OMAP2PLUS 96 97menu "TI OMAP2/3/4 Specific Features" 98 99config ARCH_OMAP2PLUS_TYPICAL 100 bool "Typical OMAP configuration" 101 default y 102 select AEABI 103 select HIGHMEM 104 select I2C 105 select I2C_OMAP 106 select MENELAUS if ARCH_OMAP2 107 select NEON if CPU_V7 108 select PM 109 select REGULATOR 110 select TWL4030_CORE if ARCH_OMAP3 || ARCH_OMAP4 111 select TWL4030_POWER if ARCH_OMAP3 || ARCH_OMAP4 112 select VFP 113 help 114 Compile a kernel suitable for booting most boards 115 116config SOC_HAS_OMAP2_SDRC 117 bool "OMAP2 SDRAM Controller support" 118 119config SOC_HAS_REALTIME_COUNTER 120 bool "Real time free running counter" 121 depends on SOC_OMAP5 || SOC_DRA7XX 122 default y 123 124comment "OMAP Core Type" 125 depends on ARCH_OMAP2 126 127config SOC_OMAP2420 128 bool "OMAP2420 support" 129 depends on ARCH_OMAP2 130 default y 131 select OMAP_DM_TIMER 132 select SOC_HAS_OMAP2_SDRC 133 134config SOC_OMAP2430 135 bool "OMAP2430 support" 136 depends on ARCH_OMAP2 137 default y 138 select SOC_HAS_OMAP2_SDRC 139 140config SOC_OMAP3430 141 bool "OMAP3430 support" 142 depends on ARCH_OMAP3 143 default y 144 select SOC_HAS_OMAP2_SDRC 145 146config SOC_TI81XX 147 bool "TI81XX support" 148 depends on ARCH_OMAP3 149 default y 150 151config OMAP_PACKAGE_CBC 152 bool 153 154config OMAP_PACKAGE_CBB 155 bool 156 157config OMAP_PACKAGE_CUS 158 bool 159 160config OMAP_PACKAGE_CBP 161 bool 162 163comment "OMAP Legacy Platform Data Board Type" 164 depends on ARCH_OMAP2PLUS 165 166config MACH_OMAP_GENERIC 167 bool 168 169config MACH_OMAP2_TUSB6010 170 bool 171 depends on ARCH_OMAP2 && SOC_OMAP2420 172 default y if MACH_NOKIA_N8X0 173 174config MACH_OMAP_LDP 175 bool "OMAP3 LDP board" 176 depends on ARCH_OMAP3 177 default y 178 select OMAP_PACKAGE_CBB 179 180config MACH_OMAP3530_LV_SOM 181 bool "OMAP3 Logic 3530 LV SOM board" 182 depends on ARCH_OMAP3 183 default y 184 select OMAP_PACKAGE_CBB 185 help 186 Support for the LogicPD OMAP3530 SOM Development kit 187 for full description please see the products webpage at 188 http://www.logicpd.com/products/development-kits/texas-instruments-zoom%E2%84%A2-omap35x-development-kit 189 190config MACH_OMAP3_TORPEDO 191 bool "OMAP3 Logic 35x Torpedo board" 192 depends on ARCH_OMAP3 193 default y 194 select OMAP_PACKAGE_CBB 195 help 196 Support for the LogicPD OMAP35x Torpedo Development kit 197 for full description please see the products webpage at 198 http://www.logicpd.com/products/development-kits/zoom-omap35x-torpedo-development-kit 199 200config MACH_OMAP3517EVM 201 bool "OMAP3517/ AM3517 EVM board" 202 depends on ARCH_OMAP3 203 default y 204 205config MACH_OMAP3_PANDORA 206 bool "OMAP3 Pandora" 207 depends on ARCH_OMAP3 208 default y 209 select OMAP_PACKAGE_CBB 210 select REGULATOR_FIXED_VOLTAGE if REGULATOR 211 212config MACH_NOKIA_N810 213 bool 214 215config MACH_NOKIA_N810_WIMAX 216 bool 217 218config MACH_NOKIA_N8X0 219 bool "Nokia N800/N810" 220 depends on SOC_OMAP2420 221 default y 222 select MACH_NOKIA_N810 223 select MACH_NOKIA_N810_WIMAX 224 225config MACH_NOKIA_RX51 226 bool "Nokia N900 (RX-51) phone" 227 depends on ARCH_OMAP3 228 default y 229 select OMAP_PACKAGE_CBB 230 231config OMAP3_SDRC_AC_TIMING 232 bool "Enable SDRC AC timing register changes" 233 depends on ARCH_OMAP3 234 default n 235 help 236 If you know that none of your system initiators will attempt to 237 access SDRAM during CORE DVFS, select Y here. This should boost 238 SDRAM performance at lower CORE OPPs. There are relatively few 239 users who will wish to say yes at this point - almost everyone will 240 wish to say no. Selecting yes without understanding what is 241 going on could result in system crashes; 242 243config OMAP4_ERRATA_I688 244 bool "OMAP4 errata: Async Bridge Corruption" 245 depends on (ARCH_OMAP4 || SOC_OMAP5) && !ARCH_MULTIPLATFORM 246 select ARCH_HAS_BARRIERS 247 help 248 If a data is stalled inside asynchronous bridge because of back 249 pressure, it may be accepted multiple times, creating pointer 250 misalignment that will corrupt next transfers on that data path 251 until next reset of the system (No recovery procedure once the 252 issue is hit, the path remains consistently broken). Async bridge 253 can be found on path between MPU to EMIF and MPU to L3 interconnect. 254 This situation can happen only when the idle is initiated by a 255 Master Request Disconnection (which is trigged by software when 256 executing WFI on CPU). 257 The work-around for this errata needs all the initiators connected 258 through async bridge must ensure that data path is properly drained 259 before issuing WFI. This condition will be met if one Strongly ordered 260 access is performed to the target right before executing the WFI. 261 In MPU case, L3 T2ASYNC FIFO and DDR T2ASYNC FIFO needs to be drained. 262 IO barrier ensure that there is no synchronisation loss on initiators 263 operating on both interconnect port simultaneously. 264endmenu 265 266endif 267 268endmenu 269