rk3128.dtsi (9ca8b8f880f2ebfe87780d553ca73fd2825a8988) rk3128.dtsi (5ca860fb438bafdf8501567b320239ea99910748)
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * (C) Copyright 2017 Rockchip Electronics Co., Ltd
4 */
5
6#include <dt-bindings/clock/rk3128-cru.h>
7#include <dt-bindings/gpio/gpio.h>
8#include <dt-bindings/interrupt-controller/arm-gic.h>
9#include <dt-bindings/interrupt-controller/irq.h>
10#include <dt-bindings/pinctrl/rockchip.h>
11#include <dt-bindings/power/rk3128-power.h>
12
13/ {
14 compatible = "rockchip,rk3128";
15 interrupt-parent = <&gic>;
16 #address-cells = <1>;
17 #size-cells = <1>;
18
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * (C) Copyright 2017 Rockchip Electronics Co., Ltd
4 */
5
6#include <dt-bindings/clock/rk3128-cru.h>
7#include <dt-bindings/gpio/gpio.h>
8#include <dt-bindings/interrupt-controller/arm-gic.h>
9#include <dt-bindings/interrupt-controller/irq.h>
10#include <dt-bindings/pinctrl/rockchip.h>
11#include <dt-bindings/power/rk3128-power.h>
12
13/ {
14 compatible = "rockchip,rk3128";
15 interrupt-parent = <&gic>;
16 #address-cells = <1>;
17 #size-cells = <1>;
18
19 aliases {
20 gpio0 = &gpio0;
21 gpio1 = &gpio1;
22 gpio2 = &gpio2;
23 gpio3 = &gpio3;
24 };
25
19 arm-pmu {
20 compatible = "arm,cortex-a7-pmu";
21 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
22 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
23 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
24 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
25 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
26 };

--- 1116 unchanged lines hidden --- 		26 arm-pmu {
27 compatible = "arm,cortex-a7-pmu";
28 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
29 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
30 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
31 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
32 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
33 };

--- 1116 unchanged lines hidden ---