1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * (C) Copyright 2017 Rockchip Electronics Co., Ltd 4 */ 5 6#include <dt-bindings/clock/rk3128-cru.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include <dt-bindings/power/rk3128-power.h> 12 13/ { 14 compatible = "rockchip,rk3128"; 15 interrupt-parent = <&gic>; 16 #address-cells = <1>; 17 #size-cells = <1>; 18 19 aliases { 20 gpio0 = &gpio0; 21 gpio1 = &gpio1; 22 gpio2 = &gpio2; 23 gpio3 = &gpio3; 24 }; 25 26 arm-pmu { 27 compatible = "arm,cortex-a7-pmu"; 28 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 29 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 30 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 31 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 32 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 33 }; 34 35 cpus { 36 #address-cells = <1>; 37 #size-cells = <0>; 38 enable-method = "rockchip,rk3036-smp"; 39 40 cpu0: cpu@f00 { 41 device_type = "cpu"; 42 compatible = "arm,cortex-a7"; 43 reg = <0xf00>; 44 clock-latency = <40000>; 45 clocks = <&cru ARMCLK>; 46 resets = <&cru SRST_CORE0>; 47 operating-points-v2 = <&cpu_opp_table>; 48 #cooling-cells = <2>; /* min followed by max */ 49 }; 50 51 cpu1: cpu@f01 { 52 device_type = "cpu"; 53 compatible = "arm,cortex-a7"; 54 reg = <0xf01>; 55 resets = <&cru SRST_CORE1>; 56 operating-points-v2 = <&cpu_opp_table>; 57 }; 58 59 cpu2: cpu@f02 { 60 device_type = "cpu"; 61 compatible = "arm,cortex-a7"; 62 reg = <0xf02>; 63 resets = <&cru SRST_CORE2>; 64 operating-points-v2 = <&cpu_opp_table>; 65 }; 66 67 cpu3: cpu@f03 { 68 device_type = "cpu"; 69 compatible = "arm,cortex-a7"; 70 reg = <0xf03>; 71 resets = <&cru SRST_CORE3>; 72 operating-points-v2 = <&cpu_opp_table>; 73 }; 74 }; 75 76 cpu_opp_table: opp-table-0 { 77 compatible = "operating-points-v2"; 78 opp-shared; 79 80 opp-216000000 { 81 opp-hz = /bits/ 64 <216000000>; 82 opp-microvolt = <950000 950000 1325000>; 83 }; 84 opp-408000000 { 85 opp-hz = /bits/ 64 <408000000>; 86 opp-microvolt = <950000 950000 1325000>; 87 }; 88 opp-600000000 { 89 opp-hz = /bits/ 64 <600000000>; 90 opp-microvolt = <950000 950000 1325000>; 91 }; 92 opp-696000000 { 93 opp-hz = /bits/ 64 <696000000>; 94 opp-microvolt = <975000 975000 1325000>; 95 }; 96 opp-816000000 { 97 opp-hz = /bits/ 64 <816000000>; 98 opp-microvolt = <1075000 1075000 1325000>; 99 opp-suspend; 100 }; 101 opp-1008000000 { 102 opp-hz = /bits/ 64 <1008000000>; 103 opp-microvolt = <1200000 1200000 1325000>; 104 }; 105 opp-1200000000 { 106 opp-hz = /bits/ 64 <1200000000>; 107 opp-microvolt = <1325000 1325000 1325000>; 108 }; 109 }; 110 111 gpu_opp_table: opp-table-1 { 112 compatible = "operating-points-v2"; 113 114 opp-200000000 { 115 opp-hz = /bits/ 64 <200000000>; 116 opp-microvolt = <975000 975000 1250000>; 117 }; 118 opp-300000000 { 119 opp-hz = /bits/ 64 <300000000>; 120 opp-microvolt = <1050000 1050000 1250000>; 121 }; 122 opp-400000000 { 123 opp-hz = /bits/ 64 <400000000>; 124 opp-microvolt = <1150000 1150000 1250000>; 125 }; 126 opp-480000000 { 127 opp-hz = /bits/ 64 <480000000>; 128 opp-microvolt = <1250000 1250000 1250000>; 129 }; 130 }; 131 132 timer { 133 compatible = "arm,armv7-timer"; 134 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 135 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 136 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 137 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 138 arm,cpu-registers-not-fw-configured; 139 clock-frequency = <24000000>; 140 }; 141 142 xin24m: oscillator { 143 compatible = "fixed-clock"; 144 clock-frequency = <24000000>; 145 clock-output-names = "xin24m"; 146 #clock-cells = <0>; 147 }; 148 149 imem: sram@10080000 { 150 compatible = "mmio-sram"; 151 reg = <0x10080000 0x2000>; 152 #address-cells = <1>; 153 #size-cells = <1>; 154 ranges = <0 0x10080000 0x2000>; 155 156 smp-sram@0 { 157 compatible = "rockchip,rk3066-smp-sram"; 158 reg = <0x00 0x10>; 159 }; 160 }; 161 162 gpu: gpu@10090000 { 163 compatible = "rockchip,rk3128-mali", "arm,mali-400"; 164 reg = <0x10090000 0x10000>; 165 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 166 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 167 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 168 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 169 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 170 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 171 interrupt-names = "gp", 172 "gpmmu", 173 "pp0", 174 "ppmmu0", 175 "pp1", 176 "ppmmu1"; 177 clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>; 178 clock-names = "bus", "core"; 179 operating-points-v2 = <&gpu_opp_table>; 180 resets = <&cru SRST_GPU>; 181 power-domains = <&power RK3128_PD_GPU>; 182 status = "disabled"; 183 }; 184 185 pmu: syscon@100a0000 { 186 compatible = "rockchip,rk3128-pmu", "syscon", "simple-mfd"; 187 reg = <0x100a0000 0x1000>; 188 189 power: power-controller { 190 compatible = "rockchip,rk3128-power-controller"; 191 #power-domain-cells = <1>; 192 #address-cells = <1>; 193 #size-cells = <0>; 194 195 power-domain@RK3128_PD_VIO { 196 reg = <RK3128_PD_VIO>; 197 clocks = <&cru ACLK_CIF>, 198 <&cru HCLK_CIF>, 199 <&cru DCLK_EBC>, 200 <&cru HCLK_EBC>, 201 <&cru ACLK_IEP>, 202 <&cru HCLK_IEP>, 203 <&cru ACLK_LCDC0>, 204 <&cru HCLK_LCDC0>, 205 <&cru PCLK_MIPI>, 206 <&cru ACLK_RGA>, 207 <&cru HCLK_RGA>, 208 <&cru ACLK_VIO0>, 209 <&cru ACLK_VIO1>, 210 <&cru HCLK_VIO>, 211 <&cru HCLK_VIO_H2P>, 212 <&cru DCLK_VOP>, 213 <&cru SCLK_VOP>; 214 pm_qos = <&qos_ebc>, 215 <&qos_iep>, 216 <&qos_lcdc>, 217 <&qos_rga>, 218 <&qos_vip>; 219 #power-domain-cells = <0>; 220 }; 221 222 power-domain@RK3128_PD_VIDEO { 223 reg = <RK3128_PD_VIDEO>; 224 clocks = <&cru ACLK_VDPU>, 225 <&cru HCLK_VDPU>, 226 <&cru ACLK_VEPU>, 227 <&cru HCLK_VEPU>, 228 <&cru SCLK_HEVC_CORE>; 229 pm_qos = <&qos_vpu>; 230 #power-domain-cells = <0>; 231 }; 232 233 power-domain@RK3128_PD_GPU { 234 reg = <RK3128_PD_GPU>; 235 clocks = <&cru ACLK_GPU>; 236 pm_qos = <&qos_gpu>; 237 #power-domain-cells = <0>; 238 }; 239 }; 240 }; 241 242 qos_gpu: qos@1012d000 { 243 compatible = "rockchip,rk3128-qos", "syscon"; 244 reg = <0x1012d000 0x20>; 245 }; 246 247 qos_vpu: qos@1012e000 { 248 compatible = "rockchip,rk3128-qos", "syscon"; 249 reg = <0x1012e000 0x20>; 250 }; 251 252 qos_rga: qos@1012f000 { 253 compatible = "rockchip,rk3128-qos", "syscon"; 254 reg = <0x1012f000 0x20>; 255 }; 256 257 qos_ebc: qos@1012f080 { 258 compatible = "rockchip,rk3128-qos", "syscon"; 259 reg = <0x1012f080 0x20>; 260 }; 261 262 qos_iep: qos@1012f100 { 263 compatible = "rockchip,rk3128-qos", "syscon"; 264 reg = <0x1012f100 0x20>; 265 }; 266 267 qos_lcdc: qos@1012f180 { 268 compatible = "rockchip,rk3128-qos", "syscon"; 269 reg = <0x1012f180 0x20>; 270 }; 271 272 qos_vip: qos@1012f200 { 273 compatible = "rockchip,rk3128-qos", "syscon"; 274 reg = <0x1012f200 0x20>; 275 }; 276 277 gic: interrupt-controller@10139000 { 278 compatible = "arm,cortex-a7-gic"; 279 reg = <0x10139000 0x1000>, 280 <0x1013a000 0x1000>, 281 <0x1013c000 0x2000>, 282 <0x1013e000 0x2000>; 283 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 284 interrupt-controller; 285 #interrupt-cells = <3>; 286 #address-cells = <0>; 287 }; 288 289 usb_otg: usb@10180000 { 290 compatible = "rockchip,rk3128-usb", "rockchip,rk3066-usb", "snps,dwc2"; 291 reg = <0x10180000 0x40000>; 292 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 293 clocks = <&cru HCLK_OTG>; 294 clock-names = "otg"; 295 dr_mode = "otg"; 296 g-np-tx-fifo-size = <16>; 297 g-rx-fifo-size = <280>; 298 g-tx-fifo-size = <256 128 128 64 32 16>; 299 phys = <&usb2phy_otg>; 300 phy-names = "usb2-phy"; 301 status = "disabled"; 302 }; 303 304 usb_host_ehci: usb@101c0000 { 305 compatible = "generic-ehci"; 306 reg = <0x101c0000 0x20000>; 307 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 308 clocks = <&cru HCLK_HOST2>; 309 phys = <&usb2phy_host>; 310 phy-names = "usb"; 311 status = "disabled"; 312 }; 313 314 usb_host_ohci: usb@101e0000 { 315 compatible = "generic-ohci"; 316 reg = <0x101e0000 0x20000>; 317 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 318 clocks = <&cru HCLK_HOST2>; 319 phys = <&usb2phy_host>; 320 phy-names = "usb"; 321 status = "disabled"; 322 }; 323 324 sdmmc: mmc@10214000 { 325 compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc"; 326 reg = <0x10214000 0x4000>; 327 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 328 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 329 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 330 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 331 dmas = <&pdma 10>; 332 dma-names = "rx-tx"; 333 fifo-depth = <256>; 334 max-frequency = <150000000>; 335 resets = <&cru SRST_SDMMC>; 336 reset-names = "reset"; 337 status = "disabled"; 338 }; 339 340 sdio: mmc@10218000 { 341 compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc"; 342 reg = <0x10218000 0x4000>; 343 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 344 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 345 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 346 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 347 dmas = <&pdma 11>; 348 dma-names = "rx-tx"; 349 fifo-depth = <256>; 350 max-frequency = <150000000>; 351 resets = <&cru SRST_SDIO>; 352 reset-names = "reset"; 353 status = "disabled"; 354 }; 355 356 emmc: mmc@1021c000 { 357 compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc"; 358 reg = <0x1021c000 0x4000>; 359 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 360 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 361 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 362 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 363 dmas = <&pdma 12>; 364 dma-names = "rx-tx"; 365 fifo-depth = <256>; 366 max-frequency = <150000000>; 367 resets = <&cru SRST_EMMC>; 368 reset-names = "reset"; 369 status = "disabled"; 370 }; 371 372 nfc: nand-controller@10500000 { 373 compatible = "rockchip,rk3128-nfc", "rockchip,rk2928-nfc"; 374 reg = <0x10500000 0x4000>; 375 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 376 clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>; 377 clock-names = "ahb", "nfc"; 378 pinctrl-names = "default"; 379 pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_cs0 380 &flash_dqs &flash_rdn &flash_rdy &flash_wrn>; 381 status = "disabled"; 382 }; 383 384 cru: clock-controller@20000000 { 385 compatible = "rockchip,rk3128-cru"; 386 reg = <0x20000000 0x1000>; 387 clocks = <&xin24m>; 388 clock-names = "xin24m"; 389 rockchip,grf = <&grf>; 390 #clock-cells = <1>; 391 #reset-cells = <1>; 392 assigned-clocks = <&cru PLL_GPLL>; 393 assigned-clock-rates = <594000000>; 394 }; 395 396 grf: syscon@20008000 { 397 compatible = "rockchip,rk3128-grf", "syscon", "simple-mfd"; 398 reg = <0x20008000 0x1000>; 399 #address-cells = <1>; 400 #size-cells = <1>; 401 402 usb2phy: usb2phy@17c { 403 compatible = "rockchip,rk3128-usb2phy"; 404 reg = <0x017c 0x0c>; 405 clocks = <&cru SCLK_OTGPHY0>; 406 clock-names = "phyclk"; 407 clock-output-names = "usb480m_phy"; 408 assigned-clocks = <&cru SCLK_USB480M>; 409 assigned-clock-parents = <&usb2phy>; 410 #clock-cells = <0>; 411 status = "disabled"; 412 413 usb2phy_host: host-port { 414 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 415 interrupt-names = "linestate"; 416 #phy-cells = <0>; 417 status = "disabled"; 418 }; 419 420 usb2phy_otg: otg-port { 421 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 422 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 423 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 424 interrupt-names = "otg-bvalid", "otg-id", 425 "linestate"; 426 #phy-cells = <0>; 427 status = "disabled"; 428 }; 429 }; 430 }; 431 432 timer0: timer@20044000 { 433 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; 434 reg = <0x20044000 0x20>; 435 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 436 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER0>; 437 clock-names = "pclk", "timer"; 438 }; 439 440 timer1: timer@20044020 { 441 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; 442 reg = <0x20044020 0x20>; 443 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 444 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER1>; 445 clock-names = "pclk", "timer"; 446 }; 447 448 timer2: timer@20044040 { 449 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; 450 reg = <0x20044040 0x20>; 451 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 452 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER2>; 453 clock-names = "pclk", "timer"; 454 }; 455 456 timer3: timer@20044060 { 457 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; 458 reg = <0x20044060 0x20>; 459 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 460 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER3>; 461 clock-names = "pclk", "timer"; 462 }; 463 464 timer4: timer@20044080 { 465 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; 466 reg = <0x20044080 0x20>; 467 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 468 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER4>; 469 clock-names = "pclk", "timer"; 470 }; 471 472 timer5: timer@200440a0 { 473 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; 474 reg = <0x200440a0 0x20>; 475 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 476 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER5>; 477 clock-names = "pclk", "timer"; 478 }; 479 480 watchdog: watchdog@2004c000 { 481 compatible = "rockchip,rk3128-wdt", "snps,dw-wdt"; 482 reg = <0x2004c000 0x100>; 483 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 484 clocks = <&cru PCLK_WDT>; 485 status = "disabled"; 486 }; 487 488 pwm0: pwm@20050000 { 489 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; 490 reg = <0x20050000 0x10>; 491 clocks = <&cru PCLK_PWM>; 492 pinctrl-names = "default"; 493 pinctrl-0 = <&pwm0_pin>; 494 #pwm-cells = <3>; 495 status = "disabled"; 496 }; 497 498 pwm1: pwm@20050010 { 499 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; 500 reg = <0x20050010 0x10>; 501 clocks = <&cru PCLK_PWM>; 502 pinctrl-names = "default"; 503 pinctrl-0 = <&pwm1_pin>; 504 #pwm-cells = <3>; 505 status = "disabled"; 506 }; 507 508 pwm2: pwm@20050020 { 509 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; 510 reg = <0x20050020 0x10>; 511 clocks = <&cru PCLK_PWM>; 512 pinctrl-names = "default"; 513 pinctrl-0 = <&pwm2_pin>; 514 #pwm-cells = <3>; 515 status = "disabled"; 516 }; 517 518 pwm3: pwm@20050030 { 519 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; 520 reg = <0x20050030 0x10>; 521 clocks = <&cru PCLK_PWM>; 522 pinctrl-names = "default"; 523 pinctrl-0 = <&pwm3_pin>; 524 #pwm-cells = <3>; 525 status = "disabled"; 526 }; 527 528 i2c1: i2c@20056000 { 529 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; 530 reg = <0x20056000 0x1000>; 531 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 532 clock-names = "i2c"; 533 clocks = <&cru PCLK_I2C1>; 534 pinctrl-names = "default"; 535 pinctrl-0 = <&i2c1_xfer>; 536 #address-cells = <1>; 537 #size-cells = <0>; 538 status = "disabled"; 539 }; 540 541 i2c2: i2c@2005a000 { 542 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; 543 reg = <0x2005a000 0x1000>; 544 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 545 clock-names = "i2c"; 546 clocks = <&cru PCLK_I2C2>; 547 pinctrl-names = "default"; 548 pinctrl-0 = <&i2c2_xfer>; 549 #address-cells = <1>; 550 #size-cells = <0>; 551 status = "disabled"; 552 }; 553 554 i2c3: i2c@2005e000 { 555 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; 556 reg = <0x2005e000 0x1000>; 557 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 558 clock-names = "i2c"; 559 clocks = <&cru PCLK_I2C3>; 560 pinctrl-names = "default"; 561 pinctrl-0 = <&i2c3_xfer>; 562 #address-cells = <1>; 563 #size-cells = <0>; 564 status = "disabled"; 565 }; 566 567 uart0: serial@20060000 { 568 compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart"; 569 reg = <0x20060000 0x100>; 570 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 571 clock-frequency = <24000000>; 572 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 573 clock-names = "baudclk", "apb_pclk"; 574 dmas = <&pdma 2>, <&pdma 3>; 575 dma-names = "tx", "rx"; 576 pinctrl-names = "default"; 577 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; 578 reg-io-width = <4>; 579 reg-shift = <2>; 580 status = "disabled"; 581 }; 582 583 uart1: serial@20064000 { 584 compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart"; 585 reg = <0x20064000 0x100>; 586 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 587 clock-frequency = <24000000>; 588 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 589 clock-names = "baudclk", "apb_pclk"; 590 dmas = <&pdma 4>, <&pdma 5>; 591 dma-names = "tx", "rx"; 592 pinctrl-names = "default"; 593 pinctrl-0 = <&uart1_xfer>; 594 reg-io-width = <4>; 595 reg-shift = <2>; 596 status = "disabled"; 597 }; 598 599 uart2: serial@20068000 { 600 compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart"; 601 reg = <0x20068000 0x100>; 602 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 603 clock-frequency = <24000000>; 604 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 605 clock-names = "baudclk", "apb_pclk"; 606 dmas = <&pdma 6>, <&pdma 7>; 607 dma-names = "tx", "rx"; 608 pinctrl-names = "default"; 609 pinctrl-0 = <&uart2_xfer>; 610 reg-io-width = <4>; 611 reg-shift = <2>; 612 status = "disabled"; 613 }; 614 615 saradc: saradc@2006c000 { 616 compatible = "rockchip,saradc"; 617 reg = <0x2006c000 0x100>; 618 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 619 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 620 clock-names = "saradc", "apb_pclk"; 621 resets = <&cru SRST_SARADC>; 622 reset-names = "saradc-apb"; 623 #io-channel-cells = <1>; 624 status = "disabled"; 625 }; 626 627 i2c0: i2c@20072000 { 628 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; 629 reg = <0x20072000 0x1000>; 630 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 631 clock-names = "i2c"; 632 clocks = <&cru PCLK_I2C0>; 633 pinctrl-names = "default"; 634 pinctrl-0 = <&i2c0_xfer>; 635 #address-cells = <1>; 636 #size-cells = <0>; 637 status = "disabled"; 638 }; 639 640 spi0: spi@20074000 { 641 compatible = "rockchip,rk3128-spi", "rockchip,rk3066-spi"; 642 reg = <0x20074000 0x1000>; 643 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 644 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 645 clock-names = "spiclk", "apb_pclk"; 646 dmas = <&pdma 8>, <&pdma 9>; 647 dma-names = "tx", "rx"; 648 pinctrl-names = "default"; 649 pinctrl-0 = <&spi0_tx &spi0_rx &spi0_clk &spi0_cs0 &spi0_cs1>; 650 #address-cells = <1>; 651 #size-cells = <0>; 652 status = "disabled"; 653 }; 654 655 pdma: dma-controller@20078000 { 656 compatible = "arm,pl330", "arm,primecell"; 657 reg = <0x20078000 0x4000>; 658 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 659 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 660 arm,pl330-broken-no-flushp; 661 arm,pl330-periph-burst; 662 clocks = <&cru ACLK_DMAC>; 663 clock-names = "apb_pclk"; 664 #dma-cells = <1>; 665 }; 666 667 gmac: ethernet@2008c000 { 668 compatible = "rockchip,rk3128-gmac"; 669 reg = <0x2008c000 0x4000>; 670 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 671 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 672 interrupt-names = "macirq", "eth_wake_irq"; 673 clocks = <&cru SCLK_MAC>, 674 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>, 675 <&cru SCLK_MAC_REF>, <&cru SCLK_MAC_REFOUT>, 676 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>; 677 clock-names = "stmmaceth", 678 "mac_clk_rx", "mac_clk_tx", 679 "clk_mac_ref", "clk_mac_refout", 680 "aclk_mac", "pclk_mac"; 681 resets = <&cru SRST_GMAC>; 682 reset-names = "stmmaceth"; 683 rockchip,grf = <&grf>; 684 rx-fifo-depth = <4096>; 685 tx-fifo-depth = <2048>; 686 status = "disabled"; 687 688 mdio: mdio { 689 compatible = "snps,dwmac-mdio"; 690 #address-cells = <0x1>; 691 #size-cells = <0x0>; 692 }; 693 }; 694 695 pinctrl: pinctrl { 696 compatible = "rockchip,rk3128-pinctrl"; 697 rockchip,grf = <&grf>; 698 #address-cells = <1>; 699 #size-cells = <1>; 700 ranges; 701 702 gpio0: gpio@2007c000 { 703 compatible = "rockchip,gpio-bank"; 704 reg = <0x2007c000 0x100>; 705 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 706 clocks = <&cru PCLK_GPIO0>; 707 gpio-controller; 708 #gpio-cells = <2>; 709 interrupt-controller; 710 #interrupt-cells = <2>; 711 }; 712 713 gpio1: gpio@20080000 { 714 compatible = "rockchip,gpio-bank"; 715 reg = <0x20080000 0x100>; 716 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 717 clocks = <&cru PCLK_GPIO1>; 718 gpio-controller; 719 #gpio-cells = <2>; 720 interrupt-controller; 721 #interrupt-cells = <2>; 722 }; 723 724 gpio2: gpio@20084000 { 725 compatible = "rockchip,gpio-bank"; 726 reg = <0x20084000 0x100>; 727 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 728 clocks = <&cru PCLK_GPIO2>; 729 gpio-controller; 730 #gpio-cells = <2>; 731 interrupt-controller; 732 #interrupt-cells = <2>; 733 }; 734 735 gpio3: gpio@20088000 { 736 compatible = "rockchip,gpio-bank"; 737 reg = <0x20088000 0x100>; 738 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 739 clocks = <&cru PCLK_GPIO3>; 740 gpio-controller; 741 #gpio-cells = <2>; 742 interrupt-controller; 743 #interrupt-cells = <2>; 744 }; 745 746 pcfg_pull_default: pcfg-pull-default { 747 bias-pull-pin-default; 748 }; 749 750 pcfg_pull_none: pcfg-pull-none { 751 bias-disable; 752 }; 753 754 emmc { 755 emmc_clk: emmc-clk { 756 rockchip,pins = <2 RK_PA7 2 &pcfg_pull_none>; 757 }; 758 759 emmc_cmd: emmc-cmd { 760 rockchip,pins = <1 RK_PC6 2 &pcfg_pull_default>; 761 }; 762 763 emmc_cmd1: emmc-cmd1 { 764 rockchip,pins = <2 RK_PA4 2 &pcfg_pull_default>; 765 }; 766 767 emmc_pwr: emmc-pwr { 768 rockchip,pins = <2 RK_PA5 2 &pcfg_pull_default>; 769 }; 770 771 emmc_bus1: emmc-bus1 { 772 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>; 773 }; 774 775 emmc_bus4: emmc-bus4 { 776 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>, 777 <1 RK_PD1 2 &pcfg_pull_default>, 778 <1 RK_PD2 2 &pcfg_pull_default>, 779 <1 RK_PD3 2 &pcfg_pull_default>; 780 }; 781 782 emmc_bus8: emmc-bus8 { 783 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>, 784 <1 RK_PD1 2 &pcfg_pull_default>, 785 <1 RK_PD2 2 &pcfg_pull_default>, 786 <1 RK_PD3 2 &pcfg_pull_default>, 787 <1 RK_PD4 2 &pcfg_pull_default>, 788 <1 RK_PD5 2 &pcfg_pull_default>, 789 <1 RK_PD6 2 &pcfg_pull_default>, 790 <1 RK_PD7 2 &pcfg_pull_default>; 791 }; 792 }; 793 794 gmac { 795 rgmii_pins: rgmii-pins { 796 rockchip,pins = <2 RK_PB0 3 &pcfg_pull_default>, 797 <2 RK_PB1 3 &pcfg_pull_default>, 798 <2 RK_PB3 3 &pcfg_pull_default>, 799 <2 RK_PB4 3 &pcfg_pull_default>, 800 <2 RK_PB5 3 &pcfg_pull_default>, 801 <2 RK_PB6 3 &pcfg_pull_default>, 802 <2 RK_PC0 3 &pcfg_pull_default>, 803 <2 RK_PC1 3 &pcfg_pull_default>, 804 <2 RK_PC2 3 &pcfg_pull_default>, 805 <2 RK_PC3 3 &pcfg_pull_default>, 806 <2 RK_PD1 3 &pcfg_pull_default>, 807 <2 RK_PC4 4 &pcfg_pull_default>, 808 <2 RK_PC5 4 &pcfg_pull_default>, 809 <2 RK_PC6 4 &pcfg_pull_default>, 810 <2 RK_PC7 4 &pcfg_pull_default>; 811 }; 812 813 rmii_pins: rmii-pins { 814 rockchip,pins = <2 RK_PB0 3 &pcfg_pull_default>, 815 <2 RK_PB4 3 &pcfg_pull_default>, 816 <2 RK_PB5 3 &pcfg_pull_default>, 817 <2 RK_PB6 3 &pcfg_pull_default>, 818 <2 RK_PB7 3 &pcfg_pull_default>, 819 <2 RK_PC0 3 &pcfg_pull_default>, 820 <2 RK_PC1 3 &pcfg_pull_default>, 821 <2 RK_PC2 3 &pcfg_pull_default>, 822 <2 RK_PC3 3 &pcfg_pull_default>, 823 <2 RK_PD1 3 &pcfg_pull_default>; 824 }; 825 }; 826 827 hdmi { 828 hdmii2c_xfer: hdmii2c-xfer { 829 rockchip,pins = <0 RK_PA6 2 &pcfg_pull_none>, 830 <0 RK_PA7 2 &pcfg_pull_none>; 831 }; 832 833 hdmi_hpd: hdmi-hpd { 834 rockchip,pins = <0 RK_PB7 1 &pcfg_pull_none>; 835 }; 836 837 hdmi_cec: hdmi-cec { 838 rockchip,pins = <0 RK_PC4 1 &pcfg_pull_none>; 839 }; 840 }; 841 842 i2c0 { 843 i2c0_xfer: i2c0-xfer { 844 rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>, 845 <0 RK_PA1 1 &pcfg_pull_none>; 846 }; 847 }; 848 849 i2c1 { 850 i2c1_xfer: i2c1-xfer { 851 rockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>, 852 <0 RK_PA3 1 &pcfg_pull_none>; 853 }; 854 }; 855 856 i2c2 { 857 i2c2_xfer: i2c2-xfer { 858 rockchip,pins = <2 RK_PC4 3 &pcfg_pull_none>, 859 <2 RK_PC5 3 &pcfg_pull_none>; 860 }; 861 }; 862 863 i2c3 { 864 i2c3_xfer: i2c3-xfer { 865 rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>, 866 <0 RK_PA7 1 &pcfg_pull_none>; 867 }; 868 }; 869 870 i2s { 871 i2s_bus: i2s-bus { 872 rockchip,pins = <0 RK_PB0 1 &pcfg_pull_none>, 873 <0 RK_PB1 1 &pcfg_pull_none>, 874 <0 RK_PB3 1 &pcfg_pull_none>, 875 <0 RK_PB4 1 &pcfg_pull_none>, 876 <0 RK_PB5 1 &pcfg_pull_none>, 877 <0 RK_PB6 1 &pcfg_pull_none>; 878 }; 879 880 i2s1_bus: i2s1-bus { 881 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_none>, 882 <1 RK_PA1 1 &pcfg_pull_none>, 883 <1 RK_PA2 1 &pcfg_pull_none>, 884 <1 RK_PA3 1 &pcfg_pull_none>, 885 <1 RK_PA4 1 &pcfg_pull_none>, 886 <1 RK_PA5 1 &pcfg_pull_none>; 887 }; 888 }; 889 890 lcdc { 891 lcdc_dclk: lcdc-dclk { 892 rockchip,pins = <2 RK_PB0 1 &pcfg_pull_none>; 893 }; 894 895 lcdc_den: lcdc-den { 896 rockchip,pins = <2 RK_PB3 1 &pcfg_pull_none>; 897 }; 898 899 lcdc_hsync: lcdc-hsync { 900 rockchip,pins = <2 RK_PB1 1 &pcfg_pull_none>; 901 }; 902 903 lcdc_vsync: lcdc-vsync { 904 rockchip,pins = <2 RK_PB2 1 &pcfg_pull_none>; 905 }; 906 907 lcdc_rgb24: lcdc-rgb24 { 908 rockchip,pins = <2 RK_PB4 1 &pcfg_pull_none>, 909 <2 RK_PB5 1 &pcfg_pull_none>, 910 <2 RK_PB6 1 &pcfg_pull_none>, 911 <2 RK_PB7 1 &pcfg_pull_none>, 912 <2 RK_PC0 1 &pcfg_pull_none>, 913 <2 RK_PC1 1 &pcfg_pull_none>, 914 <2 RK_PC2 1 &pcfg_pull_none>, 915 <2 RK_PC3 1 &pcfg_pull_none>, 916 <2 RK_PC4 1 &pcfg_pull_none>, 917 <2 RK_PC5 1 &pcfg_pull_none>, 918 <2 RK_PC6 1 &pcfg_pull_none>, 919 <2 RK_PC7 1 &pcfg_pull_none>, 920 <2 RK_PD0 1 &pcfg_pull_none>, 921 <2 RK_PD1 1 &pcfg_pull_none>; 922 }; 923 }; 924 925 nfc { 926 flash_ale: flash-ale { 927 rockchip,pins = <2 RK_PA0 1 &pcfg_pull_none>; 928 }; 929 930 flash_cle: flash-cle { 931 rockchip,pins = <2 RK_PA1 1 &pcfg_pull_none>; 932 }; 933 934 flash_wrn: flash-wrn { 935 rockchip,pins = <2 RK_PA2 1 &pcfg_pull_none>; 936 }; 937 938 flash_rdn: flash-rdn { 939 rockchip,pins = <2 RK_PA3 1 &pcfg_pull_none>; 940 }; 941 942 flash_rdy: flash-rdy { 943 rockchip,pins = <2 RK_PA4 1 &pcfg_pull_none>; 944 }; 945 946 flash_cs0: flash-cs0 { 947 rockchip,pins = <2 RK_PA6 1 &pcfg_pull_none>; 948 }; 949 950 flash_dqs: flash-dqs { 951 rockchip,pins = <2 RK_PA7 1 &pcfg_pull_none>; 952 }; 953 954 flash_bus8: flash-bus8 { 955 rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>, 956 <1 RK_PD1 1 &pcfg_pull_none>, 957 <1 RK_PD2 1 &pcfg_pull_none>, 958 <1 RK_PD3 1 &pcfg_pull_none>, 959 <1 RK_PD4 1 &pcfg_pull_none>, 960 <1 RK_PD5 1 &pcfg_pull_none>, 961 <1 RK_PD6 1 &pcfg_pull_none>, 962 <1 RK_PD7 1 &pcfg_pull_none>; 963 }; 964 }; 965 966 pwm0 { 967 pwm0_pin: pwm0-pin { 968 rockchip,pins = <0 RK_PD2 1 &pcfg_pull_none>; 969 }; 970 }; 971 972 pwm1 { 973 pwm1_pin: pwm1-pin { 974 rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>; 975 }; 976 }; 977 978 pwm2 { 979 pwm2_pin: pwm2-pin { 980 rockchip,pins = <0 RK_PD4 1 &pcfg_pull_none>; 981 }; 982 }; 983 984 pwm3 { 985 pwm3_pin: pwm3-pin { 986 rockchip,pins = <3 RK_PD2 1 &pcfg_pull_none>; 987 }; 988 }; 989 990 sdio { 991 sdio_clk: sdio-clk { 992 rockchip,pins = <1 RK_PA0 2 &pcfg_pull_none>; 993 }; 994 995 sdio_cmd: sdio-cmd { 996 rockchip,pins = <0 RK_PA3 2 &pcfg_pull_default>; 997 }; 998 999 sdio_pwren: sdio-pwren { 1000 rockchip,pins = <0 RK_PD6 1 &pcfg_pull_default>; 1001 }; 1002 1003 sdio_bus4: sdio-bus4 { 1004 rockchip,pins = <1 RK_PA1 2 &pcfg_pull_default>, 1005 <1 RK_PA2 2 &pcfg_pull_default>, 1006 <1 RK_PA4 2 &pcfg_pull_default>, 1007 <1 RK_PA5 2 &pcfg_pull_default>; 1008 }; 1009 }; 1010 1011 sdmmc { 1012 sdmmc_clk: sdmmc-clk { 1013 rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>; 1014 }; 1015 1016 sdmmc_cmd: sdmmc-cmd { 1017 rockchip,pins = <1 RK_PB7 1 &pcfg_pull_default>; 1018 }; 1019 1020 sdmmc_det: sdmmc-det { 1021 rockchip,pins = <1 RK_PC1 1 &pcfg_pull_default>; 1022 }; 1023 1024 sdmmc_wp: sdmmc-wp { 1025 rockchip,pins = <1 RK_PA7 1 &pcfg_pull_default>; 1026 }; 1027 1028 sdmmc_pwren: sdmmc-pwren { 1029 rockchip,pins = <1 RK_PB6 1 &pcfg_pull_default>; 1030 }; 1031 1032 sdmmc_bus4: sdmmc-bus4 { 1033 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_default>, 1034 <1 RK_PC3 1 &pcfg_pull_default>, 1035 <1 RK_PC4 1 &pcfg_pull_default>, 1036 <1 RK_PC5 1 &pcfg_pull_default>; 1037 }; 1038 }; 1039 1040 spdif { 1041 spdif_tx: spdif-tx { 1042 rockchip,pins = <3 RK_PD3 1 &pcfg_pull_none>; 1043 }; 1044 }; 1045 1046 spi0 { 1047 spi0_clk: spi0-clk { 1048 rockchip,pins = <1 RK_PB0 1 &pcfg_pull_default>; 1049 }; 1050 1051 spi0_cs0: spi0-cs0 { 1052 rockchip,pins = <1 RK_PB3 1 &pcfg_pull_default>; 1053 }; 1054 1055 spi0_tx: spi0-tx { 1056 rockchip,pins = <1 RK_PB1 1 &pcfg_pull_default>; 1057 }; 1058 1059 spi0_rx: spi0-rx { 1060 rockchip,pins = <1 RK_PB2 1 &pcfg_pull_default>; 1061 }; 1062 1063 spi0_cs1: spi0-cs1 { 1064 rockchip,pins = <1 RK_PB4 1 &pcfg_pull_default>; 1065 }; 1066 1067 spi1_clk: spi1-clk { 1068 rockchip,pins = <2 RK_PA0 2 &pcfg_pull_default>; 1069 }; 1070 1071 spi1_cs0: spi1-cs0 { 1072 rockchip,pins = <1 RK_PD6 3 &pcfg_pull_default>; 1073 }; 1074 1075 spi1_tx: spi1-tx { 1076 rockchip,pins = <1 RK_PD5 3 &pcfg_pull_default>; 1077 }; 1078 1079 spi1_rx: spi1-rx { 1080 rockchip,pins = <1 RK_PD4 3 &pcfg_pull_default>; 1081 }; 1082 1083 spi1_cs1: spi1-cs1 { 1084 rockchip,pins = <1 RK_PD7 3 &pcfg_pull_default>; 1085 }; 1086 1087 spi2_clk: spi2-clk { 1088 rockchip,pins = <0 RK_PB1 2 &pcfg_pull_default>; 1089 }; 1090 1091 spi2_cs0: spi2-cs0 { 1092 rockchip,pins = <0 RK_PB6 2 &pcfg_pull_default>; 1093 }; 1094 1095 spi2_tx: spi2-tx { 1096 rockchip,pins = <0 RK_PB3 2 &pcfg_pull_default>; 1097 }; 1098 1099 spi2_rx: spi2-rx { 1100 rockchip,pins = <0 RK_PB5 2 &pcfg_pull_default>; 1101 }; 1102 }; 1103 1104 uart0 { 1105 uart0_xfer: uart0-xfer { 1106 rockchip,pins = <2 RK_PD2 2 &pcfg_pull_default>, 1107 <2 RK_PD3 2 &pcfg_pull_none>; 1108 }; 1109 1110 uart0_cts: uart0-cts { 1111 rockchip,pins = <2 RK_PD5 2 &pcfg_pull_none>; 1112 }; 1113 1114 uart0_rts: uart0-rts { 1115 rockchip,pins = <0 RK_PC1 2 &pcfg_pull_none>; 1116 }; 1117 }; 1118 1119 uart1 { 1120 uart1_xfer: uart1-xfer { 1121 rockchip,pins = <1 RK_PB1 2 &pcfg_pull_default>, 1122 <1 RK_PB2 2 &pcfg_pull_default>; 1123 }; 1124 1125 uart1_cts: uart1-cts { 1126 rockchip,pins = <1 RK_PB0 2 &pcfg_pull_none>; 1127 }; 1128 1129 uart1_rts: uart1-rts { 1130 rockchip,pins = <1 RK_PB3 2 &pcfg_pull_none>; 1131 }; 1132 }; 1133 1134 uart2 { 1135 uart2_xfer: uart2-xfer { 1136 rockchip,pins = <1 RK_PC2 2 &pcfg_pull_default>, 1137 <1 RK_PC3 2 &pcfg_pull_none>; 1138 }; 1139 1140 uart2_cts: uart2-cts { 1141 rockchip,pins = <0 RK_PD1 1 &pcfg_pull_none>; 1142 }; 1143 1144 uart2_rts: uart2-rts { 1145 rockchip,pins = <0 RK_PD0 1 &pcfg_pull_none>; 1146 }; 1147 }; 1148 }; 1149}; 1150