Kconfig (d702d12167a2c05a346f49aac7a311d597762495) Kconfig (2f7e8faef5a50efaa1c173e99bdaa29e0129bb99)
1#
2# For a description of the syntax of this configuration file,
3# see Documentation/kbuild/kconfig-language.txt.
4#
5
6mainmenu "Linux Kernel Configuration"
7
8config ARM
9 bool
10 default y
11 select HAVE_AOUT
12 select HAVE_IDE
13 select RTC_LIB
14 select SYS_SUPPORTS_APM_EMULATION
1#
2# For a description of the syntax of this configuration file,
3# see Documentation/kbuild/kconfig-language.txt.
4#
5
6mainmenu "Linux Kernel Configuration"
7
8config ARM
9 bool
10 default y
11 select HAVE_AOUT
12 select HAVE_IDE
13 select RTC_LIB
14 select SYS_SUPPORTS_APM_EMULATION
15 select GENERIC_ATOMIC64 if (!CPU_32v6K)
16 select HAVE_OPROFILE
17 select HAVE_ARCH_KGDB
18 select HAVE_KPROBES if (!XIP_KERNEL)
19 select HAVE_KRETPROBES if (HAVE_KPROBES)
20 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
21 select HAVE_GENERIC_DMA_COHERENT
22 select HAVE_KERNEL_GZIP
23 select HAVE_KERNEL_LZO
15 select HAVE_OPROFILE
16 select HAVE_ARCH_KGDB
17 select HAVE_KPROBES if (!XIP_KERNEL)
18 select HAVE_KRETPROBES if (HAVE_KPROBES)
19 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
20 select HAVE_GENERIC_DMA_COHERENT
21 select HAVE_KERNEL_GZIP
22 select HAVE_KERNEL_LZO
24 select HAVE_PERF_EVENTS
25 select PERF_USE_VMALLOC
26 help
27 The ARM series is a line of low-power-consumption RISC chip designs
28 licensed by ARM Ltd and targeted at embedded applications and
29 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
30 manufactured, but legacy ARM-based PC hardware remains popular in
31 Europe. There is an ARM Linux project with a web page at
32 <http://www.arm.linux.org.uk/>.
33

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50 bool
51 depends on GENERIC_CLOCKEVENTS
52 default y if SMP && !LOCAL_TIMERS
53
54config HAVE_TCM
55 bool
56 select GENERIC_ALLOCATOR
57
23 help
24 The ARM series is a line of low-power-consumption RISC chip designs
25 licensed by ARM Ltd and targeted at embedded applications and
26 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
27 manufactured, but legacy ARM-based PC hardware remains popular in
28 Europe. There is an ARM Linux project with a web page at
29 <http://www.arm.linux.org.uk/>.
30

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47 bool
48 depends on GENERIC_CLOCKEVENTS
49 default y if SMP && !LOCAL_TIMERS
50
51config HAVE_TCM
52 bool
53 select GENERIC_ALLOCATOR
54
58config HAVE_PROC_CPU
59 bool
60
61config NO_IOPORT
62 bool
63
64config EISA
65 bool
66 ---help---
67 The Extended Industry Standard Architecture (EISA) bus was
68 developed as an open alternative to the IBM MicroChannel bus.

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162 bool
163
164config ARCH_MTD_XIP
165 bool
166
167config GENERIC_HARDIRQS_NO__DO_IRQ
168 def_bool y
169
55config NO_IOPORT
56 bool
57
58config EISA
59 bool
60 ---help---
61 The Extended Industry Standard Architecture (EISA) bus was
62 developed as an open alternative to the IBM MicroChannel bus.

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156 bool
157
158config ARCH_MTD_XIP
159 bool
160
161config GENERIC_HARDIRQS_NO__DO_IRQ
162 def_bool y
163
170config ARM_L1_CACHE_SHIFT_6
171 bool
172 help
173 Setting ARM L1 cache line size to 64 Bytes.
174
175if OPROFILE
176
177config OPROFILE_ARMV6
178 def_bool y
179 depends on CPU_V6 && !SMP
180 select OPROFILE_ARM11_CORE
181
182config OPROFILE_MPCORE

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503 select GENERIC_CLOCKEVENTS
504 select PLAT_ORION
505 help
506 Support for the following Marvell Orion 5x series SoCs:
507 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
508 Orion-2 (5281), Orion-1-90 (6183).
509
510config ARCH_MMP
164if OPROFILE
165
166config OPROFILE_ARMV6
167 def_bool y
168 depends on CPU_V6 && !SMP
169 select OPROFILE_ARM11_CORE
170
171config OPROFILE_MPCORE

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492 select GENERIC_CLOCKEVENTS
493 select PLAT_ORION
494 help
495 Support for the following Marvell Orion 5x series SoCs:
496 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
497 Orion-2 (5281), Orion-1-90 (6183).
498
499config ARCH_MMP
511 bool "Marvell PXA168/910"
500 bool "Marvell PXA168/910/MMP2"
512 depends on MMU
513 select GENERIC_GPIO
514 select ARCH_REQUIRE_GPIOLIB
515 select HAVE_CLK
516 select COMMON_CLKDEV
517 select GENERIC_TIME
518 select GENERIC_CLOCKEVENTS
519 select TICK_ONESHOT
520 select PLAT_PXA
521 help
501 depends on MMU
502 select GENERIC_GPIO
503 select ARCH_REQUIRE_GPIOLIB
504 select HAVE_CLK
505 select COMMON_CLKDEV
506 select GENERIC_TIME
507 select GENERIC_CLOCKEVENTS
508 select TICK_ONESHOT
509 select PLAT_PXA
510 help
522 Support for Marvell's PXA168/910 processor line.
511 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
523
524config ARCH_KS8695
525 bool "Micrel/Kendin KS8695"
526 select CPU_ARM922T
527 select GENERIC_GPIO
528 select ARCH_REQUIRE_GPIOLIB
529 help
530 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based

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556 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
557 At present, the w90x900 has been renamed nuc900, regarding
558 the ARM series product line, you can login the following
559 link address to know more.
560
561 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
562 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
563
512
513config ARCH_KS8695
514 bool "Micrel/Kendin KS8695"
515 select CPU_ARM922T
516 select GENERIC_GPIO
517 select ARCH_REQUIRE_GPIOLIB
518 help
519 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based

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545 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
546 At present, the w90x900 has been renamed nuc900, regarding
547 the ARM series product line, you can login the following
548 link address to know more.
549
550 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
551 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
552
564config ARCH_NUC93X
565 bool "Nuvoton NUC93X CPU"
566 select CPU_ARM926T
567 select HAVE_CLK
568 select COMMON_CLKDEV
569 help
570 Support for Nuvoton (Winbond logic dept.) NUC93X MCU,The NUC93X is a
571 low-power and high performance MPEG-4/JPEG multimedia controller chip.
572
573config ARCH_PNX4008
574 bool "Philips Nexperia PNX4008 Mobile"
575 select CPU_ARM926T
576 select HAVE_CLK
553config ARCH_PNX4008
554 bool "Philips Nexperia PNX4008 Mobile"
555 select CPU_ARM926T
556 select HAVE_CLK
577 select COMMON_CLKDEV
578 help
579 This enables support for Philips PNX4008 mobile platform.
580
581config ARCH_PXA
582 bool "PXA2xx/PXA3xx-based"
583 depends on MMU
584 select ARCH_MTD_XIP
585 select ARCH_HAS_CPUFREQ

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649config ARCH_S3C64XX
650 bool "Samsung S3C64XX"
651 select GENERIC_GPIO
652 select HAVE_CLK
653 select ARCH_HAS_CPUFREQ
654 help
655 Samsung S3C64XX series based systems
656
557 help
558 This enables support for Philips PNX4008 mobile platform.
559
560config ARCH_PXA
561 bool "PXA2xx/PXA3xx-based"
562 depends on MMU
563 select ARCH_MTD_XIP
564 select ARCH_HAS_CPUFREQ

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628config ARCH_S3C64XX
629 bool "Samsung S3C64XX"
630 select GENERIC_GPIO
631 select HAVE_CLK
632 select ARCH_HAS_CPUFREQ
633 help
634 Samsung S3C64XX series based systems
635
636config ARCH_S5P6440
637 bool "Samsung S5P6440"
638 select CPU_V6
639 select GENERIC_GPIO
640 select HAVE_CLK
641 help
642 Samsung S5P6440 CPU based systems
643
657config ARCH_S5PC1XX
658 bool "Samsung S5PC1XX"
659 select GENERIC_GPIO
660 select HAVE_CLK
661 select CPU_V7
644config ARCH_S5PC1XX
645 bool "Samsung S5PC1XX"
646 select GENERIC_GPIO
647 select HAVE_CLK
648 select CPU_V7
662 select ARM_L1_CACHE_SHIFT_6
663 help
664 Samsung S5PC1XX series based systems
665
666config ARCH_SHARK
667 bool "Shark"
668 select CPU_SA110
669 select ISA
670 select ISA_DMA

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802
803source "arch/arm/mach-netx/Kconfig"
804
805source "arch/arm/mach-nomadik/Kconfig"
806source "arch/arm/plat-nomadik/Kconfig"
807
808source "arch/arm/mach-ns9xxx/Kconfig"
809
649 help
650 Samsung S5PC1XX series based systems
651
652config ARCH_SHARK
653 bool "Shark"
654 select CPU_SA110
655 select ISA
656 select ISA_DMA

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788
789source "arch/arm/mach-netx/Kconfig"
790
791source "arch/arm/mach-nomadik/Kconfig"
792source "arch/arm/plat-nomadik/Kconfig"
793
794source "arch/arm/mach-ns9xxx/Kconfig"
795
810source "arch/arm/mach-nuc93x/Kconfig"
811
812source "arch/arm/plat-omap/Kconfig"
813
814source "arch/arm/mach-omap1/Kconfig"
815
816source "arch/arm/mach-omap2/Kconfig"
817
818source "arch/arm/mach-orion5x/Kconfig"
819

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825source "arch/arm/mach-realview/Kconfig"
826
827source "arch/arm/mach-sa1100/Kconfig"
828
829source "arch/arm/plat-samsung/Kconfig"
830source "arch/arm/plat-s3c24xx/Kconfig"
831source "arch/arm/plat-s3c64xx/Kconfig"
832source "arch/arm/plat-s3c/Kconfig"
796source "arch/arm/plat-omap/Kconfig"
797
798source "arch/arm/mach-omap1/Kconfig"
799
800source "arch/arm/mach-omap2/Kconfig"
801
802source "arch/arm/mach-orion5x/Kconfig"
803

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809source "arch/arm/mach-realview/Kconfig"
810
811source "arch/arm/mach-sa1100/Kconfig"
812
813source "arch/arm/plat-samsung/Kconfig"
814source "arch/arm/plat-s3c24xx/Kconfig"
815source "arch/arm/plat-s3c64xx/Kconfig"
816source "arch/arm/plat-s3c/Kconfig"
817source "arch/arm/plat-s5p/Kconfig"
833source "arch/arm/plat-s5pc1xx/Kconfig"
834
835if ARCH_S3C2410
836source "arch/arm/mach-s3c2400/Kconfig"
837source "arch/arm/mach-s3c2410/Kconfig"
838source "arch/arm/mach-s3c2412/Kconfig"
839source "arch/arm/mach-s3c2440/Kconfig"
840source "arch/arm/mach-s3c2442/Kconfig"
841source "arch/arm/mach-s3c2443/Kconfig"
842endif
843
844if ARCH_S3C64XX
845source "arch/arm/mach-s3c6400/Kconfig"
846source "arch/arm/mach-s3c6410/Kconfig"
847endif
848
818source "arch/arm/plat-s5pc1xx/Kconfig"
819
820if ARCH_S3C2410
821source "arch/arm/mach-s3c2400/Kconfig"
822source "arch/arm/mach-s3c2410/Kconfig"
823source "arch/arm/mach-s3c2412/Kconfig"
824source "arch/arm/mach-s3c2440/Kconfig"
825source "arch/arm/mach-s3c2442/Kconfig"
826source "arch/arm/mach-s3c2443/Kconfig"
827endif
828
829if ARCH_S3C64XX
830source "arch/arm/mach-s3c6400/Kconfig"
831source "arch/arm/mach-s3c6410/Kconfig"
832endif
833
834source "arch/arm/mach-s5p6440/Kconfig"
835
849source "arch/arm/plat-stmp3xxx/Kconfig"
850
851if ARCH_S5PC1XX
852source "arch/arm/mach-s5pc100/Kconfig"
853endif
854
855source "arch/arm/mach-u300/Kconfig"
856

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886 running on a CPU that supports it.
887
888# bool 'Use XScale PMU as timer source' CONFIG_XSCALE_PMU_TIMER
889config XSCALE_PMU
890 bool
891 depends on CPU_XSCALE && !XSCALE_PMU_TIMER
892 default y
893
836source "arch/arm/plat-stmp3xxx/Kconfig"
837
838if ARCH_S5PC1XX
839source "arch/arm/mach-s5pc100/Kconfig"
840endif
841
842source "arch/arm/mach-u300/Kconfig"
843

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873 running on a CPU that supports it.
874
875# bool 'Use XScale PMU as timer source' CONFIG_XSCALE_PMU_TIMER
876config XSCALE_PMU
877 bool
878 depends on CPU_XSCALE && !XSCALE_PMU_TIMER
879 default y
880
894config CPU_HAS_PMU
895 depends on CPU_V6 || CPU_V7 || XSCALE_PMU
896 default y
897 bool
898
899if !MMU
900source "arch/arm/Kconfig-nommu"
901endif
902
903config ARM_ERRATA_411920
904 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
905 depends on CPU_V6 && !SMP
906 help

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945 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
946 erratum. Any asynchronous access to the L2 cache may encounter a
947 situation in which recent store transactions to the L2 cache are lost
948 and overwritten with stale memory contents from external memory. The
949 workaround disables the write-allocate mode for the L2 cache via the
950 ACTLR register. Note that setting specific bits in the ACTLR register
951 may not be available in non-secure mode.
952
881if !MMU
882source "arch/arm/Kconfig-nommu"
883endif
884
885config ARM_ERRATA_411920
886 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
887 depends on CPU_V6 && !SMP
888 help

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927 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
928 erratum. Any asynchronous access to the L2 cache may encounter a
929 situation in which recent store transactions to the L2 cache are lost
930 and overwritten with stale memory contents from external memory. The
931 workaround disables the write-allocate mode for the L2 cache via the
932 ACTLR register. Note that setting specific bits in the ACTLR register
933 may not be available in non-secure mode.
934
953config PL310_ERRATA_588369
954 bool "Clean & Invalidate maintenance operations do not invalidate clean lines"
955 depends on CACHE_L2X0 && ARCH_OMAP4
956 help
957 The PL310 L2 cache controller implements three types of Clean &
958 Invalidate maintenance operations: by Physical Address
959 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
960 They are architecturally defined to behave as the execution of a
961 clean operation followed immediately by an invalidate operation,
962 both performing to the same memory location. This functionality
963 is not correctly implemented in PL310 as clean lines are not
964 invalidated as a result of these operations. Note that this errata
965 uses Texas Instrument's secure monitor api.
966endmenu
967
968source "arch/arm/common/Kconfig"
969
970config FORCE_MAX_ZONEORDER
971 int
972 depends on SA1111
973 default "9"

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1112 accounting to be spread across the timer interval, preventing a
1113 "thundering herd" at every timer tick.
1114
1115source kernel/Kconfig.preempt
1116
1117config HZ
1118 int
1119 default 128 if ARCH_L7200
935endmenu
936
937source "arch/arm/common/Kconfig"
938
939config FORCE_MAX_ZONEORDER
940 int
941 depends on SA1111
942 default "9"

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1081 accounting to be spread across the timer interval, preventing a
1082 "thundering herd" at every timer tick.
1083
1084source kernel/Kconfig.preempt
1085
1086config HZ
1087 int
1088 default 128 if ARCH_L7200
1120 default 200 if ARCH_EBSA110 || ARCH_S3C2410
1089 default 200 if ARCH_EBSA110 || ARCH_S3C2410 || ARCH_S5P6440
1121 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1122 default AT91_TIMER_HZ if ARCH_AT91
1123 default 100
1124
1125config THUMB2_KERNEL
1126 bool "Compile the kernel in Thumb-2 mode"
1127 depends on CPU_V7 && EXPERIMENTAL
1128 select AEABI

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1208
1209 If unsure, say n.
1210
1211config HIGHPTE
1212 bool "Allocate 2nd-level pagetables from highmem"
1213 depends on HIGHMEM
1214 depends on !OUTER_CACHE
1215
1090 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1091 default AT91_TIMER_HZ if ARCH_AT91
1092 default 100
1093
1094config THUMB2_KERNEL
1095 bool "Compile the kernel in Thumb-2 mode"
1096 depends on CPU_V7 && EXPERIMENTAL
1097 select AEABI

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1177
1178 If unsure, say n.
1179
1180config HIGHPTE
1181 bool "Allocate 2nd-level pagetables from highmem"
1182 depends on HIGHMEM
1183 depends on !OUTER_CACHE
1184
1216config HW_PERF_EVENTS
1217 bool "Enable hardware performance counter support for perf events"
1218 depends on PERF_EVENTS && CPU_HAS_PMU && (CPU_V6 || CPU_V7)
1219 default y
1220 help
1221 Enable hardware performance counter support for perf events. If
1222 disabled, perf events will use software events only.
1223
1224source "mm/Kconfig"
1225
1226config LEDS
1227 bool "Timer and CPU usage LEDs"
1228 depends on ARCH_CDB89712 || ARCH_EBSA110 || \
1229 ARCH_EBSA285 || ARCH_INTEGRATOR || \
1230 ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
1231 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \

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1275 The LART uses the same LED for both Timer LED and CPU usage LED
1276 functions. You may choose to use both, but the Timer LED function
1277 will overrule the CPU usage LED.
1278
1279config ALIGNMENT_TRAP
1280 bool
1281 depends on CPU_CP15_MMU
1282 default y if !ARCH_EBSA110
1185source "mm/Kconfig"
1186
1187config LEDS
1188 bool "Timer and CPU usage LEDs"
1189 depends on ARCH_CDB89712 || ARCH_EBSA110 || \
1190 ARCH_EBSA285 || ARCH_INTEGRATOR || \
1191 ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
1192 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \

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1236 The LART uses the same LED for both Timer LED and CPU usage LED
1237 functions. You may choose to use both, but the Timer LED function
1238 will overrule the CPU usage LED.
1239
1240config ALIGNMENT_TRAP
1241 bool
1242 depends on CPU_CP15_MMU
1243 default y if !ARCH_EBSA110
1283 select HAVE_PROC_CPU if PROC_FS
1284 help
1285 ARM processors cannot fetch/store information which is not
1286 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1287 address divisible by 4. On 32-bit ARM processors, these non-aligned
1288 fetch/store instructions will be emulated in software if you say
1289 here, which has a severe performance impact. This is necessary for
1290 correct operation of some network protocols. With an IP-only
1291 configuration it is safe to say N, otherwise say Y.

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1245 ARM processors cannot fetch/store information which is not
1246 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1247 address divisible by 4. On 32-bit ARM processors, these non-aligned
1248 fetch/store instructions will be emulated in software if you say
1249 here, which has a severe performance impact. This is necessary for
1250 correct operation of some network protocols. With an IP-only
1251 configuration it is safe to say N, otherwise say Y.

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