tlb.c (d79e678d746d3d4234477f08ce7d27d55ebe283a) tlb.c (41195d236e84458bebd4fdc218610a92231ac791)
1/*
2 * TLB Management (flush/create/diagnostics) for ARC700
3 *
4 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.

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469 * ASID mgmt data structures are compile time init
470 * asid_cache = FIRST_ASID and asid_mm_map[] all zeroes
471 */
472
473 local_flush_tlb_all();
474
475 /* Enable the MMU */
476 write_aux_reg(ARC_REG_PID, MMU_ENABLE);
1/*
2 * TLB Management (flush/create/diagnostics) for ARC700
3 *
4 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.

--- 460 unchanged lines hidden (view full) ---

469 * ASID mgmt data structures are compile time init
470 * asid_cache = FIRST_ASID and asid_mm_map[] all zeroes
471 */
472
473 local_flush_tlb_all();
474
475 /* Enable the MMU */
476 write_aux_reg(ARC_REG_PID, MMU_ENABLE);
477
478 /* In smp we use this reg for interrupt 1 scratch */
479#ifndef CONFIG_SMP
480 /* swapper_pg_dir is the pgd for the kernel, used by vmalloc */
481 write_aux_reg(ARC_REG_SCRATCH_DATA0, swapper_pg_dir);
482#endif
477}
478
479/*
480 * TLB Programmer's Model uses Linear Indexes: 0 to {255, 511} for 128 x {2,4}
481 * The mapping is Column-first.
482 * --------------------- -----------
483 * |way0|way1|way2|way3| |way0|way1|
484 * --------------------- -----------

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484
485/*
486 * TLB Programmer's Model uses Linear Indexes: 0 to {255, 511} for 128 x {2,4}
487 * The mapping is Column-first.
488 * --------------------- -----------
489 * |way0|way1|way2|way3| |way0|way1|
490 * --------------------- -----------

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