fsl,plldig.yaml (2b703bbda2713fd2a7d98029ea6c44f9c3159f34) fsl,plldig.yaml (9f60a65bc5e6cd882120d8477cc7bec065887e3d)
1# SPDX-License-Identifier: GPL-2.0
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/fsl,plldig.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: NXP QorIQ Layerscape LS1028A Display PIXEL Clock Binding
8

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23
24 clocks:
25 maxItems: 1
26
27 '#clock-cells':
28 const: 0
29
30 fsl,vco-hz:
1# SPDX-License-Identifier: GPL-2.0
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/fsl,plldig.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: NXP QorIQ Layerscape LS1028A Display PIXEL Clock Binding
8

--- 14 unchanged lines hidden (view full) ---

23
24 clocks:
25 maxItems: 1
26
27 '#clock-cells':
28 const: 0
29
30 fsl,vco-hz:
31 description: Optional for VCO frequency of the PLL in Hertz.
32 The VCO frequency of this PLL cannot be changed during runtime
33 only at startup. Therefore, the output frequencies are very
34 limited and might not even closely match the requested frequency.
35 To work around this restriction the user may specify its own
36 desired VCO frequency for the PLL.
37 minimum: 650000000
38 maximum: 1300000000
39 default: 1188000000
31 description: Optional for VCO frequency of the PLL in Hertz. The VCO frequency
32 of this PLL cannot be changed during runtime only at startup. Therefore,
33 the output frequencies are very limited and might not even closely match
34 the requested frequency. To work around this restriction the user may specify
35 its own desired VCO frequency for the PLL.
36 minimum: 650000000
37 maximum: 1300000000
38 default: 1188000000
40
41required:
42 - compatible
43 - reg
44 - clocks
45 - '#clock-cells'
46
47additionalProperties: false

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40required:
41 - compatible
42 - reg
43 - clocks
44 - '#clock-cells'
45
46additionalProperties: false

--- 12 unchanged lines hidden ---