1# SPDX-License-Identifier: GPL-2.0 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/clock/fsl,plldig.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: NXP QorIQ Layerscape LS1028A Display PIXEL Clock Binding 8 9maintainers: 10 - Wen He <wen.he_1@nxp.com> 11 12description: | 13 NXP LS1028A has a clock domain PXLCLK0 used for the Display output 14 interface in the display core, as implemented in TSMC CLN28HPM PLL. 15 which generate and offers pixel clocks to Display. 16 17properties: 18 compatible: 19 const: fsl,ls1028a-plldig 20 21 reg: 22 maxItems: 1 23 24 clocks: 25 maxItems: 1 26 27 '#clock-cells': 28 const: 0 29 30 fsl,vco-hz: 31 description: Optional for VCO frequency of the PLL in Hertz. 32 The VCO frequency of this PLL cannot be changed during runtime 33 only at startup. Therefore, the output frequencies are very 34 limited and might not even closely match the requested frequency. 35 To work around this restriction the user may specify its own 36 desired VCO frequency for the PLL. 37 minimum: 650000000 38 maximum: 1300000000 39 default: 1188000000 40 41required: 42 - compatible 43 - reg 44 - clocks 45 - '#clock-cells' 46 47additionalProperties: false 48 49examples: 50 # Display PIXEL Clock node: 51 - | 52 dpclk: clock-display@f1f0000 { 53 compatible = "fsl,ls1028a-plldig"; 54 reg = <0x0 0xf1f0000 0x0 0xffff>; 55 #clock-cells = <0>; 56 clocks = <&osc_27m>; 57 }; 58 59... 60