1 /*
2  * This file was automatically generated by cpcgen from the data file
3  * data/perfmonf17h
4  *
5  * Do not modify this file. Your changes will be lost!
6  */
7 
8 #include <opteron_pcbe_table.h>
9 #include <sys/null.h>
10 
11 const amd_event_t opteron_pcbe_f17h_events[] = {
12 	{ "FpuPipeAssignment", 0x000, 0 },
13 	{ "FpSchedEmpty", 0x001, 0 },
14 	{ "FpRetx87FpOps", 0x002, 0 },
15 	{ "FpRetx87FpOps.DivSqrROps", 0x002, 0x4 },
16 	{ "FpRetx87FpOps.MulOps", 0x002, 0x2 },
17 	{ "FpRetx87FpOps.AddSubOps", 0x002, 0x1 },
18 	{ "FpRetSseAvxOps", 0x003, 0 },
19 	{ "FpRetSseAvxOps.DpMultAddFlops", 0x003, 0x80 },
20 	{ "FpRetSseAvxOps.DpDivFlops", 0x003, 0x40 },
21 	{ "FpRetSseAvxOps.DpMultFlops", 0x003, 0x20 },
22 	{ "FpRetSseAvxOps.DpAddSubFlops", 0x003, 0x10 },
23 	{ "FpRetSseAvxOps.SpMultAddFlops", 0x003, 0x8 },
24 	{ "FpRetSseAvxOps.SpDivFlops", 0x003, 0x4 },
25 	{ "FpRetSseAvxOps.SpMultFlops", 0x003, 0x2 },
26 	{ "FpRetSseAvxOps.SpAddSubFlops", 0x003, 0x1 },
27 	{ "FpNumMovElimScalOp", 0x004, 0 },
28 	{ "FpNumMovElimScalOp.Optimized", 0x004, 0x8 },
29 	{ "FpNumMovElimScalOp.OptPotential", 0x004, 0x4 },
30 	{ "FpNumMovElimScalOp.SseMovOpsElim", 0x004, 0x2 },
31 	{ "FpNumMovElimScalOp.SseMovOps", 0x004, 0x1 },
32 	{ "FpRetiredSerOps", 0x005, 0 },
33 	{ "FpRetiredSerOps.X87CtrlRet", 0x005, 0x8 },
34 	{ "FpRetiredSerOps.X87BotRet", 0x005, 0x4 },
35 	{ "FpRetiredSerOps.SseCtrlRet", 0x005, 0x2 },
36 	{ "FpRetiredSerOps.SseBotRet", 0x005, 0x1 },
37 	{ "LsBadStatus2", 0x024, 0 },
38 	{ "LsBadStatus2.StlfNoData", 0x024, 0x4 },
39 	{ "LsBadStatus2.StliOther", 0x024, 0x2 },
40 	{ "LsLocks", 0x025, 0 },
41 	{ "LsRetClClush", 0x026, 0 },
42 	{ "LsRetCpuid", 0x027, 0 },
43 	{ "LsDispatch", 0x029, 0 },
44 	{ "LsSmiRx", 0x02B, 0 },
45 	{ "LsSTLF", 0x035, 0 },
46 	{ "LsStCommitCancel2", 0x037, 0 },
47 	{ "LsStCommitCancel2.StCommitCancelWcbFull", 0x037, 0x1 },
48 	{ "LsDcAccesses", 0x040, 0 },
49 	{ "LsRefillsFromSys", 0x043, 0 },
50 	{ "LsRefillsFromSys.LS_MABRESP_RMT_DRAM", 0x043, 0x40 },
51 	{ "LsRefillsFromSys.LS_MABRESP_RMT_CACHE", 0x043, 0x10 },
52 	{ "LsRefillsFromSys.LS_MABRESP_LCL_DRAM", 0x043, 0x8 },
53 	{ "LsRefillsFromSys.LS_MABRESP_LCL_CACHE", 0x043, 0x2 },
54 	{ "LsRefillsFromSys.MABRESP_LCL_L2", 0x043, 0x1 },
55 	{ "LsL1DTlbMiss", 0x045, 0 },
56 	{ "LsL1DTlbMiss.TlbReload1GL2Miss", 0x045, 0x80 },
57 	{ "LsL1DTlbMiss.TlbReload2ML2Miss", 0x045, 0x40 },
58 	{ "LsL1DTlbMiss.TlbReload32KL2Miss", 0x045, 0x20 },
59 	{ "LsL1DTlbMiss.TlbReload4KL2Miss", 0x045, 0x10 },
60 	{ "LsL1DTlbMiss.TlbReload1GL2Hit", 0x045, 0x8 },
61 	{ "LsL1DTlbMiss.TlbReload2ML2Hit", 0x045, 0x4 },
62 	{ "LsL1DTlbMiss.TlbReload32KL2Hit", 0x045, 0x2 },
63 	{ "LsL1DTlbMiss.TlbReload4KL2Hit", 0x045, 0x1 },
64 	{ "LsTablewalker", 0x046, 0 },
65 	{ "LsTablewalker.PerfMonTablewalkAllocIside1", 0x046, 0x8 },
66 	{ "LsTablewalker.PerfMonTablewalkAllocIside0", 0x046, 0x4 },
67 	{ "LsTablewalker.PerfMonTablewalkAllocDside1", 0x046, 0x2 },
68 	{ "LsTablewalker.PerfMonTablewalkAllocDside0", 0x046, 0x1 },
69 	{ "LsMisalAccesses", 0x047, 0 },
70 	{ "LsPrefInstrDisp", 0x04B, 0 },
71 	{ "LsPrefInstrDisp.PrefetchNTA", 0x04B, 0x4 },
72 	{ "LsPrefInstrDisp.StorePrefetchW", 0x04B, 0x2 },
73 	{ "LsPrefInstrDisp.LoadPrefetchW", 0x04B, 0x1 },
74 	{ "LsInefSwPref", 0x052, 0 },
75 	{ "LsInefSwPref.MabMchCnt", 0x052, 0x2 },
76 	{ "LsInefSwPref.DataPipeSwPfDcHit", 0x052, 0x1 },
77 	{ "LsSwPfDcFills", 0x059, 0 },
78 	{ "LsSwPfDcFills.LS_MABRESP_RMT_DRAM", 0x059, 0x40 },
79 	{ "LsSwPfDcFills.LS_MABRESP_RMT_CACHE", 0x059, 0x10 },
80 	{ "LsSwPfDcFills.LS_MABRESP_LCL_DRAM", 0x059, 0x8 },
81 	{ "LsSwPfDcFills.LS_MABRESP_LCL_CACHE", 0x059, 0x2 },
82 	{ "LsSwPfDcFills.MABRESP_LCL_L2", 0x059, 0x1 },
83 	{ "LsHwPfDcFills", 0x05A, 0 },
84 	{ "LsHwPfDcFills.LS_MABRESP_RMT_DRAM", 0x05A, 0x40 },
85 	{ "LsHwPfDcFills.LS_MABRESP_RMT_CACHE", 0x05A, 0x10 },
86 	{ "LsHwPfDcFills.LS_MABRESP_LCL_DRAM", 0x05A, 0x8 },
87 	{ "LsHwPfDcFills.LS_MABRESP_LCL_CACHE", 0x05A, 0x2 },
88 	{ "LsHwPfDcFills.MABRESP_LCL_L2", 0x05A, 0x1 },
89 	{ "LsTwDcFills", 0x05B, 0 },
90 	{ "LsTwDcFills.LS_MABRESP_RMT_DRAM", 0x05B, 0x40 },
91 	{ "LsTwDcFills.LS_MABRESP_RMT_CACHE", 0x05B, 0x10 },
92 	{ "LsTwDcFills.LS_MABRESP_LCL_DRAM", 0x05B, 0x8 },
93 	{ "LsTwDcFills.LS_MABRESP_LCL_CACHE", 0x05B, 0x2 },
94 	{ "LsTwDcFills.MABRESP_LCL_L2", 0x05B, 0x1 },
95 	{ "LsNotHaltedCyc", 0x076, 0 },
96 	{ "IcFw32", 0x080, 0 },
97 	{ "IcFw32Miss", 0x081, 0 },
98 	{ "IcCacheFillL2", 0x082, 0 },
99 	{ "IcCacheFillSys", 0x083, 0 },
100 	{ "BpL1TlbMissL2Hit", 0x084, 0 },
101 	{ "BpL1TlbMissL2Miss", 0x085, 0 },
102 	{ "IcFetchStall", 0x087, 0 },
103 	{ "IcFetchStall.IcStallDqEmpty", 0x087, 0x2 },
104 	{ "IcFetchStall.IcStallBackPressure", 0x087, 0x1 },
105 	{ "BpL1BTBCorrect", 0x08A, 0 },
106 	{ "BpL2BTBCorrect", 0x08B, 0 },
107 	{ "IcCacheInval", 0x08C, 0 },
108 	{ "IcCacheInval.L2InvalidatingProbe", 0x08C, 0x2 },
109 	{ "IcCacheInval.FillInvalidated", 0x08C, 0x1 },
110 	{ "BpTlbRel", 0x099, 0 },
111 	{ "IcOcModeSwitch", 0x28A, 0 },
112 	{ "IcOcModeSwitch.OcIcModeSwitch", 0x28A, 0x2 },
113 	{ "IcOcModeSwitch.IcOcModeSwitch", 0x28A, 0x1 },
114 	{ "DeDisDispatchTokenStalls0", 0x0AF, 0 },
115 	{ "DeDisDispatchTokenStalls0.RetireTokenStall", 0x0AF, 0x40 },
116 	{ "DeDisDispatchTokenStalls0.AGSQTokenStall", 0x0AF, 0x20 },
117 	{ "DeDisDispatchTokenStalls0.ALUTokenStall", 0x0AF, 0x10 },
118 	{ "DeDisDispatchTokenStalls0.ALSQ3_0_TokenStall", 0x0AF, 0x8 },
119 	{ "DeDisDispatchTokenStalls0.ALSQ3TokenStall", 0x0AF, 0x4 },
120 	{ "DeDisDispatchTokenStalls0.ALSQ2TokenStall", 0x0AF, 0x2 },
121 	{ "DeDisDispatchTokenStalls0.ALSQ1TokenStall", 0x0AF, 0x1 },
122 	{ "ExRetInstr", 0x0C0, 0 },
123 	{ "ExRetCops", 0x0C1, 0 },
124 	{ "ExRetBrn", 0x0C2, 0 },
125 	{ "ExRetBrnMisp", 0x0C3, 0 },
126 	{ "ExRetBrnTkn", 0x0C4, 0 },
127 	{ "ExRetBrnTknMisp", 0x0C5, 0 },
128 	{ "ExRetBrnFar", 0x0C6, 0 },
129 	{ "ExRetBrnResync", 0x0C7, 0 },
130 	{ "ExRetNearRet", 0x0C8, 0 },
131 	{ "ExRetNearRetMispred", 0x0C9, 0 },
132 	{ "ExRetBrnIndMisp", 0x0CA, 0 },
133 	{ "ExRetMmxFpInstr", 0x0CB, 0 },
134 	{ "ExRetMmxFpInstr.SseInstr", 0x0CB, 0x4 },
135 	{ "ExRetMmxFpInstr.MmxInstr", 0x0CB, 0x2 },
136 	{ "ExRetMmxFpInstr.X87Instr", 0x0CB, 0x1 },
137 	{ "ExRetCond", 0x0D1, 0 },
138 	{ "ExDivBusy", 0x0D3, 0 },
139 	{ "ExDivCount", 0x0D4, 0 },
140 	{ "ExTaggedIbsOps", 0x1CF, 0 },
141 	{ "ExTaggedIbsOps.IbsCountRollover", 0x1CF, 0x4 },
142 	{ "ExTaggedIbsOps.IbsTaggedOpsRet", 0x1CF, 0x2 },
143 	{ "ExTaggedIbsOps.IbsTaggedOps", 0x1CF, 0x1 },
144 	{ "ExRetFusBrnchInst", 0x1D0, 0 },
145 	{ "L2RequestG1", 0x060, 0 },
146 	{ "L2RequestG1.RdBlkL", 0x060, 0x80 },
147 	{ "L2RequestG1.RdBlkX", 0x060, 0x40 },
148 	{ "L2RequestG1.LsRdBlkC_S", 0x060, 0x20 },
149 	{ "L2RequestG1.CacheableIcRead", 0x060, 0x10 },
150 	{ "L2RequestG1.ChangeToX", 0x060, 0x8 },
151 	{ "L2RequestG1.PrefetchL2", 0x060, 0x4 },
152 	{ "L2RequestG1.L2HwPf", 0x060, 0x2 },
153 	{ "L2RequestG1.OtherRequests", 0x060, 0x1 },
154 	{ "L2RequestG2", 0x061, 0 },
155 	{ "L2RequestG2.Group1", 0x061, 0x80 },
156 	{ "L2RequestG2.LsRdSized", 0x061, 0x40 },
157 	{ "L2RequestG2.LsRdSizedNC", 0x061, 0x20 },
158 	{ "L2RequestG2.IcRdSized", 0x061, 0x10 },
159 	{ "L2RequestG2.IcRdSizedNC", 0x061, 0x8 },
160 	{ "L2RequestG2.SmcInval", 0x061, 0x4 },
161 	{ "L2RequestG2.BusLocksOriginator", 0x061, 0x2 },
162 	{ "L2RequestG2.BusLocksResponses", 0x061, 0x1 },
163 	{ "L2Latancy", 0x062, 0 },
164 	{ "L2Latancy.L2CyclesWaitingOnFills", 0x062, 0x1 },
165 	{ "L2WbcReq", 0x063, 0 },
166 	{ "L2WbcReq.WcbWrite", 0x063, 0x40 },
167 	{ "L2WbcReq.WcbClose", 0x063, 0x20 },
168 	{ "L2WbcReq.CacheLineFlush", 0x063, 0x10 },
169 	{ "L2WbcReq.I_LineFlush", 0x063, 0x8 },
170 	{ "L2WbcReq.ZeroByteStore", 0x063, 0x4 },
171 	{ "L2WbcReq.LocalIcClr", 0x063, 0x2 },
172 	{ "L2WbcReq.CLZero", 0x063, 0x1 },
173 	{ "L2CacheReqStat", 0x064, 0 },
174 	{ "L2CacheReqStat.LsRdBlkCS", 0x064, 0x80 },
175 	{ "L2CacheReqStat.LsRdBlkLHitX", 0x064, 0x40 },
176 	{ "L2CacheReqStat.LsRdBlkLHitS", 0x064, 0x20 },
177 	{ "L2CacheReqStat.LsRdBlkX", 0x064, 0x10 },
178 	{ "L2CacheReqStat.LsRdBlkC", 0x064, 0x8 },
179 	{ "L2CacheReqStat.IcFillHitX", 0x064, 0x4 },
180 	{ "L2CacheReqStat.IcFillHitS", 0x064, 0x2 },
181 	{ "L2CacheReqStat.IcFillMiss", 0x064, 0x1 },
182 	{ "L2FillPending", 0x06D, 0 },
183 	{ NULL, 0, 0 }
184 };
185